JP6583169B2 - Trench gate type semiconductor device - Google Patents

Description

  The present invention relates to a trench gate type semiconductor device.

  In the power semiconductor element disclosed in Patent Document 1, as shown in FIG. 13, a first conductivity type semiconductor layer (n drift layer) 100 and a first conductivity type electrically connected to the first conductivity type semiconductor layer 100. Main electrode (drain electrode) 101, a first second conductivity type semiconductor layer (p well region) 102 selectively formed on the surface of the first conductivity type semiconductor layer 100, and a first second conductivity type. A second main electrode (source electrode) 103 electrically connected to the semiconductor layer 102 and a plurality of second conductive semiconductor layers 104 with a plurality of potentials embedded in the first conductive semiconductor layer 100 are provided. Have. A groove 105 is formed from the surface of the element so as to reach the second second conductivity type semiconductor layer 104 at the terminal portion of the element.

JP 2001-15744 A

By the way, as shown by the phantom line in FIG. 13, if the withstand voltage is held so that the terminal groove (trench) 105 reaches the high-concentration first conductive semiconductor layer (n ⁺ substrate) 106, the terminal groove (trench) is obtained. The inner side Ain and the outer side Aout from 105 are electrically insulated and separated. In this case, there is a concern that the electric field concentrates at the boundary corner portion S1 with the terminal groove (trench) 105 in the first second conductivity type semiconductor layer (p-well region) 102, thereby causing a decrease in breakdown voltage. The

  An object of the present invention is to provide a trench gate type semiconductor device capable of suppressing electric field concentration and preventing a decrease in breakdown voltage.

  In the first aspect of the present invention, the low-concentration first conductive semiconductor layer is formed on the high-concentration first conductive semiconductor layer in contact with the high-concentration first conductive semiconductor layer in the thickness direction of the semiconductor substrate. And a second conductive semiconductor layer is formed on the low-concentration first conductive semiconductor layer so as to be in contact with the low-concentration first conductive semiconductor layer, and is formed on a surface layer portion of the second conductive semiconductor layer. A trench gate type semiconductor in which a gate electrode is arranged through a gate insulating film inside a gate trench that penetrates the first conductive type semiconductor region and the second conductive type semiconductor layer under the first conductive type semiconductor region. In the active region of the semiconductor substrate, the gate trench is formed deeper than an interface between the high-concentration first conductive semiconductor layer and the low-concentration first conductive semiconductor layer, and the gate trench is formed. A junction between the first conductive type semiconductor and the second conductive type semiconductor is located above the interface between the high concentration first conductive type semiconductor layer and the low concentration first conductive type semiconductor layer. A termination trench extending around the active region in the semiconductor substrate, the termination trench being deeper than an interface between the high concentration first conductivity type semiconductor layer and the low concentration first conductivity type semiconductor layer; A junction between the first conductivity type semiconductor and the second conductivity type semiconductor is formed on at least a side surface on the bottom side of the termination trench, and the high concentration first conductivity type semiconductor layer and the low concentration first conductivity type semiconductor layer are formed. The termination trenches are formed more than double around the active region, and at least in the termination trenches other than the outermost periphery of the termination trenches formed more than double. In one place, and summarized in that with a dividing region which continuously the low concentration first conductivity type semiconductor layer together.

  According to the first aspect of the present invention, the termination trench surrounding the periphery of the active region in the semiconductor substrate is formed deeper than the interface between the high concentration first conductivity type semiconductor layer and the low concentration first conductivity type semiconductor layer. The junction between the first conductivity type semiconductor and the second conductivity type semiconductor is at the interface between the high-concentration first conductivity type semiconductor layer and the low-concentration first conductivity type semiconductor layer at least on the side surface on the bottom side of the termination trench. It is extended upward from. In addition, the termination trench is formed more than double around the active region. Here, the potential difference between the potential of the high-concentration first conductivity type semiconductor layer and the potential of the second conductivity type semiconductor layer is held in the innermost termination trench among the termination trenches formed more than double. Although electric field concentration is about to occur, at least one of the terminal trenches other than the outermost periphery of the double or more terminal trenches is formed with a dividing region in which the low-concentration first conductivity type semiconductor layers are continuous with each other. Therefore, the concentration of the electric field is suppressed in the innermost terminal trench, and the breakdown voltage is prevented from being lowered. In this way, the electric field concentration can be suppressed and the breakdown voltage can be prevented from decreasing.

  In the active region of the semiconductor substrate, the gate trench is formed deeper than the interface between the high-concentration first conductivity type semiconductor layer and the low-concentration first conductivity type semiconductor layer, and on the side surface on the bottom side of the gate trench, The junction between the first conductivity type semiconductor and the second conductivity type semiconductor extends upward from the interface between the high concentration first conductivity type semiconductor layer and the low concentration first conductivity type semiconductor layer, and the low concentration first current flows. The narrowing of the width of the one-conductivity-type semiconductor layer is avoided, and the breakdown voltage can be improved without deteriorating the on-resistance.

  According to a second aspect of the present invention, in the trench gate type semiconductor device according to the first aspect of the present invention, it is preferable that all of the terminal trenches in the terminal trench formed more than double have the dividing regions.

  As described in claim 3, in the trench gate type semiconductor device according to claim 1 or 2, a plurality of the dividing regions are provided per one termination trench in the double or more termination trenches, and It is preferable that the active regions are evenly arranged at two or more locations.

  The trench gate type semiconductor device according to any one of claims 1 to 3, wherein the termination trench surrounding the periphery of the active region in the semiconductor substrate has the dividing region in a straight portion. It is good to have.

  According to the present invention, electric field concentration can be suppressed and a decrease in breakdown voltage can be prevented.

The top view which shows typically the trench gate type MOSFET in embodiment. The longitudinal cross-sectional view in the AA line of FIG. The longitudinal cross-sectional view in the BB line of FIG. The longitudinal cross-sectional view in the CC line of FIG. (A) is a figure which shows the equipotential line in the AA line of FIG. 1, (b) is a figure which shows the equipotential line in the BB line of FIG. The schematic longitudinal cross-sectional view for demonstrating the manufacturing process of trench gate type MOSFET. The schematic longitudinal cross-sectional view for demonstrating the manufacturing process of trench gate type MOSFET. The schematic longitudinal cross-sectional view for demonstrating the manufacturing process of trench gate type MOSFET. The schematic longitudinal cross-sectional view for demonstrating the manufacturing process of trench gate type MOSFET. The schematic longitudinal cross-sectional view of the trench gate type MOSFET of another example. The top view of the trench gate type MOSFET of a comparative example. The longitudinal cross-sectional view in the DD line of FIG. 1 is a schematic longitudinal sectional view of a semiconductor device for explaining background art and problems.

Hereinafter, an embodiment in which the present invention is embodied in a trench gate type MOSFET will be described with reference to the drawings.
1, 2, 3, and 4 show a schematic configuration of a trench gate type MOSFET (chip) 10 as a trench gate type semiconductor device, and are AA lines, BB lines, and CC lines in FIG. Each cross-sectional structure taken along the line is shown in FIGS. The trench gate type MOSFET (chip) 10 is a vertical MOSFET in which a plurality of gate trenches 17 are formed in a silicon substrate 11. As shown in FIG. 1, the gate trenches 17 extend linearly, and the gate trenches 17 are arranged in parallel at a certain distance.

As shown in FIG. 2, the silicon substrate 11 is formed in the order of an n ⁺ silicon layer 12, an n silicon layer 13, and a p silicon layer (channel formation region) 14 from the bottom. An n ⁺ source region 15 is formed in the surface layer portion of the p silicon layer 14. A plurality of gate trenches 17 are arranged in parallel in the silicon substrate 11. The side surface of the gate trench 17 is formed perpendicular to the upper surface of the silicon substrate 11.

Each gate trench 17 passes through the n ⁺ source region 15 and the p silicon layer 14 and reaches the n silicon layer 13. A polysilicon gate electrode 19 is disposed (embedded) on the inner surface of the gate trench 17 via a gate oxide film 18. A drain electrode 21 is formed on the lower surface (back surface) of the silicon substrate 11. The upper surface of the polysilicon gate electrode 19 is covered with an insulating film (not shown). An aluminum source electrode 20 is disposed on the upper surface of the silicon substrate 11, and the aluminum source electrode 20 is electrically connected to the n ⁺ source region 15 and the contact p ⁺ region 16 formed in the surface layer portion of the p silicon layer 14. .

Thus, the low concentration first conductivity type is in contact with the n ⁺ silicon layer 12 on the n ⁺ silicon layer 12 as the high concentration first conductivity type semiconductor layer in the thickness direction of the silicon substrate 11 as the semiconductor substrate. An n silicon layer 13 is formed as a semiconductor layer. A p silicon layer 14 as a second conductivity type semiconductor layer is formed on the n silicon layer 13 so as to be in contact with the n silicon layer 13. Furthermore, a gate insulating film is formed inside the gate trench 17 penetrating the n ⁺ source region 15 as the first conductivity type semiconductor region formed in the surface layer portion of the p silicon layer 14 and the p silicon layer 14 below the n ⁺ source region 15. A polysilicon gate electrode 19 as a gate electrode is arranged through a gate oxide film 18 as a gate electrode.

Further, in the active region of the silicon substrate 11, the gate trench 17 is formed deeper than the interface between the n ⁺ silicon layer 12 and the n silicon layer 13. That is, the gate trenches 17, to the interface between the ^{n +} silicon layer 12 and the n silicon layer 13, or is formed deeper than the interface between the ^{n +} silicon layer 12 and the n silicon layer 13.

Further, a p-type impurity doped silicon oxide film 22 as a second conductivity type impurity doped oxide film is buried on the bottom side of the gate trench 17. A p silicon region 23 as a second conductivity type semiconductor region is formed on the side surface of the p type impurity doped silicon oxide film 22. The p silicon region 23 is formed by the diffusion of impurities from the p-type impurity doped silicon oxide film 22. The p silicon region 23 extends upward from the interface between the n ⁺ silicon layer 12 and the n silicon layer 13. The junction between the p silicon region 23 and the n silicon layer 13 is a pn junction 24, and this pn junction 24 is formed on the side surface on the bottom side of the gate trench 17 between the n ⁺ silicon layer 12 and the n silicon layer 13. It extends upward from the interface. A gate oxide film 18 is formed on the p-type impurity doped silicon oxide film 22.

Thus, a pn junction 24 as a junction between the first conductivity type semiconductor and the second conductivity type semiconductor is formed between the n ⁺ silicon layer 12 and the n silicon layer 13 on the side surface on the bottom side of the gate trench 17. It extends upward from the interface. More specifically, the pn junction 24 is formed by the p silicon region 23 and the n silicon layer 13 diffused from the p-type impurity doped silicon oxide film 22 buried on the bottom side of the gate trench 17.

The aluminum source electrode 20 is set to the ground potential, and a high voltage (for example, 100 V) is applied to the drain electrode 21.
Further, as shown in FIGS. 1 and 2, the silicon substrate 11 has termination trenches (trench rings) 30, 31 and 32 surrounding the periphery of the active region. That is, the termination region is formed around the active region, and the termination trenches 30, 31, and 32 are formed so as to surround the active region in the termination region. The termination trenches 30, 31, and 32 are formed deeper than the interface between the n ⁺ silicon layer 12 and the n silicon layer 13.

A p-type impurity doped silicon oxide film 34 as a second conductivity type impurity doped oxide film is buried on the bottom side of each termination trench 30, 31, 32. A p silicon region 36 as a second conductivity type semiconductor region is formed on the side surface of the p type impurity doped silicon oxide film 34. The p silicon region 36 is formed by the diffusion of impurities from the p-type impurity doped silicon oxide film 34. The p silicon region 36 extends upward from the interface between the n ⁺ silicon layer 12 and the n silicon layer 13. The junction between the p silicon region 36 and the n silicon layer 13 is a pn junction 37, and the pn junction 37 is formed on the side surface on the bottom side of the termination trenches 30, 31, 32 on the n ⁺ silicon layer 12 and the n silicon. It extends upward from the interface with the layer 13. Each termination trench 30, 31, 32 is filled with a silicon oxide film 35.

  As shown in FIG. 1, the termination trenches (30, 31, 32) are formed more than double around the active region, and at least of the termination trenches (30, 31, 32) formed more than double. In the termination trenches 30 and 31 other than the outermost periphery, there are divided regions 40 to 43 and 50 to 53 for continuing the n silicon layers 13 at least at one place. In other words, at least one of the termination trenches excluding the outermost termination trench has at least one divided region 40-43, 50-53, 60-63 in which the n silicon layers 13 are continuous.

  As shown in FIG. 1 and FIG. 4, all the termination trenches 30, 31, 32 in the termination trenches 30, 31, 32 formed more than double have division regions 40 to 43, 50 to 53, 60 to 63. . The dividing regions 40 to 43, 50 to 53, and 60 to 63 have a plurality of terminal trenches 30, 31, and 32 formed in double or more per one end trench, and at two or more locations with respect to the active region. Evenly arranged. Specifically, they are arranged point-symmetrically with respect to the center O (see FIG. 1) of the active region. Specifically, as shown in FIG. 1, the gate trenches 17 are linearly extended in one direction in the active region, and a plurality of gate trenches 17 are formed in parallel to each other. Termination trenches 30, 31, and 32 are formed in a square shape at the periphery, and the termination trenches 30, 31, and 32 have four straight portions and arc-shaped corner portions, and the dividing regions 40 to 40 are formed at the central portions of the four straight portions. 43, 50-53, 60-63 are formed. Further, the divided regions 40 to 43 of the termination trench 30, the divided regions 50 to 53 of the termination trench 31, and the divided regions 60 to 63 of the termination trench 32 are aligned. That is, in FIG. 1, the divided regions 40, 50, 60 are arranged in the right direction, the divided regions 41, 51, 61 are arranged in the downward direction, and the divided regions 42, 52, 62 are arranged in the left direction. The divided regions 43, 53, and 63 are aligned in the upward direction. As described above, the termination trenches 30, 31, and 32 surrounding the active region in the silicon substrate 11 have the dividing regions 40 to 43, 50 to 53, and 60 to 63 in the straight portions.

Next, a manufacturing method will be described.
As shown in FIG. 6, a silicon substrate 11 having an n silicon layer 13 formed on an n ⁺ silicon layer 12 is prepared. A p silicon layer 14 is formed on the n silicon layer 13 and the p silicon layer 14 is formed. An n ⁺ source region 15 and a contact p ⁺ region 16 are formed in the surface layer portion. Then, a gate trench 17 whose side surface is perpendicular to the upper surface of the silicon substrate 11 is formed. The depth of the gate trench 17 is greater than or equal to the interface between the n ⁺ silicon layer 12 and the n silicon layer 13. That is, the gate trenches 17, to the interface between the ^{n +} silicon layer 12 and the n silicon layer 13, or deeper than the interface between the ^{n +} silicon layer 12 and the n silicon layer 13. More specifically, the gate trench 17 is formed deeper than the maximum manufacturing tolerance (manufacturing variation) Δd with respect to the interface between the n ⁺ silicon layer 12 and the n silicon layer 13.

By forming the gate trench 17 in this manner, the gate trench 17 can be at least deep enough to reach the interface between the n ⁺ silicon layer 12 and the n silicon layer 13 even if the gate trench depth varies during manufacturing. .

Simultaneously with the formation of the gate trench 17, termination trenches 30, 31, and 32 surrounding the periphery of the active region in the silicon substrate 11 are formed. The termination trenches 30, 31, and 32 are formed deeper than the interface between the n ⁺ silicon layer 12 and the n silicon layer 13.

  Subsequently, as shown in FIG. 7, a p-type impurity doped silicon oxide film 22 is buried in the bottom of the gate trench 17, and a p-type impurity doped silicon oxide film 34 is buried in the bottom of the termination trenches 30, 31, 32. More specifically, a p-type impurity doped silicon oxide film (22, 34) is deposited on the upper surface of the silicon substrate 11 including the inside of the gate trench 17 and the termination trenches 30, 31, 32, and the gate trench 17 is etched back. The p-type impurity doped silicon oxide films (22, 34) in the inner and termination trenches 30, 31, 32 are left and the others are removed.

Further, as shown in FIG. 8, p-type impurities are diffused from the p-type impurity doped silicon oxide films (22, 34) into the n silicon layer 13 by heat treatment to form p silicon regions (23, 36). That is, p-type impurities are diffused from the p-type impurity-doped silicon oxide films (22, 34) to form p-silicon regions (23, 36). Thereby, a pn junction 24 formed at the interface between the p silicon region 23 and the n silicon layer 13 is formed so as to extend upward from the interface between the n ⁺ silicon layer 12 and the n silicon layer 13. Further, a pn junction portion 37 formed at the interface between the p silicon region 36 and the n silicon layer 13 is formed so as to extend upward from the interface between the n ⁺ silicon layer 12 and the n silicon layer 13.

Note that when the p-type impurity is diffused from the p-type impurity-doped silicon oxide film (22, 34) to form the p-silicon region (23, 36), the p-type impurity-doped silicon oxide film (22, 34) is formed. 34), p-type impurities are also diffused below, but not so much that the n ⁺ silicon layer 12 is inverted into the p region.

In this way, the pn junction portion 37 extends upward from the interface between the n ⁺ silicon layer 12 and the n silicon layer 13 on the side surface on the bottom side of the termination trenches 30, 31, 32. The termination trenches 30, 31, and 32 are formed in triplicate around the active region. In the triple termination trenches 30, 31, and 32, the division regions 40 to 43 that connect the n silicon layers 13 to each other at four locations. , 50-53, 60-63.

  Then, as shown in FIG. 9, a gate oxide film 18 is formed inside the gate trench 17 in the active region. Further, a polysilicon gate electrode 19 is disposed in the gate trench 17 through a gate oxide film 18. The termination trenches 30, 31, 32 are filled with a silicon oxide film 35.

  Subsequently, as shown in FIG. 2, the drain electrode 21 is formed on the back surface of the silicon substrate 11, and the aluminum source electrode 20 is disposed at a predetermined position on the upper surface of the silicon substrate 11. As a result, the trench gate type MOSFET 10 is manufactured.

Next, the operation will be described.
As shown in FIG. 2, it is possible to secure the width W1 of the n silicon layer 13 (n-type region) through which current flows without increasing the width of the p silicon region 23 and improve the breakdown voltage without deteriorating the on-resistance. it can.

That is, the gate trench 17 is first dug up to a depth reaching the interface between the n ⁺ silicon layer 12 and the n silicon layer 13, and the p-type impurity doped silicon oxide film 22 which is an oxide film containing p-type impurities is buried in the lateral direction. By diffusing the film, it is possible to make the p-type region straight and long without expanding the width of the p-type region. That is, without narrowing the width W1 of the n silicon layer 13 through which current actually flows between adjacent gate electrodes 19 (gate trenches 17), the pn junction 24 can be formed in a vertically long shape, and the breakdown voltage is not degraded without deteriorating the on-resistance. Is improved.

  In the active region, the drain-source breakdown voltage is maintained in the p silicon region 23 beside the gate trench 17. A gate trench 17 is used to form the p silicon region 23. On the other hand, termination trenches 30, 31, and 32 are formed as termination structures.

  In FIG. 5A, an equipotential line when a voltage is applied between the drain and the source along the AA line in FIG. 1 is indicated by a broken line, and in FIG. An equipotential line when a voltage is applied between the drain and the source on the -B line is shown. 5A and 5B, L20 is an equipotential line at the source potential, L23 is an equipotential line at the drain potential, and L21 and L22 are intermediate potentials between the source potential and the drain potential. Are equipotential lines. 5A and 5B, the equipotential line L20 at the source potential extends to the innermost side of the termination region, and the equipotential line L23 at the drain potential extends to the outermost side of the termination region. It can be seen that the equipotential lines L21 and L22 at the intermediate potential are spread in an evenly distributed state between the innermost side and the outermost side of the termination region. That is, the depletion layer can be expanded in the termination region. At this time, the p silicon region 36 formed on the side surfaces of the termination trenches 30, 31, 32 is used.

11 and 12 are comparative examples, and FIG. 12 shows a longitudinal section taken along line DD in FIG. 11 showing a plan view.
In the comparative example shown in FIGS. 11 and 12, endless termination trenches (130, 131, 132) are formed in triplicate.

  In FIG. 12, an equipotential line when a voltage is applied between the drain and the source is indicated by a broken line. In FIG. 12, L30 is an equipotential line at the source potential, L33 is an equipotential line at the drain potential, and L31 and L32 are equipotential lines at an intermediate potential between the source potential and the drain potential.

  From FIG. 12, the equipotential line L30 at the source potential extends inwardly inside the innermost termination trench 130, and the equipotential line L33 at the drain potential extends outwardly in the innermost termination trench 130, It can be seen that equipotential lines L31 and L32 at an intermediate potential between the source potential and the drain potential are spread inside the innermost termination trench 130.

  Thus, the electric field concentrates at the boundary corner portion S2 with the termination trench 131 in the p silicon layer (channel formation region) 14. That is, the electric field strength due to the potential difference between the vertical direction and the horizontal direction is combined, and the electric field strength is increased. As a result, the breakdown voltage decreases.

  In the present embodiment shown in FIGS. 5A and 5B, the termination trenches 30, 31, and 32 have dividing regions 40 to 43, 50 to 53, and 60 to 63. As a result, the lateral potential gradient becomes gentle, so that excessive concentration of the electric field strength is eliminated.

  1 and 4, the distance L10 at the time of division is controlled to adjust the holding voltage per one for the termination trenches (30, 31, 32) (adjust so that the depletion layer spreads over a wide range). . That is, the optimum distance (division width) L10 corresponding to the extension of the depletion layer in the lateral direction may be set. In FIG. 1, the holding voltage is adjusted by adjusting the distance L11 between the inner and outer terminal trenches (adjusted so that the depletion layer spreads over a wide range).

  In this way, a plurality of termination trenches (30, 31, 32) that maintain a breakdown voltage in the termination region are arranged, and each is divided at an appropriate distance. By doing so, the holding voltage per one termination trench (30, 31, 32) can be controlled, and the electric field strength can be dispersed to prevent a decrease in breakdown voltage.

According to the above embodiment, the following effects can be obtained.
(1) As a structure of the trench gate type MOSFET, as shown in FIG. 2, the gate trench 17 is formed deeper than the interface between the n ⁺ silicon layer 12 and the n silicon layer 13 in the active region in the silicon substrate 11, and the gate A pn junction 24 extends upward from the interface between the n ⁺ silicon layer 12 and the n silicon layer 13 on the side surface on the bottom side of the trench 17.

Therefore, the width W1 of the n silicon layer 13 through which the current flows is prevented from being narrowed, and the breakdown voltage can be improved without deteriorating the on-resistance.
Further, as shown in FIG. 1, the silicon substrate 11 has termination trenches 30, 31, and 32 surrounding the periphery of the active region. As shown in FIG. 2, the termination trenches 30, 31, and 32 are n ⁺ silicon layers. 12 is formed deeper than the interface between the n ⁺ silicon layer 13, and a pn junction 37 is formed at least on the side surface on the bottom side of the termination trenches 30, 31, 32 from the interface between the n ⁺ silicon layer 12 and the n silicon layer 13. It extends upward. As shown in FIGS. 1 and 2, the termination trenches 30, 31 and 32 are formed more than double around the active region, and at least the outermost periphery of the termination trenches 30, 31 and 32 formed more than double. In the other end trenches 30, 31, and 32, at least at one location, there are divided regions 40 to 43, 50 to 53, and 60 to 63 that allow the n silicon layers 13 to be continuous.

Therefore, the potential difference between the potential of the n ⁺ silicon layer 12 and the potential of the p silicon layer 14 is held in the innermost termination trench 30 among the termination trenches 30, 31, and 32 formed more than double. Although electric field concentration is about to occur, n silicon layers 13 are continuously arranged at least at one position in termination trenches 30 and 31 other than at least the outermost periphery among termination trenches 30, 31 and 32 formed in double or more. Since the divided regions 40 to 43 and 50 to 53 are provided, the concentration of the electric field is suppressed in the innermost terminal trench 30 and the breakdown voltage is prevented from being lowered. In this way, the electric field concentration can be suppressed and the breakdown voltage can be prevented from decreasing.

explain in detail.
In the power semiconductor element disclosed in Patent Document 1, as shown in FIG. 13, a second second conductive semiconductor layer having a polarity opposite to the first conductive semiconductor layer (n drift layer) 100 such as a planar MOS ( In the SuperFET structure having the floating semiconductor region (104), the terminal withstand voltage holding region is manufactured by the terminal groove (trench) 105, whereby the terminal withstand voltage holding region can be formed in a narrow range.

  Here, in FIG. 13, when the withstand voltage is held in the terminal groove (trench) 105, the inner side and the outer side of the terminal groove (trench) 105 are electrically insulated and separated. At that time, the potential Eout of the outer side Aout of the terminal groove (trench) 105 is substantially the same as the potential of the bottom portion 105 a of the terminal groove (trench) 105.

Therefore, as shown by the phantom line in FIG. 13, when the terminal groove (trench) 105 becomes deep enough to reach the high-concentration first conductive semiconductor layer (n ⁺ substrate) 106, the high-concentration first conductive semiconductor layer ( The potential difference between the potential (= drain potential) of the n ⁺ substrate 106 and the source potential is held in the terminal groove (trench) 105.

  Therefore, the vertical electric field strength component due to the potential rising from the front surface (source) to the back surface (drain) and the horizontal electrolytic strength component compressed to the distance of the terminal groove (trench) 105 are the terminal groove. There is a concern that the electric field strength is locally increased and the breakdown voltage is reduced.

On the other hand, this embodiment is as follows.
Termination trenches 30, 31, and 32 filled with an insulator reach the n ⁺ silicon layer 12, and there are vertically long p silicon regions 36 inside and outside thereof, and the termination trenches 30, 31, and 32 are divided to form n silicon. The layer 13 is connected so that the depletion layer is not blocked by at least the termination trench 30 at the time of withstand voltage, thereby reducing the concentration of the electric field. In order to easily extend the depletion layer to the side, the p silicon region 36 is arranged on the outer periphery with appropriate concentrations and intervals L12 and L13 (see FIG. 2).

  (2) As shown in FIG. 1, all the termination trenches 30, 31, 32 in the termination trenches 30, 31, 32 formed in double or more have the dividing regions 40 to 43, 50 to 53, 60 to 63. . Therefore, electric field concentration can be further suppressed and the breakdown voltage can be prevented from being lowered. That is, the maximum effect (suppression of electric field concentration / decrease in breakdown voltage) can be obtained.

  (3) As shown in FIG. 1, the dividing regions 40 to 43, 50 to 53, and 60 to 63 have a plurality of the terminal trenches 30, 31, and 32 formed more than double per one terminal trench, and These are evenly arranged at two or more locations with respect to the active area.

Therefore, electric field concentration can be further suppressed and the breakdown voltage can be prevented from being lowered.
(4) As shown in FIG. 1, the termination trenches 30, 31, and 32 surrounding the active region in the silicon substrate 11 have dividing regions 40 to 43, 50 to 53, and 60 to 63 in the straight line portions.

  Therefore, electric field concentration can be further suppressed and the breakdown voltage can be prevented from being lowered. That is, when the parting location is a straight line, the electric field concentration (decrease in breakdown voltage) can be suppressed as compared with the case where the parting region is formed at the corner.

(5) The method for manufacturing the trench gate type MOSFET includes a first step, a second step, and a third step.
In the first step, as shown in FIG. 6, the gate trench 17 and the termination trenches 30, 31, 32 are formed to have a depth greater than the interface between the n ⁺ silicon layer 12 and the n silicon layer 13.

In the second step, after the first step, as shown in FIG. 7, the p-type impurity doped silicon oxide films 22 and 34 are embedded in the gate trench 17 and the termination trenches 30, 31 and 32.
In the third step, after the second step, as shown in FIG. 8, p-type impurities are diffused from the p-type impurity-doped silicon oxide films 22 and 34 into the n-silicon layer 13 by heat treatment, and the pn junctions 24 and 37 are formed. Are formed so as to extend upward from the interface between the n ⁺ silicon layer 12 and the n silicon layer 13.

Thereby, the trench gate type MOSFET of the above (1) can be manufactured.
(6) In the first step in the above (5), the gate trench 17 and the termination trenches 30, 31, 32 are formed deeper than the interface between the n ⁺ silicon layer 12 and the n silicon layer 13. Thereby, the maximum manufacturing tolerance (wafer manufacturing error) about the depth of the gate trench 17 and the termination trenches 30, 31, 32 can be absorbed, and the trench gate type MOSFET of (1) can be manufactured.

The embodiment is not limited to the above, and may be embodied as follows, for example.
As shown in FIG. 10 instead of FIG. 2, the p silicon region 36 is extended to the surface of the silicon substrate 11 in the termination trenches 30, 31, 32, and the pn junction portion 37 is connected to the n ⁺ silicon layer 12, the n silicon layer 13, You may extend from the interface to the surface of the silicon substrate 11. In FIG. 10, the pn junction 37 is connected to the p silicon layer 14. In order to obtain such a configuration, for example, the p-type impurity doped silicon oxide film 34 in FIG. 7 is buried in the entire region in the depth direction of the termination trenches 30, 31, and 32, and the lateral diffusion processing described in FIG. Just do it. As described above, the pn junction 37 may be extended upward from the interface between the n ⁺ silicon layer 12 and the n silicon layer 13 on at least the side surface of the termination trenches 30, 31, and 32.

-Although the place to divide in a termination | terminus trench was a straight part, a corner part may be sufficient and a straight part and a corner part may be sufficient.
Although all the termination trenches 30, 31, and 32 are divided, the outermost termination trench 32 may not be divided.

  In FIG. 1, the divided regions 40 to 43 of the termination trench 30, the divided regions 50 to 53 of the termination trench 31, and the divided regions 60 to 63 of the termination trench 32 are aligned, but may not be aligned.

-Although the termination trench is formed in triple, it may be formed in double. Moreover, you may form a termination | terminus trench in quadruple or more.
The p-type impurity doped silicon oxide films 22 and 34 may be removed after forming the p silicon regions 23 and 36 as shown in FIG.

  The pn junctions 24 and 37 may be formed by the p-type silicon embedded in the gate trench 17 and the termination trenches 30, 31, and 32 and the n silicon layer 13. And after digging the termination trenches 30, 31, 32, p-type silicon may be buried. As described above, the pn junctions 24 and 37 as the junction between the first conductivity type semiconductor and the second conductivity type semiconductor are the second conductivity type impurity doped buried in the gate trench 17 and the termination trenches 30, 31 and 32. It may be formed of p-type silicon as a semiconductor and an n-silicon layer 13 as a low-concentration first conductivity type semiconductor layer. Note that the p-type impurity may be diffused in the lateral direction by performing heat treatment after the p-type silicon is embedded in the gate trench 17 and the termination trenches 30, 31, and 32. Further, the p-type silicon may be removed after the p-type impurity is diffused in the lateral direction in this way.

The p-type and n-type semiconductor conductivity types may be reversed.
The side surfaces of the gate trench 17 and the termination trenches 30, 31, and 32 are formed perpendicular to the upper surface of the silicon substrate 11, but the side surfaces of the gate trench 17 and the termination trenches 30, 31, and 32 are oblique to the upper surface of the silicon substrate 11 (V Character groove).

DESCRIPTION OF SYMBOLS 10 ... Trench gate type MOSFET, 11 ... Silicon substrate (semiconductor substrate), 12 ... n ⁺ silicon layer (high concentration 1st conductivity type semiconductor layer), 13 ... n silicon layer (low concentration 1st conductivity type semiconductor layer), 14 ... p silicon layer (second conductivity type semiconductor layer), 15 ... n ⁺ source region (first conductivity type semiconductor region), 17 ... gate trench, 18 ... gate oxide film (gate insulating film), 19 ... polysilicon gate electrode (Gate electrode), 22... P-type impurity doped silicon oxide film (second conductivity type impurity-doped oxide film), 23... P silicon region (second conductivity type semiconductor region), 24. (Junction between semiconductor and second conductivity type semiconductor), 30... Termination trench, 31... Termination trench, 32... Termination trench, 37 .. pn junction, 40, 41, 42, 43. , 52, 53 ... dividing region, 60, 61, 62, 63 ... dividing region.

Claims (4)

A low concentration first conductivity type semiconductor layer is formed on the high concentration first conductivity type semiconductor layer in contact with the high concentration first conductivity type semiconductor layer in the thickness direction of the semiconductor substrate, and the low concentration first conductivity type is formed. A second conductivity type semiconductor layer is formed on the type semiconductor layer so as to be in contact with the low-concentration first conductivity type semiconductor layer, and a first conductivity type semiconductor region formed on a surface layer portion of the second conductivity type semiconductor layer; A trench gate type semiconductor device comprising a gate electrode disposed through a gate insulating film inside a gate trench penetrating the second conductivity type semiconductor layer under the first conductivity type semiconductor region,
The gate trench is formed deeper than an interface between the high-concentration first conductive semiconductor layer and the low-concentration first conductive semiconductor layer in an active region of the semiconductor substrate;
A junction between the first conductivity type semiconductor and the second conductivity type semiconductor is formed on the side surface on the bottom side of the gate trench from the interface between the high concentration first conductivity type semiconductor layer and the low concentration first conductivity type semiconductor layer. Extended upwards,
A termination trench surrounding the periphery of the active region in the semiconductor substrate;
The termination trench is formed deeper than an interface between the high-concentration first conductive semiconductor layer and the low-concentration first conductive semiconductor layer;
A junction between the first conductivity type semiconductor and the second conductivity type semiconductor is an interface between the high concentration first conductivity type semiconductor layer and the low concentration first conductivity type semiconductor layer on at least a side surface on the bottom side of the termination trench. Extending upward from
The termination trench is formed more than double around the active region, and at least one of the termination trenches other than the outermost periphery of the termination trenches formed more than double, the low concentration first conductive A trench gate type semiconductor device characterized by having a dividing region in which type semiconductor layers are continuous.   2. The trench gate type semiconductor device according to claim 1, wherein all of the termination trenches in the termination trench formed more than double have the dividing region.   The divisional region includes a plurality of the dividing regions formed in the double or more terminal trenches, and is equally disposed at two or more locations with respect to the active region. 3. A trench gate type semiconductor device according to 1 or 2.   4. The trench gate type semiconductor device according to claim 1, wherein a termination trench surrounding an active region in the semiconductor substrate has the dividing region in a straight line portion. 5.

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