JP2013102213A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a structure having a plane orientation advantageous for manufacturing a super-junction wafer and for manufacturing a trench gate structure.SOLUTION: In an n-type semiconductor substrate 1 having a plane (100) as its surface, a plurality of first trenches 2 which extend in a direction <001> and have planes (010) and (0-10) as their side faces are formed. Each of the trenches 2 is buried with a p-type epitaxial layer 3 to manufacture a super-junction wafer. In the super-junction wafer, second trenches 4 extending in the direction <001> are formed. Each of the trenches 4 is buried with a gate insulating film 5 and a gate electrode 6 to manufacture a semiconductor element having a trench gate structure.

Description

  The present invention relates to a semiconductor element and a method for manufacturing the semiconductor element, and more particularly, to a MOSFET having a trench gate structure on the surface of a semiconductor layer in which first conductive type semiconductor regions and second conductive type semiconductor regions are alternately arranged. The present invention relates to a semiconductor element such as an insulated gate field effect transistor) and a manufacturing method thereof.

  In general, semiconductor elements are classified into a horizontal element having electrodes formed on one side and a vertical element having electrodes on both sides. In the vertical semiconductor element, the direction in which the drift current flows in the on state is the same as the direction in which the depletion layer due to the reverse bias voltage extends in the off state. In a normal planar type n-channel vertical MOSFET, the portion of the high n − drift layer functions as a region for flowing a drift current in the vertical direction when in the ON state. Therefore, if the current path of the n − drift layer is shortened, the drift resistance is lowered, so that an effect that the substantial on-resistance of the MOSFET is lowered can be obtained.

  On the other hand, the portion of the high resistance n − drift layer is depleted in the off state to increase the breakdown voltage. Accordingly, when the n − drift layer is thinned, the width of the drain-base depletion layer that progresses from the pn junction between the P base region and the drift region becomes narrower, and the critical electric field strength of silicon is reached quickly. It will decline. On the other hand, in a semiconductor device with a high breakdown voltage, since the n − drift layer is thick, the on-resistance increases and the loss increases. Thus, there is a trade-off relationship between on-resistance and breakdown voltage.

  This trade-off relationship is also known to hold in semiconductor devices such as IGBTs, bipolar transistors, and diodes. This trade-off relationship is also common to lateral semiconductor elements in which the direction in which the drift current flows in the on state and the direction in which the depletion layer extends in the off state are different.

  As a solution to the above-described problem due to the trade-off relationship, a parallel pn structure in which a drift layer is formed by alternately and repeatedly joining a drift region made of an n-type semiconductor region with an increased impurity concentration and a partition region made of a p-type semiconductor region. Such a super junction semiconductor element is known (see, for example, Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4). In the semiconductor element having such a structure, even when the impurity concentration of the parallel pn structure is high, the depletion layer extends laterally from each pn junction extending in the vertical direction of the parallel pn structure in the off state, and the entire drift region Therefore, a high breakdown voltage can be achieved.

  In order to manufacture a silicon super-junction wafer used for manufacturing the above-described super-junction semiconductor element at low cost and with high productivity, a trench is formed in the surface layer of the first conductivity type silicon substrate, and a second layer is formed in the trench. A method of epitaxially growing a conductive silicon layer is suitable. In general, epitaxial growth strongly depends on the crystal plane orientation. That is, there are crystal plane orientations and disadvantageous orientations that are advantageous for trench filling. By changing the epitaxial growth conditions such as growth temperature and material supply pressure, it is possible to reduce the difference between superiority and inferiority due to the plane orientation, but it is impossible to completely overcome the plane orientation dependence in epitaxial growth. .

  FIG. 10 is a cross-sectional perspective view showing the configuration of the main part of the super-bonded wafer. As shown in FIG. 10, a plurality of trenches 2 formed in the N-type semiconductor substrate 1 are buried with a P-type epitaxial layer 3. In this case, it is necessary to avoid that the opening of the trench 2 is first closed by the P-type epitaxial layer 3 and voids remain inside the trench 2. For this purpose, it is desirable that the side wall of the trench 2, that is, the boundary surface between the N-type semiconductor substrate 1 and the P-type epitaxial layer 3 is a low index surface that easily forms a facet (a stabilized flat surface) during crystal growth. . In FIG. 10, reference numeral 12 denotes an N + type drain layer.

  For example, the low index plane in which facets are easily formed in the silicon crystal is a (100) plane, a (111) plane, a (311) plane, a (411) plane, or a plane equivalent to each of them. Here, the equivalent plane is, for example, (11-1) plane, (1-11) plane, (-111) plane, (1-1-1) plane, etc. with respect to the (111) plane. . These crystal planes are different in the sign of the index in the notation, but the atomic arrangement of the crystal itself is exactly the same, and the chemical properties and physical properties are also equivalent.

  In this specification, “−1” in “−1” is a bar that is originally placed on the index, and in the case of a crystal plane, the plane crosses the corresponding principal axis of the unit cell in the minus direction. Means that. In the case of a direction, it means that the coordinate about the corresponding main axis is a negative value.

  As a proposal considering the crystal plane orientation, a method is known in which a trench having a (111) plane as a side surface is formed in a silicon semiconductor substrate having a (110) plane as a surface, and the trench is filled with an epitaxial layer (for example, (See Patent Document 5). By adopting such a plane orientation, for example, in Patent Document 5, high aspect trench processing is performed.

  By the way, in general, the gate of the MOSFET is desirably formed on a plane having a low interface state density, for example, a (100) plane. The same applies to a MOSFET having a trench gate structure, which is known as a structure for reducing the J-FET resistance of the MOSFET.

Therefore, FIG. 11 shows a trench 4 in which a gate electrode 6 is embedded via a gate insulating film 5, as shown in FIG. The side wall of (100) plane or an equivalent plane (for example, (010) plane, (001) plane, (-100) plane, (0-10) plane, (00-1) plane). The reason is that the interface state density is low and the electrical characteristics are excellent, and in FIG. It is an area.
Reference numeral 10 denotes an interlayer insulating film, and reference numerals 11 and 13 denote a source electrode and a drain electrode, respectively.

  As a proposal in consideration of the plane orientation of the side wall of the trench in which the gate electrode is embedded, a trench having (100) plane and (110) plane as side surfaces is formed on a silicon semiconductor substrate having (110) plane as a surface. Is well known in the art (see, for example, Patent Document 6). For example, in Patent Document 6, a channel is formed along the side wall of the (100) plane of the trench.

European Patent Application No. 0053854 US Pat. No. 5,216,275 US Pat. No. 5,438,215 JP-A-9-266611 JP 2002-124474 A JP 2002-231948 A

  However, when producing a trench gate type MOSFET on a superjunction wafer, if a plane orientation advantageous in trench buried epitaxial growth is selected to produce a superjunction wafer, the side wall of the trench for producing the trench gate structure is not necessarily ( 100) surface.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a plane orientation that is advantageous for the production of a superjunction wafer and also for the production of a trench gate structure. To do. Another object of the present invention is to provide a method for manufacturing a semiconductor device having a plane orientation that is advantageous for producing a super-junction wafer and also for producing a trench gate structure.

  In order to achieve the above object, a semiconductor element according to the invention of claim 1 includes a first semiconductor region comprising a first conductivity type semiconductor substrate having (100) plane and (0-10) plane as surfaces, and A second conductive type epitaxial layer that extends in the <001> direction on the surface layer of the semiconductor substrate and is embedded in a plurality of first trenches having a (010) plane or a plane equivalent thereto as side surfaces. Two semiconductor regions, a second trench extending in the <001> direction in the surface layer of the first semiconductor region, a gate insulating film along the inner surface of the second trench, and a second trench in the second trench A gate electrode embedded inside the gate insulating film, wherein the width of the second trench is wider than the width of the first semiconductor region between the adjacent second semiconductor regions. To do.

  A semiconductor element according to a second aspect of the invention is characterized in that, in the first aspect of the invention, the width of the first semiconductor region and the width of the second semiconductor region are the same.

  According to a third aspect of the present invention, there is provided a semiconductor element according to the first or second aspect of the present invention, wherein the source region of the first conductivity type provided in the surface layer between the adjacent second trenches, and the interlayer insulating film And a source electrode which is insulated from the gate electrode and is in contact with the source region.

  According to a fourth aspect of the present invention, there is provided a semiconductor element according to the first or second aspect of the present invention, wherein the drain layer of the first conductivity type provided on the back surface of the semiconductor substrate and the drain electrode in contact with the drain layer are provided. And further comprising.

  According to the present invention, in any case, the side surface of the first trench is one of the low index surfaces that easily form facets in epitaxial growth (the surface is equivalent to the 100 surface, and the side surface of the second trench is also The plane is equivalent to the (100) plane having a low interface state density.

  According to the present invention, the side surface of the first trench becomes a surface equivalent to the (100) surface, which is one of the low index surfaces where facets are easily formed during epitaxial growth, and the side surface of the second trench is also an interface state. A plane equivalent to the (100) plane having a low density is obtained. Therefore, it is possible to obtain a semiconductor element having a plane orientation that is advantageous for producing a superjunction wafer and also for producing a trench gate structure.

  According to the present invention, the side surface of the first trench is a surface equivalent to the (100) surface which is one of the low index surfaces where facets are easily formed in epitaxial growth, and the side surface of the second trench is A plane equivalent to the (100) plane having a low interface state density can be obtained. Therefore, it is possible to manufacture a super-junction wafer at low cost with high productivity, and it is possible to manufacture an insulated gate device having a trench gate structure with excellent electrical characteristics.

3 is a cross-sectional perspective view showing a configuration of a main part of the trench gate type MOSFET of Embodiment 1. FIG. FIG. 6 is a cross-sectional perspective view showing a configuration of a main part of a trench gate type MOSFET according to a second embodiment. FIG. 10 is a cross-sectional perspective view showing a configuration of a main part of a trench gate type MOSFET according to a third embodiment. FIG. 10 is a diagram for explaining dimensions of a trench gate type MOSFET according to a third embodiment. 7 is a cross-sectional perspective view showing a configuration of a main part of a trench gate type MOSFET of Reference Example 1. FIG. 10 is a cross-sectional perspective view showing a configuration of a main part of a trench gate type MOSFET of Reference Example 2. FIG. 10 is a cross-sectional perspective view showing a configuration of a main part of a trench gate type MOSFET of Reference Example 3. FIG. 12 is a cross-sectional perspective view showing a configuration of a main part of a trench gate type MOSFET of Reference Example 4. FIG. 10 is a cross-sectional perspective view showing a configuration of a main part of a trench gate type MOSFET of Reference Example 5. FIG. It is a cross-sectional perspective view which shows the structure of the principal part of a super bonded wafer. It is a cross-sectional perspective view which shows the structure of the principal part of the conventional trench gate type MOSFET. FIG. 10 is a cross-sectional perspective view showing a configuration of a main part of a planar gate MOSFET according to a fourth embodiment. FIG. 10 is a cross-sectional perspective view illustrating a configuration of a main part of a planar gate type MOSFET according to a fifth embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the first conductivity type is N-type and the second conductivity type is P-type, and vice versa. As the best mode of the present invention, the <001> direction is formed by a first semiconductor region formed of a first conductivity type semiconductor substrate having a (100) plane or an equivalent plane as a surface, and a surface layer of the semiconductor substrate. And having a second semiconductor region comprising an epitaxial layer of the second conductivity type embedded in a plurality of first trenches having the (010) plane and the (0-10) plane as side surfaces.
Embodiment 1 FIG.
FIG. 1 is a cross-sectional perspective view showing a configuration of a main part of the trench gate type MOSFET according to the first embodiment. As shown in FIG. 1, the surface of the high-resistance N-type semiconductor substrate 1 made of silicon is a (100) plane or a plane equivalent thereto. In the surface layer of the N-type semiconductor substrate 1, first trenches 2 extending in the <001> direction are formed at a predetermined pitch.

  The side surfaces of the first trench 2 are a (010) plane and a (0-10) plane, which are easy to form facets during epitaxial growth and have an orientation that makes it difficult to leave voids in the trench. Therefore, by performing epitaxial growth, the first trench 2 is filled with the P-type epitaxial layer 3 without a gap. The super-junction wafer has a structure in which the first semiconductor region made of the N-type semiconductor substrate 1 and the second semiconductor region made of the P-type epitaxial layer 3 are alternately and repeatedly bonded. A semiconductor layer to be a high concentration N + type drain layer 12 is provided on the back surface of the super bonded wafer.

  The second trench 4 extending in the <001> direction is formed so as to remove at least the surface layer of the first semiconductor region of the superjunction wafer, that is, the exposed portion of the N-type semiconductor substrate 1. At this time, the side surface of the second trench 4 is a (010) plane or a plane equivalent thereto, and has an orientation with a low interface state density. A gate insulating film 5 is formed along the inner surface of the second trench 4, and an inner portion thereof is buried with the gate electrode 6. As the gate electrode 6, for example, phosphorus-doped polysilicon or the like is used.

  A high concentration N + type source region 8 and a high concentration P type semiconductor region 9 are formed in the surface layer of the second semiconductor region of the superjunction wafer, that is, the surface layer of the P type epitaxial layer 3. A source electrode 11 is formed so as to be in contact with the N + -type source region 8 and the P-type semiconductor region 9 and not in contact with the gate electrode 6. An interlayer insulating film 10 is formed between the gate electrode 6 and the source electrode 11. A drain electrode 13 is in contact with the N + type drain layer 12.

According to the first embodiment described above, the side surface of the first trench 2 becomes a surface equivalent to the (100) surface, which is one of the low index surfaces where facets are easily formed during epitaxial growth, and the second trench 4 This side surface is also a surface equivalent to the (100) surface having a low interface state density. Therefore, it is possible to obtain a MOSFET having a plane orientation that is advantageous for producing a super-junction wafer and also for producing a trench gate structure. In addition, a super-junction wafer can be manufactured at low cost and with high productivity, and a MOSFET having excellent electrical characteristics can be manufactured.
Embodiment 2. FIG.
FIG. 2 is a cross-sectional perspective view showing a configuration of a main part of the trench gate type MOSFET of the second embodiment. As shown in FIG. 2, the second embodiment is different from the first embodiment in that the second trench 4 removes not the exposed portion of the N-type semiconductor substrate 1 but the exposed portion of the P-type epitaxial layer 3. And the P-type semiconductor region 7 is formed in the surface layer of the N-type semiconductor substrate 1, and the high-concentration N + -type source region 8 and the high-concentration source region 8 are formed in the surface layer of the P-type semiconductor region 7. That is, a P-type semiconductor region 9 having a concentration is formed. Other configurations are the same as those of the first embodiment. About the same structure as Embodiment 1, the code | symbol same as Embodiment 1 is attached | subjected and description is abbreviate | omitted.

According to the second embodiment, in addition to the same effects as those of the first embodiment, the impurity concentration and diffusion depth of the P-type semiconductor region 7 formed in the surface layer of the N-type semiconductor substrate 1 are accurately determined. The effect is that the channel length and threshold voltage of the MOSFET can be accurately controlled.
Embodiment 3 FIG.
FIG. 3 is a cross-sectional perspective view showing the configuration of the main part of the trench gate type MOSFET of the third embodiment. As shown in FIG. 3, the third embodiment is different from the first embodiment in that the second trench 4 is adjacent to the width of the exposed portion of the N-type semiconductor substrate 1. A P-type semiconductor region 7 is formed in a surface layer between the second trenches 4, and a high-concentration N + -type source region 8 and a high-concentration P-type semiconductor region 9 are formed in the surface layer of the P-type semiconductor region 7. Is formed. Other configurations are the same as those of the first embodiment. About the same structure as Embodiment 1, the code | symbol same as Embodiment 1 is attached | subjected and description is abbreviate | omitted.

  Here, in the trench gate type MOSFET having the configuration shown in FIG. 3, the standard dimensions and impurity concentrations of the respective parts are as follows. However, as shown in FIG. 4, the opening width of the first trench 2, that is, the width of the P-type epitaxial layer 3, is Wp, and the pitch of the first trench 2, that is, the N-type semiconductor in the superjunction region of the superjunction wafer. The width of the substrate 1 is Wn. That is, in the super-bonded wafer, it is assumed that P-type regions having a width of Wp and N-type regions having a width of Wn are alternately bonded.

  The opening width of the second trench 4 is Wt. The depth of the second trench 4 is dt, and the thickness of the superjunction region of the superjunction wafer, that is, the depth from the bottom of the second trench 4 to the bottom of the first trench 2 is ds.

  For example, in the case of a 600V withstand voltage MOSFET, Wn and Wp are substantially equal, 8 μm or less, and preferably 5 μm or less. The impurity concentration of the N-type semiconductor substrate 1 and the impurity concentration of the P-type epitaxial layer 3 in the superjunction region are substantially equal, and are about 2.5 × 10 16 cm −3 when Wn and Wp are 8 μm, and when Wn and Wp are 5 μm. It is about 4 × 10 16 cm −3. ds is approximately 40 to 50 μm. Wt is 2 μm or less, preferably 1 μm or less. dt is 5 μm or less, and preferably about 1 to 3 μm.

  For example, in the case of a MOSFET with a withstand voltage of 100 V, Wn and Wp are substantially equal and are 2 μm or less, preferably about 1 μm. The impurity concentration of the N-type semiconductor substrate 1 and the impurity concentration of the P-type epitaxial layer 3 in the superjunction region are substantially equal, and is approximately 1 × 10 17 cm −3 when Wn and Wp are 2 μm, and 2 × when Wn and Wp are 1 μm. It is about 1017 cm-3. ds is approximately 8 to 10 μm. Wt is smaller than Wn, preferably 1 μm or less. dt is preferably 3 μm or less.

According to the third embodiment described above, in addition to the same effects as those of the first embodiment, the impurity concentration and diffusion depth of the P-type semiconductor region 7 formed in the surface layer of the N-type semiconductor substrate 1 are accurately determined. As a result, it is possible to accurately control the channel length and the threshold voltage of the MOSFET. Further, since the width of the second trench 4 is narrower than that of the first embodiment, the ratio of the opening area of the second trench 4 to the total surface area of the wafer, that is, the opening ratio is reduced. An effect is obtained that a wide range of process conditions can be taken when the trench 4 is formed. Further, in the region 15 of the P-type semiconductor region 7 that overlaps with the P-type epitaxial layer 3, the impurity concentration is high, and therefore, together with the high-concentration P-type semiconductor region 9 formed in the surface layer of the P-type semiconductor region 7. This has the effect of increasing the latch-up resistance at turn-off.
Reference Example 1
FIG. 5 is a cross-sectional perspective view showing the configuration of the main part of the trench gate type MOSFET of Reference Example 1. As shown in FIG. 5, Reference Example 1 differs from Embodiment 1 in that the surface of N-type semiconductor substrate 1 is a (110) plane or a plane equivalent thereto, and the first and second trenches. 2 and 4 extend in the <1-10> direction, and the side surfaces of these trenches 2 and 4 become (001) planes or equivalent planes. Other configurations are the same as those of the first embodiment. About the same structure as Embodiment 1, the code | symbol same as Embodiment 1 is attached | subjected and description is abbreviate | omitted. According to Reference Example 1, the same effect as in the first embodiment can be obtained.
Reference Example 2
6 is a cross-sectional perspective view showing the configuration of the main part of the trench gate type MOSFET of Reference Example 2. FIG. As shown in FIG. 6, in Reference Example 2, the surface orientation of the surface of the N-type semiconductor substrate 1 and the directions of the first and second trenches 2 and 4 are changed in the second embodiment. That is, in Reference Example 2, the surface of the N-type semiconductor substrate 1 is the (110) plane or a plane equivalent thereto.

The first and second trenches 2 and 4 extend in the <1-10> direction, and the side surfaces of the trenches 2 and 4 are (001) planes or equivalent planes. Other configurations are the same as those of the second embodiment. About the same structure as Embodiment 2, the code | symbol same as Embodiment 2 is attached | subjected and description is abbreviate | omitted. According to the reference example 2, the same effect as in the second embodiment can be obtained.
Reference Example 3.
FIG. 7 is a cross-sectional perspective view showing the configuration of the main part of the trench gate type MOSFET of Reference Example 3. As shown in FIG. 7, in Reference Example 3, the surface orientation of the surface of the N-type semiconductor substrate 1 and the directions of the first and second trenches 2 and 4 are changed in the third embodiment. That is, in Reference Example 3, the surface of the N-type semiconductor substrate 1 is the (110) plane or a plane equivalent thereto.

The first and second trenches 2 and 4 extend in the <1-10> direction, and the side surfaces of the trenches 2 and 4 are (001) planes or equivalent planes. Other configurations are the same as those of the third embodiment. About the same structure as Embodiment 3, the same code | symbol as Embodiment 3 is attached | subjected and description is abbreviate | omitted. According to the reference example 3, the same effect as in the third embodiment can be obtained.
Reference Example 4
FIG. 8 is a cross-sectional perspective view showing the configuration of the main part of the trench gate type MOSFET of Reference Example 4. As shown in FIG. 8, the reference example 4 is different from the first embodiment in that the second trench 4 extends in the direction perpendicular to the first trench 2, that is, the <010> direction. A P-type semiconductor region 7 is formed in the surface layer between the matching second trenches 4, and a high-concentration N + -type source region 8 and a high-concentration P-type semiconductor region are formed in the surface layer of the P-type semiconductor region 7. 9 is formed.

The side surface of the second trench 4 is a (001) plane or a plane equivalent thereto. Other configurations are the same as those of the first embodiment. About the same structure as Embodiment 1, the code | symbol same as Embodiment 1 is attached | subjected and description is abbreviate | omitted. According to the reference example 4, in addition to the same effect as that of the first embodiment, the opening width and pitch of the second trench 4 can be determined independently from the pattern of the first trench 2. It is done.
Reference Example 5
FIG. 9 is a cross-sectional perspective view showing the configuration of the main part of the trench gate type MOSFET of Reference Example 5. As shown in FIG. 9, Reference Example 5 is the same as Reference Example 4 except that a high-resistance N-type buffer layer 14 is formed on the surface layer of the superjunction wafer across the N-type semiconductor substrate 1 and the P-type epitaxial layer 3. It is. The second trench 4 is formed through the N-type buffer layer 14. The high concentration N + type source region 8 and the high concentration P type semiconductor region 9 are formed in the surface layer of the N type buffer layer 14. Other configurations are the same as those of the third embodiment. About the same structure as Embodiment 3, the same code | symbol as Embodiment 3 is attached | subjected and description is abbreviate | omitted.

  According to the reference example 5, in addition to the same effects as those of the reference example 4, the presence of the N-type buffer layer 14 makes the impurity concentration on the outside along the second trench 4 constant. The P-type semiconductor region 7 provided between the two trenches 4 is not affected by the overlap or non-overlap with the P-type epitaxial layer 3, and the electrical characteristics such as the threshold voltage are stabilized. .

  As described above, the present invention is not limited to the N-channel MOSFET exemplified in the embodiment, but can be applied to all semiconductor elements having a superjunction structure and a trench gate structure. For example, the present invention can also be applied to a P-channel MOSFET, an IGBT (insulated gate bipolar transistor) having a trench type MOS gate structure, or the like.

The first to third embodiments and the first to fifth reference examples have a trench gate structure as the gate structure. In general, the use of a trench gate structure is advantageous in terms of characteristics because it can reduce the on-resistance in terms of electrical characteristics. However, with the current manufacturing technology, it cannot be said that the technology for forming the trench gate structure has been sufficiently established, and as a result of adopting the trench gate structure, the variation in electrical characteristics increases and the yield rate decreases. It is also possible. In view of this, an embodiment for suppressing variation in electrical characteristics and maintaining a high yield rate will be described below.
Embodiment 4 FIG.
FIG. 12 is a cross-sectional perspective view showing a configuration of a main part of the planar gate type MOSFET of the fourth embodiment. As shown in FIG. 12, in the fourth embodiment, the surface of the high resistance N-type semiconductor substrate 1 made of silicon is the (100) plane or a plane equivalent thereto. The first trenches 2 extending in the <001> direction are formed at a predetermined pitch in the surface layer of the N-type semiconductor substrate 1.

  The side surface of the first trench 2 is a (010) plane or a plane equivalent thereto, and has an orientation in which facets are easily formed during epitaxial growth, and voids are not easily left in the trench. Therefore, by performing epitaxial growth, the first trench 2 is filled with the P-type epitaxial layer 3 without a gap. The super-junction wafer has a structure in which the first semiconductor region made of the N-type semiconductor substrate 1 and the second semiconductor region made of the P-type epitaxial layer 3 are alternately and repeatedly bonded. A semiconductor layer to be a high concentration N + type drain layer 12 is provided on the back surface of the super bonded wafer.

  The P-type semiconductor region 9 extending in the <001> direction is formed on the P-type epitaxial layer 3 of the N-type semiconductor substrate 1. A gate insulating film 5 is formed on the N-type semiconductor substrate 1 along the surface of the P-type semiconductor region 9, and a gate electrode 6 is formed on the upper portion thereof. As the gate electrode 6, for example, phosphorus-doped polysilicon or the like is used.

A high concentration N + type source region 8 is formed on the surface of the high concentration P type semiconductor region 9.
A source electrode 11 is formed so as to be in contact with the N + -type source region 8 and the P-type semiconductor region 9 and not in contact with the gate electrode 6. An interlayer insulating film 10 is formed between the gate electrode 6 and the source electrode 11. A drain electrode 13 is in contact with the N + type drain layer 12.

According to the fourth embodiment described above, the side surface of the first trench 2 becomes a surface equivalent to the (100) surface, which is one of the low index surfaces where facets are easily formed during epitaxial growth. Therefore, a MOSFET having a plane orientation advantageous for producing a super-junction wafer can be obtained. In addition, a super-junction wafer can be manufactured at low cost with high productivity, and an excellent MOSFET with little variation in electrical characteristics can be manufactured by adopting a planar gate structure with established manufacturing technology.
Embodiment 5
FIG. 13 is a cross-sectional perspective view showing a configuration of a main part of the planar gate type MOSFET of the fifth embodiment. As shown in FIG. 13, in the fifth embodiment, the surface of the N-type semiconductor substrate 1 is a (100) plane or a plane equivalent thereto, and the surface layer of the N-type semiconductor substrate 1 has a <001> direction. As in the fourth embodiment, the first trenches 2 are formed at a predetermined pitch, and the side surfaces of the first trenches 2 are (010) planes or equivalent planes. The difference from the fourth embodiment is the direction in which the P-type semiconductor region 9 extends. That is, in the fourth embodiment, the extending direction of the P-type semiconductor region 9 is the same (parallel) to the extending direction of the first trench 2, whereas in the fifth embodiment, the first trench 2 is extended. The direction in which the P-type semiconductor region 9 extends is different (orthogonal) from the direction in which the P-type semiconductor region 9 extends. Since other configurations are the same as those of the fourth embodiment, the same configurations as those of the fourth embodiment are denoted by the same reference numerals as those of the fourth embodiment and description thereof is omitted. In the fourth embodiment, it is necessary to make the pitch of the adjacent P-type epitaxial layer 3 coincide with the pitch of the adjacent P-type semiconductor region 9 or to multiply (to be parallel) in order to reduce variation in electrical characteristics. However, in the fifth embodiment, it is not necessary to match or multiply the pitch of the adjacent P-type epitaxial layer 3 and the pitch of the adjacent P-type semiconductor region 9 (because they are orthogonal).
As described above, the present invention is not limited to the N-channel MOSFET exemplified in the embodiment, but can be applied to all semiconductor elements having a superjunction structure and a trench gate structure. For example, the present invention can also be applied to a P-channel MOSFET, an IGBT (insulated gate bipolar transistor) having a trench type MOS gate structure, or the like.

  Since the semiconductor element of the present invention can realize a low on-resistance, it can be applied to a circuit that requires a low loss switching element.

DESCRIPTION OF SYMBOLS 1 N type semiconductor substrate 2 1st trench 3 P type epitaxial layer 4 2nd trench 5 Gate insulating film 6 Gate electrode 7 P type semiconductor region 8 N + type source region 9 High concentration P type semiconductor region 10 Interlayer insulating film 11 Source electrode 12 N + type drain layer 13 Drain electrode 14 High resistance N type buffer layer

Claims (4)

A first semiconductor region comprising a semiconductor substrate of a first conductivity type having a (100) plane or a plane equivalent thereto,
From a second conductivity type epitaxial layer embedded in a plurality of first trenches extending in the <001> direction on the surface layer of the semiconductor substrate and having (010) plane and (0-10) plane as side surfaces A second semiconductor region comprising:
A second trench extending in the <001> direction in the surface layer of the first semiconductor region;
A gate insulating film along the inner surface of the second trench;
A gate electrode embedded inside the gate insulating film in the second trench;
Comprising
The width of the second trench is wider than the width of the first semiconductor region between the adjacent second semiconductor regions. The semiconductor element according to claim 1, wherein a width of the first semiconductor region and a width of the second semiconductor region are the same. A source region of a first conductivity type provided in a surface layer between the adjacent second trenches;
A source electrode insulated from the gate electrode by an interlayer insulating film and in contact with the source region;
The semiconductor device according to claim 1, further comprising: A drain layer of a first conductivity type provided on the back surface of the semiconductor substrate;
A drain electrode in contact with the drain layer;
The semiconductor device according to claim 1, further comprising: