JPS61168912A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of facets from an interface between an insulating film and an epitaxial semiconductor, by making one crystal plane to be a main surface of a semiconductor substrate, and specifying the orientation of a square opening part, with the other crystal plane, which crosses said crystal plane at a right angle, as a reference plane. CONSTITUTION:In a P-type silicon semiconductor wafer 11, whose (100) plane is the main surface, a (0T0) plane or a (010) plane is specified as an orientation flat. The pattern orientation of a chip 12 is specified so that (001) becomes the lateral (X) direction and (010) becomes the longitudinal (Y) direction. The shape of an opening-part pattern 13 for an island region, in which a semiconductor element is formed at one chip 12, is as follows: two sides are in parallel with the (001)-axis direction, and the other two sides are in parallel with the (010)-axis direction. When the epitaxial semiconductor layer is selectively formed on the semiconductor surface, facets and the like do not occur in an interface between the layer and the insulating film.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor devices, particularly selective epitaxial technology.
The present invention relates to a semiconductor device having a further element isolation structure.

[Background technology]

@Selective epitaxial growth technology is attracting attention in the construction of fine element isolation of LSI and three-dimensional devices.

This selective epitaxial technique is used, for example, in step 5 shown in FIG. It has an epitaxial semiconductor layer 4 that has been selectively grown in a vapor phase, and uses this epitaxial semiconductor layer 4 as an element active region, making it possible to create a fine element isolation structure whose plane is flatter than Ic.

However, in such a selective epitaxial semiconductor layer 4, diagonal stacking faults 5 are likely to occur from the bottom to the surface of the sidewall of the semiconductor layer in contact with the diluted film 2, as shown in the figure. The flow of leaks increases,
There was a risk that instability would occur due to the characteristics.

According to the Japan Society of Applied Physics 21st Semiconductor Specialized Seminar Proceedings 1983 Autumn Li No. 26P-N-4, the technology to deal with this is to add a nitride layer (SI) on the side surface of the element isolation region (S!Os).
s N4) reduces the number of stacking faults formed in the selectively epitaxially grown semiconductor layer, but at the cost of
It has been reported that facets 6 are likely to occur on the surface of the epitaxial semiconductor layer 40 during step 5 shown in FIGS.

As shown in FIG. 9, this facet is a crystal plane (this crystal plane is 111) plane or (113) plane) 6, and the width W and depth D of this portion 6 are said to depend on the film thickness t of the epitaxial layer 4.

The presence of such 7 assets 6 naturally prevents surface flattening. In addition, when facets occur, impurities tend to diffuse and become highly concentrated at the interface between the side surface of the epitaxial semiconductor layer and the oxide film 2, resulting in 911
The resistance at the first wall portion 7 decreases, resulting in leakage current failure.

Also, according to the same preliminary report '83 Spring 6a-T-6, it was proposed to use °C polysilicon as the sidewall material of the selective epitaxial growth layer, and although stacking faults would be reduced in that case, grains (crystal grains) ) is reported to develop abnormally, reducing the effective device formation area (・ru).

The present invention has been made in view of these problems.

OBJECT OF THE INVENTION One object of the present invention is to use selective epitaxial technology to
Another object of the present invention is to prevent the generation of facets from the interface between an insulating film and an epitaxial semiconductor layer in a semiconductor device isolation structure using selective epitaxial technology. Another object of the present invention is to improve the crystallinity of an epitaxial semiconductor layer, reduce leakage current, and improve device yield.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

Among the inventions disclosed in this application, a brief summary of typical ones is as follows.

That is, a silicon layer is selectively epitaxially grown on the exposed surface of the semiconductor substrate at the bottom within a rectangular opening that is opened above the silicon semiconductor substrate and has at least one side surface covered with an insulating film.
In a semiconductor device in which an element active region is formed on the surface of a silicon layer, the semiconductor substrate has one crystal plane, for example, a (100) plane as a principal plane. 9, one other crystal plane, for example (010) plane, (001
) plane is defined so as to be in the side direction of the above-mentioned rectangular opening, and an open pattern is provided in the direction in which the (111) plane of the facet is difficult to occur. Because of this K, no facets are generated at the interface between the epitaxial silicon layer and the insulating film inside the opening, and the crystallinity is excellent and leakage is prevented.
Semiconductor devices with better characteristics can be realized.

Prior to explaining the present invention, the crystal orientation of silicon semiconductor wafers used in semiconductor devices will be explained.As shown in FIG.
0) The main surface is the plane 3° to 4° outside the crystal plane,
Orientate a plane ((110) plane) that forms an angle of C45° with respect to the other crystal planes (001) and (010) planes that are A5e. In such a semiconductor unit, the orientation of the pattern of the semiconductor chip is set with reference to (,1,F), and the opening of the insulating film on each chip is The pattern of the part is O, as shown in the figure.
F, parallel to the direction and perpendicular to the direction, seven degrees Celsius will be provided.

On the other hand, according to the present invention, the semiconductor wafer (substrate) is (100) ±1° as shown in FIG.
as the main surface, with an orientation of 1 franc) 0. F, is (100) plane and I5! , do (010) or (OTO)
Use f as the surface.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments of a process for manufacturing semiconductor devices from semiconductor wafers.

As shown in FIG. 1, 5 is a p-type silicon semiconductor wafer 11 having a (100) plane as its main surface. For convenience, (001) is changed to horizontal (X)
Chip 1 so that the (010) direction is the vertical (Y) direction.
2 pattern direction is defined.

FIG. 2 shows the pattern orientation in one chip 12, and 13 shows the shape and arrangement of the opening pattern for the island region where the semiconductor element is formed.

What should be noted here is that if one pattern is taken, two
The side is parallel to the (001> axis direction, and the other two sides are <010>
It is parallel to the axial direction. By doing this, the directions in which 7γ set is unlikely to occur are limited.

FIG. 3 is a cross-sectional view of A-A'≦large slope in FIG. , the semiconductor 14 is exposed at the bottom of this opening 16.

Figure 4 shows the semiconductor 14 at the bottom of the opening 16 (.
n-type epitaxial semiconductor (
3 is a cross-sectional view showing a state in which a silicon layer 17 is formed. FIG.

In order to selectively form this epitaxial semiconductor layer 17, for example, vapor phase growth is performed using the reaction of the following formula: This controls the epitaxial growth rate and selectively grows silicon only on the surface of the silicon substrate 14, while suppressing silicon growth from the surface of the oxide film 15, and forms the epitaxial semiconductor layer 17 so as to completely fill the inside of the opening. It is.

In the above epitaxial growth process, °C, SiH, Ci
By pre-mixing a P (phosphorus) component or a B (boron) component into the , low concentration n-type or p-
A p-type silicon crystal can be grown as shown in FIG. 18, n+ type collector 1
9. A device active tilted wall consisting of a discrete layer such as the n''W emitter 20 is formed, and the islands are isolated from each other through various processes such as removal of surface oxidation fi 21, contact photoetching, and formation of aluminum evaporated electrode 22. Knpn within the area
Complete transistors, etc.

Effects of the Invention] According to the present invention described in the above embodiments, the following effects can be obtained.

The orientation of the reference plane of the semiconductor wafer is set to one crystal orientation (001).
or (010) plane, and absolute lj &
By defining the side surface of the opening in the film to be parallel to the crystal plane, facets and the like are not generated at the interface with the insulating film when an epitaxial semiconductor layer is selectively formed on the semiconductor surface. In other words, the plane orientations of the 7-piece set are usually crystal planes (111), (112), (113), and (114).
etc.

That is, on the (100) plane, (001) plane, (010)
By forming a pattern along the surface, the occurrence of 7 assets can be prevented.

By eliminating the occurrence of facets in this way, the crystallinity of the epitaxial semiconductor layer formed in the opening of the insulating film is significantly improved, leakage current, etc. are reduced, and as a result, the yield of the device is improved.

Furthermore, the separation area can be reduced, and the amount of miniaturization is 1llll! It becomes possible to create bipolar ICs with

Furthermore, it should be noted that by eliminating the 7γ set, the area of the epitaxial layer can be used effectively, and the stacking density of the semiconductor device can be improved.

Although the invention made by the inventor has been specifically explained above based on examples, the present invention is not limited to the above examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, an opening in an insulating film on the surface of a semiconductor substrate! Open,
In addition to selectively growing an epitaxial semiconductor layer within this layer, as shown in FIG. After forming an insulating layer on the surface, the insulating film at the bottom of the opening may be removed and an epitaxial semiconductor layer may be selectively grown there.

In addition, a semiconductor device in which the present invention is applicable to a semiconductor substrate having, for example, a (111) plane as a main surface is also possible.

[Application field]

The present invention is an insulation valve l! ! It can be applied to all semiconductor devices having a rough epitaxial semiconductor layer.

The present invention has an M effect particularly when applied to highly efficient and miniaturized semiconductor devices such as high-speed memories.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor wafer of the present invention, FIG. 2 is a plan view of a semiconductor chip (substrate), and FIG. 3 is a semiconductor chip that has been fired. Figure 4 is a partial cross-sectional view of a semiconductor chip after selective epitaxial growth; Figure 5 is a partial cross-sectional view of a semiconductor chip with an element active region formed thereon; Figure 6 shows a conventional example. FIG. 7 is an enlarged partial cross-sectional oblique view of a semiconductor chip showing a conventional example; FIG. 8 is a plan view of a selective epitaxial semiconductor layer showing a conventional example; FIG. 9 The figure is a sectional view taken along the line B-B' in FIG. 8, and FIG. 10 is an enlarged partially sectional oblique view of a semiconductor chip showing another embodiment of the present invention. 11... Semiconductor wafer, 12... Semiconductor chip, 1
3... Opening, 14... Semiconductor silicon substrate, 15
... semiconductor oxide film, 16... opening, 17...)
8 selection pitaxial half 4 layers, 18...base, 19
...Collector extraction part, 2o...Emitter. Agent: Patent Attorney Katsuo Ogawa ゛) No. 1
Figure 2 (σl Figure 3 Figure 6 Figure 10)

Claims (1)

[Scope of Claims] 1. An epitaxial semiconductor layer is selectively grown on the exposed surface of the semiconductor substrate at the bottom of a rectangular opening formed in one principal surface of a semiconductor substrate, at least one side of which is made of an insulating film. A semiconductor device in which an element active region is formed on the surface of the epitaxial semiconductor layer, wherein the semiconductor substrate has one crystal plane as a principal plane and another crystal plane orthogonal to this crystal plane as a reference plane. A semiconductor device characterized in that the orientation of the rectangular opening is defined as . 2. The semiconductor device according to claim 1, wherein the semiconductor substrate has a (100) plane as a principal plane, and a (010) plane or a (001) plane perpendicular to the (100) plane as a reference plane.