JP2585642B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device manufacturing technique, in particular, to specify a plane direction of a main surface of a silicon single crystal plate and a direction of a length direction of an orientation flat to obtain a good electrical property. The present invention relates to a semiconductor device manufacturing technique capable of manufacturing a semiconductor device having characteristics with high yield and high profitability.

[Conventional technology]

In the manufacture of a semiconductor device using a silicon crystal plate, a semiconductor wafer having a crystal plane of {100} (semiconductor thin plate: hereinafter also simply referred to as a wafer) is frequently used.

In addition, planar defects (oxidative stacking faults: O
As a technique for suppressing SF), a technique described in Japanese Patent Publication No. 50-182 is known. This document describes the following. That is, in a silicon wafer having a crystal plane of {100} as a main surface, an oxide stacking fault occurs in a thermal oxide film forming step, a high temperature processing step, and the like. When this oxidation stacking fault exists, impurity atoms concentrate on dislocations during diffusion, or the dislocations act as diffusion pipes to abnormally increase the diffusion speed. When the dislocation crosses the PN junction, the microplasma causes a breakdown phenomenon of the junction, thereby deteriorating the PN junction. In addition, a general property of the dislocation is a property of acting as a carrier recombination center, which is a problem particularly when low noise is required.

Therefore, in the technique according to this document, a wafer whose main surface is inclined at a desired angle (off-angle: θ) with respect to {100} of silicon bonding is used, thereby reducing the number of planar defects directly under the oxide film. It is described that a silicon semiconductor device is obtained.

On the other hand, Japanese Patent Publication No. 56-24380 discloses that, in a semiconductor device or a semiconductor device using a semiconductor wafer or chip having a silicon crystal plane on an equivalent plane {100} or a plane in the vicinity thereof, the silicon crystal plane is diffused into the semiconductor wafer or the chip. A semiconductor device, wherein a resistance is formed and a length direction of the diffusion resistor is formed so as to be parallel or perpendicular to a (100) equivalent crystal axis direction or a crystal axis direction in the vicinity thereof. I have. This document describes that "variation" in the resistance value of the diffused resistor is one of the major factors affecting the yield of the linear IC. In addition, the following is described in this document.
That is, the resistance value fluctuates depending on the state of the wafer, the state in which the wafer is divided into pellets, or the state in which the wafer is packaged into a final product. This is because the resistance value of the diffusion resistor fluctuates due to a piezoresistance effect caused by a thermal stress or a mechanical stress applied to the silicon substrate provided with the diffusion resistor. Therefore, in the manufacture of a semiconductor device, even in a process in which heat is applied to the diffusion resistance portion and a process in which mechanical pressure is applied, in the direction of the silicon crystal axis where the piezoresistance effect is minimized so that the resistance value does not fluctuate. Along the length of the diffusion resistor.

[Problems to be solved by the invention]

The present inventor has attempted to achieve a semiconductor device having few crystal defects such as oxidized stacking faults and exhibiting good electrical characteristics by combining the above two prior arts.

However, it has been clarified by the present inventor that the following new problems occur only by combining the above two technologies.

That is, FIG. 18 shows an improved silicon wafer (hereinafter, simply referred to as a wafer) provided with an off-angle and proposed by the present applicant. The main surface 2 of the wafer 1 has a crystal <10
It has a structure in which a crystal plane (100) perpendicular to the <0> axis is inclined (off-angle: θ) along the <010> direction.
The orientation flat 3 indicating the directionality of the wafer 1 is provided along the crystal direction <01> or <01>. Accordingly, an off angle of θ (θ = 4 °) is provided in the direction of 225 ° from the orientation flat 3 of the wafer 1 with respect to the crystal plane of (100), for example.

When this structure is reversed, the crystal orientation on the upper surface of the wafer 1 is different. A wafer is manufactured by slicing a single crystal ingot, but simply slicing a single crystal ingot with the orientation flat 3 provided,
Since there is no mark, it is difficult to specify the front and back surfaces of the wafer thereafter, and it cannot be guaranteed which surface is used as the surface for forming the semiconductor device, that is, the main surface.

On the other hand, the main surface of the wafer 1 is provided with an epitaxial growth layer. Since the main surface of the epitaxial growth layer has an off-angle structure, as shown in FIG. When the epitaxial growth layer 5 grows, the groove portion gradually shifts in the off-angle direction due to the difference in crystallinity due to the off-angle. This shift amount Δl substantially corresponds to the thickness d of the epitaxial growth layer 5.

Also, the orientation flat 3 is set to <01>
Alternatively, in the wafer 1 to be set to <01>, the longitudinal direction of the diffusion resistor 7 provided in the chip region 6 extends in a direction of 45 ° or 135 ° with respect to the orientation flat 3. As a result, when the wafer 1 is rotated 180 degrees around the <00> crystal axis in FIG. 18 and the front and back of the wafer 1 are turned over, the shift direction of the epitaxial growth layer 5 is not constant. If the front and back are mixed in opposite directions, the plane XY direction (the direction parallel to the orientation flat is the X direction and the direction
Direction) is shifted in three directions of + X and ± Y.

From the above, in the photolithography process at the time of forming the diffusion pattern, it is necessary to set an extra margin when performing mask alignment with the underlying pattern. That is, the alignment margin of the mask alignment is not limited to the absolute margin α originally required due to the relationship between the wafer processing error and the positioning error of the equipment and the like, and the growth deviation error Δl ( For example, the alignment margin α + Δ obtained by adding the thickness d) of the epitaxial growth layer 5
1, that is, α + d.

Therefore, when such a wafer 1 is used, the margin of alignment of the mask alignment must be increased, so that the miniaturization of the putter is alienated. On the other hand, the orientation flat (main flat) 3 is provided. In addition, if a mark such as a sub-flat is provided for discrimination of the front and back, a mirror-polished mirror surface (main surface) can be specified, and the crystal tilt direction of the substrate can be kept constant. However, in this case, the addition of the sub-flat causes a problem that a new mechanism must be incorporated in the semiconductor device manufacturing apparatus because the sub-flat or the like is provided in the automatic conveyance or alignment mechanism system. This is not always an effective solution.

An object of the present invention is to provide a semiconductor device manufacturing technique capable of achieving reduction of oxidized stacking faults.

Another object of the present invention is to provide a semiconductor device manufacturing technique capable of stabilizing a diffusion resistance.

Another object of the present invention is to provide a semiconductor device manufacturing technique capable of achieving fine patterning.

Another object of the present invention is to provide a semiconductor device manufacturing technique which has excellent characteristics and can achieve high density.

Another object of the present invention is to provide a semiconductor device manufacturing technique capable of achieving miniaturization of a semiconductor element and a semiconductor device.

Another object of the present invention is to provide a wafer (semiconductor substrate) which is easy to use because of the occurrence of oxidative stacking faults.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

In the manufacture of the semiconductor device of the present invention, the (100)
After manufacturing a silicon wafer having a surface inclined at a predetermined angle to the <010> direction or a surface equivalent to the surface and having an orientation flat in a direction along the inclination direction, the wafer A photolithography process is performed on the surface to form a rectangular semiconductor region to form a diffusion resistor and the like, thereby manufacturing a semiconductor device. The longitudinal direction of the semiconductor region extends along the <010> or <001> orientation of the crystal orientation, or an orientation equivalent to the orientation. The wafer is sliced after forming an orientation flat portion on a silicon single crystal ingot. Further, since the direction of extension of the orientation flat coincides with the off-angle direction as described above, the direction and direction of the substrate inclination with respect to the orientation flat are always constant regardless of which surface of the sliced wafer is mirror-polished. Become.

[Action]

According to the above-described means, in the manufacture of the semiconductor device of the present invention, since the off-angle structure wafer has the same orientation of the off-angle and the extension direction of the orientation flat, the wafer is used in a front state or a back state. In this case, at the time of epitaxial growth, the growth direction of the epitaxial growth layer is shifted only in one direction (for example, the plus direction) of the X-axis along the orientation flat, and no growth shift occurs in the direction orthogonal to the orientation flat. As a result, the wafer can be used without worrying about the front and back surfaces, and the usability of the wafer is improved. That is,
There is no need to provide a sub-flat on the wafer for discrimination of the front and back of the wafer, and it is not necessary to remodel the semiconductor device manufacturing equipment to cope with the sub-flat. In addition, in the mask alignment, a margin (growth deviation error) obtained by adding a deviation of the epitaxial growth layer in only one direction of the X axis to the absolute margin α essentially required is sufficient as the margin of alignment. In the Y-axis direction, only the margin α is sufficient, so that the alignment margin is reduced as a whole, and downsizing of the pattern can be achieved. Also, due to the miniaturization of this pattern,
It is also possible to achieve finer patterns and higher densities.
The direction of the orientation flat is generally a direction in which one side of the chip faces, and a rectangular semiconductor region (rectangular pattern) is formed along the direction of one side of the chip. Therefore, when a diffusion resistor is formed by a rectangular semiconductor region, the longitudinal direction of the diffusion resistor always coincides with the direction along one side of the chip, and the area for forming the diffusion resistor can be reduced in size, and the chip can be downsized. . The longitudinal direction of the diffusion resistance is also the direction in which the piezoresistance effect is minimized. As a result, the dispersion of the diffusion resistance is reduced, and the characteristics of the semiconductor element can be improved. Further, since the off-angle wafer hardly generates oxidative stacking faults even in the oxidation step, the stability of the characteristics of the semiconductor element is improved and the yield is improved.

〔Example〕

FIG. 1 is a perspective view showing a wafer used for manufacturing a semiconductor device according to one embodiment of the present invention, FIG. 2 is a flowchart showing the same wafer manufacturing process, and FIG. 3 is also a silicon unit provided with a main flat. FIG. 4 is a perspective view showing a crystal ingot, FIG. 4 is a cross-sectional view showing a cut state of the ingot, FIG. 5 is a partial plan view also showing the cut state of the ingot, FIG. FIG. 9 is a schematic plan view showing a main part of a semiconductor device similarly manufactured according to the present invention, FIG. 8 is a flowchart showing a manufacturing process of a semiconductor device according to one embodiment of the present invention, FIGS.
FIG. 9 is a cross-sectional view of a wafer in each manufacturing process of the semiconductor device, FIG. 9 is a cross-sectional view of a wafer subjected to buried diffusion, FIG. 10 is a cross-sectional view of a wafer on which an epitaxial growth layer is formed, and FIG. FIG. 12 is a schematic plan view showing a state in which the buried layer has grown, FIG. 12 is a plan view of an isolated wafer, FIG. 13 is a cross-sectional view of a wafer provided with a diffusion resistor, and FIG. 14 is a collector contact layer. 15 is a cross-sectional view of a wafer on which a base region is formed, FIG. 16 is a cross-sectional view of a wafer on which an emitter region is formed, and FIG. 17 is a cross-sectional view of a wafer on which electrodes are formed. It is sectional drawing.

An embodiment of the present invention will be described below with reference to the drawings.

In the present invention, a wafer (semiconductor wafer) 1 as shown in FIG. 1 is used. That is, the wafer 1 is made of silicon, and its main surface, in other words, a surface on which active elements such as transistors and diodes and passive elements such as diffusion resistors are formed, is formed of a generally used crystal plane. 100) is slightly inclined (off-angle). As shown in FIG. 1, this off-angle azimuth is inclined clockwise by θ, for example, 4 °, with respect to the <010> azimuth as viewed from the orientation flat 3. The off angle may be provided in the <00> direction. In this case, the <010> direction is set to + X direction,
If the <00> direction is the −X direction, if an off angle is provided in the <010> direction, if an epitaxial growth layer is formed on the main surface 2 of the wafer 1, a shift in epitaxial growth occurs in the + X direction, When an off-angle is provided in the <00> direction, a shift in epitaxial growth occurs in the −X direction. Note that the <001> direction is +
The Y direction is set, and the <00> direction is set to the −Y direction.

As described above, if the main surface of the wafer 1 is provided with an off-angle, when the wafer 1 is subjected to a heat treatment such as formation of an oxide film, or when heat is applied in a state where the wafer 1 is sealed in a package as a chip. However, oxidized stacking faults (OSF) are less likely to occur on the surface of the silicon substrate, and the pn junction does not deteriorate. That is, low noise can be achieved in a transistor or the like. Further, the off-angle θ for reducing the oxidized stacking faults is desirably in the range of 2.5 ° to 15 °.

The wafer 1 has an orientation flat 3
Are provided along a direction corresponding to the off-angle direction. In this direction, that is, in the silicon crystal, the crystallinity in the [100] equivalent orientation has the lowest piezoresistance effect. When semiconductor elements such as active elements are formed on the main surface of the wafer 1, as shown in FIG. 6, a rectangular chip area 6 [one chip area 6 is indicated by hatching for convenience of explanation. This chip area 6 is formed after the element formation.
By dividing the wafer 1 into a lattice, chips (semiconductor elements) are obtained. ] Is laid out along the orientation flat 3.

Therefore, as shown in FIG. 7, when two active elements 8, 9 and a passive element 10 are formed in the chip area 6, a number of effects will be obtained as described below.
In the manufacture of this semiconductor element, the active element 8,
9 as emitter (E) 11, base (B) 12,
The transistor comprising the collector (C) 13 is connected to the passive element 10
An example in which a diffusion resistor 7 is formed is shown.

The emitter 11, base 12, collector 13 and diffusion resistor 7 are each formed of a rectangular semiconductor region.

When semiconductor elements are formed using such a wafer 1, as shown in FIG. 7, the longitudinal direction or width direction (longitudinal direction in FIG. 7) of the diffusion resistor 7 extends along one side of the chip region 6. This also allows a layout that extends. This is because the conventional diffusion resistor 7 shown by the two-dot chain line in FIG.
In other words, the area of the chip region 6 can be significantly reduced as compared with the orientation flat 3 which extends obliquely to one side of the chip region 6. In addition, since the orientation of the orientation flat 3, in other words, the orientation of one side of the chip region 6, has a crystal orientation of [100] equivalent orientation,
The piezoresistive effect is minimized. Therefore, the characteristics of the element pattern portion whose characteristics become unstable due to the diffusion resistance and other piezoresistance effects are stabilized. Further, since the orientation of the orientation flat 3 is the orientation in which the piezoresistance effect is minimized, the orientation of the diffusion resistor 7 in the formation of the semiconductor element is changed to the conventional orientation as shown in FIG. It is not necessary to adopt a layout that tilts the wafer, and the usability of the wafer is improved.

Further, when semiconductor elements are formed using this wafer 1, as described above, the off angle is one-sided, for example,
In the case of the <010> orientation, when the epitaxial growth layer is formed on the main surface 2 of the wafer 1, the shift orientation of the epitaxial growth layer is <010>, and is only in the + X direction. This is the same even if the wafer 1 is turned upside down. Therefore, as shown in FIG.
The margin of mask alignment between 8 and 9 is + X
In the direction, an absolute margin α required from the relationship between a wafer processing error and a predetermined error such as equipment, and a matching margin α + Δ obtained by adding a growth deviation error Δl during epitaxial growth.
In the ± Y direction, since there is no shift of the epitaxial growth layer unlike the conventional case, the margin for mask alignment is only the absolute margin α. As a result, the chip area can be reduced in size, the profitability of chips from one wafer 1 can be increased, and the manufacturing cost of semiconductor devices can be reduced.

Further, since the longitudinal direction of the diffusion resistor 7 can be laid out along one side of the chip region 6 and the margin of the mask alignment is reduced, the pattern can be miniaturized, and the integration and the density of the semiconductor element can be increased. Can be achieved.

Next, a method of manufacturing the wafer 1 will be briefly described. As shown in the flowchart of FIG. 2, the wafer 1 is formed into a wafer by manufacturing a silicon single crystal ingot, forming an orientation flat (main surface flat), slicing the silicon single crystal ingot, polishing the mirror surface, and the like.

That is, as shown in FIG. 3, a wafer 1 is provided with a silicon single crystal ingot 15 provided with an orientation flat 3 along a generating line, as shown in FIG. 4 and FIG. It is manufactured by slicing thinly with a diamond cutting blade 17 provided on the inner peripheral edge of a blade 16 of the cutting device. Prior to the slicing, the silicon single crystal ingot 15 is fixed to a carbon support plate 18 so that the silicon single crystal ingot 15 does not fall apart even when cut by the diamond cutting blade 17. Further, the silicon single crystal ingot 15
The upper end is fixed to a holder 20 via a wax 19, and thereafter is subjected to slicing. During the slicing, the main surface 2 of the wafer 1 is off-angled as described above.

Next, the main surface 2 of the wafer 1 is mirror-finished through a mirror polishing process such as cutting and polishing. On this main surface, a semiconductor element is formed. At this time, the wafer 1
Since the orientation flat 3 and the off-angle orientation match each other after slicing, the orientation of the crystal on the main surface, that is, the formation of the epitaxial growth layer At this time, the growth shift direction of the epitaxial growth layer is constant. Therefore, it is not necessary to pay particular attention to the specification of the front and back surfaces of the wafer after slicing when forming the mirror surface. Therefore,
There is no need to provide a sub-flat on the wafer 1 for discriminating the front and back of the wafer, and it is not necessary to remodel the semiconductor device manufacturing equipment to support the sub-flat.

Next, a method for forming semiconductor elements on such a wafer 1 will be described.

In this embodiment, as shown in FIG.
An example of manufacturing 8, 9 and the passive element 10 will be described.
The active elements 8, 9 are npn transistors.
Here, since the manufacturing steps of the active elements 8 and 9 are completely the same, the following description will be made only with the active element 8.

As shown in FIG. 8, this semiconductor device has a buried diffusion step, an epitaxial growth step, an isolation step, a diffusion resistance formation step, a collector contact diffusion step, a base region formation step, an emitter region formation step, an electrode formation step, a chip It is manufactured through a series of steps.

Next, a method for manufacturing a semiconductor device will be described with reference to FIGS. 9 to 17.

First, as shown in FIG. 9, a semiconductor thin plate (wafer) 1 having a diameter of several inches is prepared. The wafer 1 is p ^-
It consists of a silicon substrate 21. The main surface of the substrate 21 is partially masked by a conventional photolithography technique, and an n-type impurity such as antimony (Sb) is deposited to form a deposition layer 23. At this time, when the insulating film (SiO ₂ film) for forming the mask is formed, the main surface of the wafer 1 is a crystal surface on which oxidation stacking faults are unlikely to occur. Oxidation stacking faults do not occur.

It should be noted that the dashed line in FIG. 3 and the subsequent figures is a portion that is cut off when the wafer 1 is formed into chips.

Next, the mask 22 is removed. Thereafter, the main surface of wafer 1 is subjected to an epitaxial growth process. By this epitaxial growth process, as shown in FIG. 10, an n ⁻ -type epitaxial growth layer 5 is formed. At this time, the deposition layer 23 is diffused with the epitaxial growth, and an n ^{+ -type} buried layer 24 is formed. During this epitaxial growth, since the wafer 1 has an off-angle structure, the buried layer 24 shifts only in the + X direction as shown in FIG. The shift of the epitaxial growth layer 5 as a whole substantially coincides with the thickness d of the epitaxial growth layer 5, but the buried layer 24 is formed by the diffusion of the deposition layer 23, and therefore is smaller than the d. c. This shift does not occur in the Y direction because the Y direction is a direction orthogonal to the off-angle direction. Therefore, in the mask alignment, taking into account the displacement of the buried layer 24, the deviation c
Need to be added. However, in this embodiment, the deviation appears only in the + X direction and does not appear in the three directions of the conventional + X direction and ± Y direction, so that the margin of alignment (margin interval) is reduced accordingly. Specifically, when the off-angle does not coincide with the direction of the side of the rectangular element pattern, the margin is a length obtained by adding twice c to the absolute margin α, as in this embodiment. In the case where the off-angle and the direction of the sides of the rectangular element pattern coincide with each other, it is not necessary to consider the deviation in the ± Y direction, so only the absolute margin α is sufficient. This allows the pattern to be downsized.

Next, as shown in FIG. 12, the insulating film 25 is partially provided by ordinary photolithography. Thereafter, an acceptor impurity such as boron (B) is diffused into a region not covered with the insulating film 25 by a diffusion technique, and a p ^{+ -type} isolation region 26 is provided. Due to this isolation, regions (islands 27, 28) where the active elements 8, 9 and the passive element 10 are formed are electrically separated from each other. In this embodiment, the margin of the mask alignment can be reduced in this isolation as described above.

Next, the insulating film 25 is removed. Thereafter, as shown in FIG. 13, the diffusion resistor 7 as the passive element 10 is provided on one of the islands 27, 28. That is, the insulating film 30 is partially provided on the main surface 2 of the wafer 1 by ordinary photolithography. Thereafter, a p-type asceptor impurity such as boron (B) is diffused into a region not covered with the insulating film 30 by a diffusion technique, thereby forming a p-type diffusion resistor 7 as the passive element 10. Since the diffused resistor 7 is provided along the active elements 8 and 9 provided in parallel as shown in FIG. 7, in other words, the diffused resistor 7 extends along one side of the rectangular chip region 6. As a result, the crystal orientation extends in a crystal orientation where the piezoresistance effect is small, and even if heat is received in various subsequent processing, the fluctuation of the resistance value of the diffusion resistance is minimized and stabilized. As shown in FIG. 7, the diffusion resistor 7 extends along one side of the chip region 6, that is, extends along the orientation flat 3 of the wafer 1. The area of the chip region 6 can be minimized as compared with the case of the diffusion resistance extending in the direction of 45 ° or 135 °.

Next, the insulating film 30 is removed. Thereafter, transistors as active elements 8 and 9 are formed on the island 27 surrounded by the isolation region 26.

Next, as shown in FIG. 14, an insulating film 31 is partially formed on the main surface of the wafer 1 by photolithography. Thereafter, an n-type impurity is diffused to form an n-type collector leading diffusion region 32 electrically connected to the buried layer 24.

Next, the insulating film 31 is removed. Thereafter, a base region 33 is formed in the island 27. That is, as shown in FIG. 15, an insulating film 34 is partially formed on the main surface of the wafer 1 by ordinary photolithography,
Thereafter, the p-type impurity is diffused into the main surface of the wafer 1 not covered with the insulating film 35 by a common diffusion technique, and the base region 33 is formed.

Next, as shown in FIG.
An n ⁺ -type emitter region 35 is formed in a part of the surface layer. That is, the insulating film 36 is again placed on the main surface of the wafer 1.
Is formed, the insulating film 36 is partially removed, and a part of the insulating film base region 33 is exposed. Thereafter, the n-type impurity is diffused to form an n ⁺ -type emitter region 35.

Next, an insulating film 37 is formed again on the main surface of the wafer 1 and the photolithography is performed by ordinary photolithography.
As shown in FIG. 17, contact holes for the emitter, base, collector and diffusion resistance electrodes are respectively provided. Then, an emitter electrode 38, a base electrode 39, a collector electrode 40, and an electrode 41 for diffusion resistance are formed. Further, after that, although not shown, the wafer 1 is formed with a passivation film on its main surface and is divided vertically and horizontally to produce a large number of chips 42 as shown in FIG.

Such a chip 42 is incorporated in a package to form a semiconductor device. That is, although not shown, the chip 42 is fixed to a support plate such as a lead frame. Thereafter, each electrode of the chip 42 is electrically connected to the inner end of an external terminal such as a corresponding lead via a wire or the like. Further, the lead frame is transferred to a packaging process such as a resin mold. In this packaging process, for example, a part of the lead frame, that is, the inner end of the lead, the support plate, the chip, the wire, and the like are sealed by a resin mold package. Further, unnecessary portions of the lead frame exposed from the package are removed. As a result, a semiconductor device is manufactured. Also, the leads protruding from the package are formed as needed.

In the manufacture of the semiconductor device, the chip 42
In some cases, heat may be applied in an assembling process such as chip bonding, wire bonding, molding, or an inspection process. However, the main surface of the substrate 21 forming the chip 42 is a crystal surface on which oxidation stacking faults are unlikely to occur. Therefore, the heat does not cause oxidative stacking faults, and various characteristics such as the diffusion resistance value do not fluctuate and can maintain a stable state. Therefore, according to the present invention, a semiconductor device having stable quality can be manufactured with a high yield.

According to such an embodiment, the following effects can be obtained.

(1) Since the main surface of the wafer used in the manufacture of the semiconductor device of the present invention is an off-angle surface in which oxidized stacking faults are unlikely to occur, deterioration of characteristics due to oxidized stacking faults does not occur. The advantage is that a semiconductor device having excellent quality can be manufactured with good reproducibility.

(2) The wafer used in the manufacture of the semiconductor device of the present invention has an off-angle structure, but the orientation flat provided on the wafer matches the orientation of the off-angle. Therefore, when the wafer is used in a front state or a back state, the off-angle direction does not change. Therefore, the wafer obtained by slicing the silicon single crystal ingot does not need to specify the front and back, and the effect of improving the usability of the wafer is obtained. That is, since it is not necessary to specify the front and back of the wafer, it is not necessary to provide a sub-flat for identifying the front and back of the wafer on the wafer, and it is not necessary to remodel the semiconductor device manufacturing equipment for the sub-flat attachment.

(3) According to (2), the orientation of the off-angle of the wafer of the present invention does not change even when the wafer is used upside down. Therefore, the growth direction of the epitaxial growth layer at the time of epitaxial growth is the XY axis along the orientation flat. Since only one axis is shifted in one direction, the margin of the mask alignment can be reduced as compared with the case where the off-angle direction and the orientation flat direction do not match.

(4) According to the above (3), according to the present invention, since the shift of epitaxial growth is in one axis and one direction and no shift occurs in the other axis direction, the pattern can be miniaturized in isolation or the like, and the chip can be miniaturized. The effect that the conversion can be achieved is obtained.

(5) According to the above (4), according to the present invention, an effect that a higher density and a higher degree of integration of a semiconductor element can be achieved can be obtained.

(6) According to the present invention, since the orientation at which the piezoresistive effect of the main surface of the wafer is minimized coincides with the orientation of the orientation flat, when a semiconductor element is formed, each rectangular semiconductor region is formed. The sides of the (element pattern) can be made to coincide with the direction in which the orientation flat extends. As a result, a piezoresistive effect acts on the formed rectangular element pattern. For example, in the case of a diffusion resistance, when a semiconductor element is manufactured or when a semiconductor device is manufactured by incorporating a semiconductor element. Even if heat is applied in, the resistance value does not fluctuate,
The advantage is that a semiconductor element and a semiconductor device having stable and excellent quality can be manufactured.

(7) In the wafer according to the present invention, since the off-angle direction and the orientation of the orientation flat coincide with each other, the rectangular element pattern as described in the above (6) can be formed by changing the longitudinal direction or width direction of the orientation flat. In the case where a diffusion resistor is provided, the longitudinal direction of the diffusion resistor can be arranged along the extending direction of another rectangular element pattern because the diffusion resistor is provided,
The effect is obtained that the size of the pattern as a whole of the semiconductor element can be reduced.

(8) According to (4) and (7), according to the present invention, it is possible to obtain an effect that a high density and high integration of a semiconductor element can be achieved.

(9) According to the above (8), according to the present invention, an effect is obtained that the semiconductor device can be downsized as the semiconductor element is downsized.

(10) According to (1) to (9), according to the present invention, a synergistic effect that a semiconductor device having excellent characteristics and high density can be provided can be provided at low cost.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. For example, the off-angle of the main surface of the wafer is provided clockwise in the above-described embodiment when viewed from the orientation flat, but the same effect as in the above-described embodiment can be obtained by providing the counterclockwise. In this case, the misalignment direction of the epitaxially grown layer is opposite to that in the above embodiment. Further, the off-angle azimuth is not limited to one position as in the embodiment, but may be any range within a certain width.
In the above embodiment, the (100) plane has been described as an example, but the present invention is not limited to the (100) plane, and is applicable to a plane equivalent to the (100) plane. Needless to say, the same effect can be obtained.

Further, in the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technique of the bipolar transistor, which is the application field in the background, has been described. However, the present invention is not limited to this. The present invention can be applied to a technique for manufacturing another semiconductor device such as a transistor.

INDUSTRIAL APPLICABILITY The present invention can be applied to at least a semiconductor device manufacturing technique which dislikes the occurrence of oxidation stacking faults and can effectively utilize the piezoresistance effect.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

Since the wafer used in the manufacture of the semiconductor device of the present invention has an off-angle structure, an oxide stacking fault is less likely to occur on the main surface of the wafer during the manufacture, and a semiconductor device having excellent characteristics is manufactured with good reproducibility. it can. Therefore, the manufacturing cost of the semiconductor device can be reduced. In addition, a rectangular element pattern is formed on the orientation flat because the orientation of the orientation flat of the wafer matches the orientation of the off angle, and when the orientation of the off angle is a silicon crystal, the piezoresistance effect is the lowest. In the manufacture of semiconductor devices that
The variation of the resistance value of the diffusion resistor can be minimized, the pattern layout can be minimized, and the margin of mask alignment can be minimized. From these facts, miniaturization, high density, and high integration of the pattern can be achieved, and miniaturization of the semiconductor element and miniaturization of the semiconductor device can be achieved. Further, in the method of manufacturing a semiconductor device according to the present invention, since it is not necessary to specify the front and back of the wafer, it is not necessary to provide a sub-flat for identifying the front and back of the wafer on the wafer, and the semiconductor corresponding to the sub-flat attachment Modification of the device manufacturing equipment is not required, and a reduction in the manufacturing cost of the semiconductor device can be achieved.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a wafer used for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a flowchart showing a wafer manufacturing process, and FIG. 3 is a silicon unit provided with a main flat similarly. FIG. 4 is a perspective view showing a crystal ingot, FIG. 4 is a sectional view showing a cut state of the ingot, FIG. 5 is a partial plan view showing a cut state of the ingot, FIG. FIG. 9 is a schematic plan view showing a main part of a semiconductor device similarly manufactured according to the present invention. FIG. 8 is a flowchart showing a manufacturing process of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view of a wafer on which an epitaxial growth layer is similarly formed, FIG. 11 is a schematic plan view showing a growth shift state of a buried layer, and FIG. FIG. 13 is a cross-sectional view of a wafer provided with a diffusion resistor, FIG. 13 is a cross-sectional view of a wafer also provided with a collector leading diffusion region, and FIG. FIG. 16 is a cross-sectional view of a wafer on which a base region is formed. FIG. 16 is a cross-sectional view of a wafer on which an emitter region is formed. FIG. 17 is a cross-sectional view of a wafer on which electrodes are formed. FIG. 19 is a cross-sectional view showing a shift state of the epitaxially grown layer, and FIG. 20 is a schematic plan view showing a main part of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Main surface, 3 ... Orientation flat (main flat), 4 ... Groove, 5 ... Epitaxial growth layer, 6 ... Chip area, 7 ... Diffusion resistance, 8, 9
…… Active element, 10 …… Passive element, 11 …… Emitter, 12
… Base, 13… Collector, 15… Silicon single crystal ingot, 16… Blade, 17… Diamond cutting blade,
18 ... carbon support plate, 19 ... wax, 20 ... holder, 21 ... substrate, 22 ... mask, 23 ... devotion layer, 24 ... buried layer, 25 ... insulating film, 26 ... isolation Region, 27, 28 island region, 30, 31 insulating film, 32 collector diffusion region, 33 base region, 34 insulating film, 35 emitter region, 36, 37
... insulating film, 38 ... emitter electrode, 39 ... base electrode, 40
…… Collector electrode, 41… Diffusion resistor electrode, 42… Chip.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication H01L 29/04 29/73

Claims (2)

(57) [Claims] 1. A principal plane having a plane in which (100) of a crystal is inclined at a predetermined angle to a <010> direction, or a plane equivalent to the plane, and an orientation flat in a direction along the inclination direction. A semiconductor wafer provided is prepared, an epitaxial growth layer is formed on one main surface of the semiconductor wafer, a semiconductor region is formed in the epitaxial growth layer, and the longitudinal direction is the <010> or <001> orientation of the crystal orientation. Or a method of manufacturing a semiconductor device, wherein the semiconductor device is formed so as to extend along an orientation equivalent to the orientation. 2. The method according to claim 1, wherein said semiconductor region forms a diffusion resistor.