JP2760401B2 - Dielectric separation substrate and semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate of a semiconductor integrated circuit device and a semiconductor device.
The present invention relates to a dielectric isolation substrate and a semiconductor device suitable for high integration.

[Related Art] In recent years, demands for power semiconductor integrated circuit devices are increasing in technical fields such as home appliances and automobiles. This type of semiconductor integrated circuit device has a high breakdown voltage (100 V or more), large current (1 A or more) output element, and a signal processing circuit composed of a low voltage and low current element compatible with a transistor-transistor logic (TTL) circuit. Are monolithically integrated.

As a conventional technique related to such a power semiconductor integrated circuit device, for example, a technique described in Japanese Patent Application Laid-Open No. 60-80243 is known.

The prior art of this type of semiconductor integrated circuit device will be described below with reference to the drawings.

FIG. 7 is a sectional view showing the structure of a dielectric isolation substrate for a semiconductor integrated circuit device according to the prior art, FIG. 8 is a view for explaining the manufacturing method, FIG. 9 (a) is a sectional view of an isolation groove, FIG. 9 (b) is a plan view near the island corner. 7 to 9, 1 is a single crystal Si region for a large current element, 2 is a single crystal Si region for a small current element, 3 is an oxide film, 4 is a high concentration impurity buried layer, 5 is a support substrate material, 9 is a single crystal part for forming a large current element, 15 is a substrate, 18 is a separation groove, 25 is a groove etching window, 27 is a single crystal layer, 29 is a large current element, and 32 is a single crystal island.

As shown in FIG. 7, a dielectric isolation substrate according to the prior art includes a plurality of single crystal islands 32 provided in a support substrate material 5 and insulated by a dielectric isolation film such as a Si oxide film 3 or the like. A single crystal island is formed by the large current element forming single crystal portion 9 which is not electrically separated from the substrate material 5. The single-crystal portion 9 for forming a large-current element forms the single-crystal Si region 1 for a large-current element. In the illustrated example, a high-breakdown-voltage, large-current npn transistor is formed on the first main surface 23 of the substrate. With the base 28 and the second main surface 24 of the substrate
With 30, a large current element 29 is formed. The single crystal island 32 is exposed only on the first main surface 23 of the substrate and the other portion is covered with an oxide film to form the single crystal region 2 for a low breakdown voltage and low current element. In, a resistor, an npn transistor, and a diode are respectively formed.
The oxide film 3 insulates and separates the single crystal regions 1 and 2 from each other, thereby enabling high voltage separation between elements. The bottom surface of the single crystal portion 9 for forming a large current element is not covered with the insulating film 3 having low thermal conductivity, and the second main surface of the substrate is formed.
24 are in contact with a metal having high thermal conductivity bonded to the mounting package. For this reason, the large current element 29 can satisfactorily dissipate heat and can increase power.

A method for manufacturing a dielectric isolation substrate having such a configuration will be described below with reference to FIG.

(1) High concentration impurity buried layer 4
Is formed by a thermal diffusion method, and a groove edge window 25 for forming a groove for separation is formed by photolithography (FIG. 8A).

(2) Next, a separation groove 18 is formed by performing a so-called anisotropic etching using an alkaline etching solution of a mixed solution of a KOH aqueous solution and an alcohol [FIG. 8 (b)].

(3) Next, an oxide film 3 for insulating isolation is formed on the surface of the substrate 15 where the groove 18 is formed, and the oxide film 3 in a portion to be the single crystal Si region 1 for a large current element is removed. Next, a support substrate material 5 is formed thereon by vapor-phase growing a Si layer to a thickness of about 500 μm. In this case, a support substrate material 5 made of a polycrystalline layer is provided on the surface on which the insulating film 3 is formed, and a single crystal layer is provided on the surface of the high-concentration impurity buried layer 4 where the insulating film 3 is removed. 27, the supporting substrate material 5 is formed. Since the single crystal layer 27 becomes a current path of the large current element 29, the resistance is reduced by adding a high concentration impurity [FIG. 8 (c)].

(4) Next, the back surface of the substrate 15 without the separation groove 18 is polished,
Alternatively, the insulating film 3 is exposed by etching or the like to expose the insulating film 3. As a result, the region that is a part of the substrate 15 is separated into a single crystal island 32 covered with the insulating film 3 and an island formed by the single crystal part 9 surrounded by the insulating film 3, and The separation substrate is completed [FIG. 8 (d)].

(5) An element is formed in the completed dielectric physical substrate through a usual photolithography step, oxidation, diffusion, film forming step, etc. [FIG. 8 (e)].

In the semiconductor element in the dielectric isolation substrate formed as described above, the breakdown voltage between the base 28 and the collector 30 of the npn transistor as the large current element 29 depends on the portion of the substrate where the element is formed (hereinafter referred to as island). Is limited by the thickness of the single crystal portion (hereinafter also referred to as i-layer) having the lowest impurity concentration. That is, as the thickness 31 of the i-layer is larger, an element having a higher withstand voltage can be obtained, and the island for forming a large current element which requires a higher withstand voltage only has the i-layer satisfying the withstand voltage requirement of the element. Is required.

On the other hand, the thickness of the i-layer in the single crystal island 32 on which the low current element is formed is not as required as the island for the high breakdown voltage element, and it is preferable that the thickness be as thin as possible from the viewpoint of the degree of integration of the semiconductor device.

 Hereinafter, this will be described with reference to FIG.

Generally, in order to increase the thickness of the single crystal island, that is, the thickness of the i-layer, the isolation groove 18 may be etched deeply when the isolation groove 18 is formed. As shown in FIG. 9 (a), the separation groove 18 has a substantially triangular shape. Therefore, when the separation groove 18 is deeply etched, its groove width becomes large. Also,
In order to etch the separation groove 18 deeply, the etching time becomes longer, and as a result, at the portion where the separation groove 18 intersects,
The width of the separation groove is further increased. For this reason, as shown in the bottom plane of the single crystal island 32 in FIG. 9B, the amount of invasion of the island indicated by the parameter x becomes large, and the vicinity of the corner of the island 32 is invaded.

That is, when the depth of the separation groove is increased to increase the thickness of the i-layer for the high withstand voltage element, the width of the separation groove is widened, and the corner of the single crystal island is invaded, so that the planar dimension of the island is reduced. At the same time, the thickness of the i-layer in the island may not be uniform, and the reproducibility of the island shape is deteriorated, and the yield of the formed element is also deteriorated. Therefore, in the above-described prior art, the minimum size of the island is limited in order to avoid such a problem.

[Problems to be Solved by the Invention] As described above, in the prior art, as the thickness of the short crystal island is increased, the minimum dimension of the island is greatly limited, and an unnecessary large island is required. In some cases, there is a problem that the withstand voltage of a high-voltage element and a large-current element is reduced when the thickness of the island is reduced as much as possible to improve the degree of integration. That is, as is apparent from the manufacturing method described with reference to FIG. 8, the thickness of the island is the same for all the elements. Accordingly, if the i-layer of the single crystal island 9 for the high-voltage high-current element is made thick enough to ensure the withstand voltage of this element, the thickness of the single-crystal island 32 for the other low-voltage low-current element also increases accordingly. Therefore, there is a problem that the minimum island size becomes large and the degree of integration cannot be increased.

Further, the above-described conventional technology has the following problems. That is, in the manufacturing method described with reference to FIG. 8, high-concentration impurities are added by the high-temperature and long-time heat treatment in the Si vapor phase growth in FIG. 8C and the device forming step in FIG. 8E. Impurities diffuse from the single crystal layer 27 and the high-concentration buried layer 4 into the island 9 where the element, which is the i-layer, is formed, as shown by arrows in FIGS. 8 (c) and 8 (e). At this time, a material different from the impurity in the high concentration buried layer 4 is used as the impurity in the single crystal layer 27, and the impurity in the single crystal layer 27 passes through the high concentration buried layer 4 in a larger amount. Spread in island 9. For this reason, the prior art is based on i
The thickness of the layer is reduced, and in order to ensure the high withstand voltage of the element formed in this island without being affected by this, the thickness of the island must be adjusted in consideration of the impurity diffusion described above. It must be increased, which causes a problem that the degree of integration of the low-voltage low-current element is reduced.

In the above-described step of growing the Si layer in FIG. 8 (c), the deposition rate is reduced in order to dope impurities at a high concentration. Therefore, during high-temperature vapor phase growth, oxide film 3 is exposed to an atmosphere of H ₂ gas, which is a carrier gas for growth, for a long time. For this reason, in the prior art, the etching effect of the oxide film 3 by the H ₂ gas becomes remarkable, the thickness of the oxide film 3 becomes thinner, and the occurrence of pinholes increases. Has a problem that the yield is deteriorated.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to reduce the island thickness while maintaining the breakdown voltage of a high breakdown voltage element, thereby improving the degree of circuit integration and a semiconductor device. It is to provide a device.

Means for Solving the Problems According to the present invention, the object is to provide a first single crystal region covered with an insulating film, a second single crystal region partially covered with an insulating film, A third single crystal region not covered with a film, wherein the first to third single crystal regions have the same impurity concentration, and the third single crystal region is covered by a fourth single crystal region. In the dielectric isolation substrate configured as described above, the fourth single crystal region is formed of a low concentration impurity layer and a high concentration impurity layer, and the low concentration impurity layer is formed of the second,
A buried layer provided in contact with the third single-crystal region and connecting a buried layer provided in the second single-crystal region to a high-concentration impurity layer in the fourth single-crystal region; This is achieved by further providing

[Operation] In the first stage of growing the support substrate material, a low-concentration impurity region is formed to a predetermined thickness, and then a high-concentration impurity layer is grown. In the heat treatment step, the impurity is diffused from the high-concentration impurity region to the low-concentration impurity region, and a transition region having a high concentration is formed in the low-concentration impurity region. For this reason,
The diffusion of the impurity into the i-layer of the island is prevented and reduced in the transition region, and the diffusion amount and the diffusion depth of the i-layer of the impurity are reduced or are not generated at all, and the thickness of the island is reduced. Even so, the thickness of the i-layer required for the withstand voltage can be ensured.

In addition, a part of the i-layer or the low-concentration layer, which is the minimum concentration layer necessary for the breakdown voltage of the element, can be grown in the support substrate material, and the thickness required for the breakdown voltage in the island can be reduced. That is, a high withstand voltage can be realized with a small island thickness.

Furthermore, since the low-concentration impurity region of the supporting substrate material is grown in contact with the oxide film as the insulating film, the growth rate in the initial stage of the growth can be increased, and the oxide film is exposed to the H ₂ gas atmosphere as the carrier gas. The time becomes smaller,
The etching amount of the oxide film can be reduced. As a result, it is possible to improve the yield of the withstand voltage between elements.

Embodiments Hereinafter, embodiments of the dielectric isolation substrate and the semiconductor device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view showing the configuration of a first embodiment of the present invention,
2 is a sectional view taken along the line AA 'in FIG. 1, FIG. 3 is a sectional view showing the structure of a second embodiment of the present invention, and FIG. 4 is a sectional view showing the structure of a third embodiment of the present invention. FIG. 5 is a view for explaining the manufacturing method of the first and second embodiments, and FIG.
FIG. 6 is a view for explaining a manufacturing method according to the example. Figures 1 to 6
In the figure, 6 is an n-type low concentration growth layer, 7 is a p-type high concentration growth layer, 8 is a main surface of a single crystal region, 10 is an n-type medium concentration growth layer,
Numeral 11 denotes a first oxide film, numeral 12 denotes a second oxide film, numerals 13 and 14 denote n-type high-concentration growth layers, numeral 17 denotes a groove, and other symbols are the same as those in FIGS.

In the first embodiment of the present invention, as shown in FIGS. 1 and 2, a second n-type single crystal region 1 for forming a high-breakdown-voltage, large-current element penetrating a substrate is provided. And a first n-type single crystal region 2 covered with oxide film 3. An n-type high-concentration buried layer 4 is formed on all the islands constituted by the single crystal regions 1 and 2. The supporting substrate material 5
The n-type low-concentration growth layer 6 is composed of an n-type low-concentration growth layer 6 and a P-type high-concentration growth layer 7. The n-type low-concentration growth layer 6 is an oxide film 3 that is an insulating film and the first n from which the oxide film 3 is removed. It is provided so as to be in contact with bottom n-type high concentration buried layer 4 of type single crystal region 1. The n-type low-concentration growth layer 6 and the p-type high-concentration growth layer 7 constituting the supporting substrate material 5 have a single-crystal Si structure at a portion continuous with the n-type high-concentration buried layer 4 and a polycrystalline structure at other portions. It has a Si structure. The portion of the p-type high-concentration growth layer 7 having the single-crystal Si structure is connected to the second n-type single-crystal region 1 and is exposed to the third single-crystal region on the second main surface of the substrate.
It becomes a Si region.

An IGBT was manufactured in the second n-type single crystal region 1 on the first main surface 8 side of the dielectric isolation substrate configured as described above. In this case, the impurity from the p-type high-concentration growth layer 7 is diffused into the n-type low-concentration growth layer 6 during the heat treatment process, and becomes a p-type transition region. Further, the buried layer 4 functions as a layer for improving the lapping resistance of the manufactured device.

According to the above-described first embodiment of the present invention, during the long-term high-temperature heat treatment at the time of element formation, the impurity, for example, B (boron) from the p-type high-concentration growth layer 7 is removed from the high-concentration impurity buried layer. 4 can be prevented from being diffused into the island by the n-type low-concentration growth layer 6 serving as the p-type transition region. It can be reduced to about 80%, and the minimum island size is reduced to 80%, and the entire chip area of the semiconductor integrated circuit is reduced.
It could be reduced to 90%.

As shown in FIG. 3, the second embodiment of the present invention is the first n-type single crystal in the first embodiment of the present invention.
The n-type high-concentration buried layer 4 in the portion of the Si region 1 where the oxide film 3 has been removed is removed, and the supporting substrate material 5 is made of a second n-type single crystal.
An n-type low-concentration growth layer 6 and a p-type high-concentration growth layer 7 having the same impurity concentration as the i-layer 9 in the Si region 1 are provided in the middle of these growth layers 6 and 7. , 7 having an intermediate impurity concentration of n-type. The speed of the thickness of these growth layers and the doping conditions are increased in consideration of diffusion of impurities into the i-layer in the heat treatment step. As in the first embodiment, the portion of the growth layer following the second n-type single-crystal Si region 1 has a single-crystal Si structure, and the other portions have a polycrystalline Si structure.

An IGBT was formed in the first n-type single crystal region 1 on the first main surface 8 side of the dielectric isolation substrate configured as described above, as in the case of the first embodiment. In this case, n-type medium-concentration growth layer 10 functions as a buffer layer for preventing diffusion of impurities from p-type high-concentration growth layer 7 into i-layer in first n-type single crystal region 1.

According to the above-described second embodiment of the present invention, it is possible to form a low-concentration layer for obtaining a withstand voltage of an element, that is, a part of the i-layer, in the support substrate material 5, and to form the i-layer in the island. Layer 9
And the thickness of the i-layer in the island, that is, the island thickness can be reduced to approximately 60% of that of the prior art, and the minimum island size can be reduced to approximately 70%. The overall chip area was reduced to about 80%.

The third embodiment of the present invention makes it possible to provide a plurality of n-type single crystal regions 1 for forming a high withstand voltage and large current element in the same substrate. The n-type single crystal region 1 is covered with a first oxide film 11 and a second oxide film 12, and an i-layer, which is a low-concentration region, is formed in the center as a third region. Second regions having the same configuration are arranged on both sides. A first region for forming a low-voltage low-current element (not shown) is covered with an oxide film with a single crystal region having the same thickness and the same impurity concentration as the above-mentioned i-layer, and a peripheral portion of the n-type single crystal region. And is formed.
A high-concentration impurity buried layer 4 is formed in the i-layer forming the second and third islands, and a transition region formed by an n-type low-concentration growth layer 6 is formed in contact with the buried layer 4. Third
A fourth region of the n-type high-concentration growth layer 13 covering the third region is provided so as to fill the space between the regions. Further, a second oxide film 12 is provided so as to be in contact with the first oxide film 1 around the n-type single crystal region 1 and to cover the n-type high-concentration growth layer 13. An n-type high-concentration growth layer 14 which is in contact with the support substrate material 5 is provided. In the embodiment shown in FIG. 4, the third
The high concentration impurity buried layer 4 at the bottom of the island is removed.

A vertical MOS device having a high withstand voltage was formed in the third island at the center of the n-type single crystal region 1 of the dielectric isolation substrate configured as described above. In this case, the on-current flowing through the element changes from the electrode provided on the surface to the buried layer 4 as shown by the arrow in FIG.
It flows through the n-type high concentration growth layer 13 to the MOS element in the island.

According to the above-described third embodiment of the present invention, the transition region formed by the low-concentration growth layer 6 can prevent impurities from the high-concentration growth layer 13 from entering the i-layer, thereby obtaining a predetermined breakdown voltage. The required island thickness is 60
%, And the minimum island size to about 70%,
The overall chip area of the semiconductor integrated circuit was reduced to about 80%.

In the above-described third embodiment of the present invention, when the thickness of the low-concentration growth layer 6 is large and the resistance between the high-concentration growth layer 13 and the high-concentration buried layer 4 increases, A high-concentration buried layer 4 ′ connecting the high-concentration growth layer 13 and the high-concentration buried layer 4 can be added at a position along the groove 17 of the second oxide film 12.

In the above-described dielectric isolation substrate according to the third embodiment of the present invention, since the single crystal region 1 forming the high withstand voltage and large current element is insulated and separated by the oxide film, a plurality of high withstand voltage and large current elements are provided. Can be formed in the same substrate.

Further, the first, second, and third embodiments of the present invention described above can be manufactured by growing a low-concentration layer at the beginning of the formation of the Si layer growth layer as a supporting substrate material, so The amount of etching of the oxide film, which is a film, during the growth of the above-described Si layer can be reduced, and the inter-element breakdown voltage yield can be improved.

Next, a manufacturing method for obtaining the dielectric isolation substrate of the first and second embodiments of the present invention will be described with reference to FIG.

(1) An n-type single crystal substrate 15 having a crystal face (100) is prepared, an isolation groove 18 is formed in the same manner as in the prior art, and a high-concentration impurity buried layer 4 is formed. To form After that, the insulating oxide film 3 in the portion 16 of the high withstand voltage and large current element forming region is etched and removed (FIG. 5A).

(2) Next, the Si growth layers 6, 7 or 6, 10, 7 are grown by vapor phase. Each growth layer is grown while being doped so as to have a predetermined impurity concentration. In this case, the dopant and the doping amount are controlled by adjusting the source gas flow and the doping gas flow. After the completion of the growth of the Si growth layer serving as a support substrate, the substrate 15 is subjected to a polishing process in the same manner as in the prior art to complete a dielectric isolation substrate [FIG. 5 (b)].

In the case of the substrate according to the second embodiment of the present invention, the above-described high-concentration impurity buried layer 4 is doped with impurities by masking unnecessary portions of the buried layer 4 by means such as masking. By doing so. Thus, the dielectric isolation substrate according to the second embodiment of the present invention described with reference to FIG. 3 can be manufactured.

Next, a method of manufacturing a dielectric isolation substrate according to a third embodiment of the present invention will be described with reference to FIG.

(1) As in the first and second embodiments, after forming the first isolation groove 18, the high-concentration impurity buried layer 4 is formed only in a predetermined necessary part, and the first insulating An oxide film 11 is formed, and a predetermined portion of the oxide film 11 is removed to form a window [FIG. 6 (a)].

(2) The low concentration Si growth layer 6 and the high concentration Si growth layer 13
As in the first and second embodiments, vapor-phase growth is performed while doping impurities [FIG. 6 (b)].

(3) Next, a second isolation groove 17 is formed around the high-breakdown-voltage, large-current element formation region until it contacts the first oxide film 11, and a second oxide film 12 is formed thereon [ FIG. 6 (c)].

(4) Next, a high-concentration Si growth layer 14 is vapor-phase grown, a predetermined portion of the single crystal substrate 15 is polished, and the Si region for element formation is separated, so that the dielectric isolation substrate is separated. It is completed [Fig. 6 (d)].

In the above, the low concentration region 6 is thick and the high concentration
In the case where the resistance between the semiconductor layer and the high-concentration buried layer 4 becomes large, a step of forming a low-resistance buried layer on the surface of the groove by the deposition of impurities after the formation of the second isolation groove 17 is added. Can be reduced.

[Effects of the Invention] As described above, according to the present invention, it is possible to reduce the thickness of a single crystal island for obtaining a withstand voltage required for a high withstand voltage and large current element, thereby reducing the size of the minimum island. Therefore, the degree of integration of the semiconductor integrated circuit device can be improved, and the overall chip area can be reduced. Further, according to the present invention, the yield of the dielectric strength between the elements can be improved. As a result, the number of chips manufactured from one wafer can be increased, so that a semiconductor integrated circuit can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a plan view showing the structure of a first embodiment of the present invention, FIG. 2 is a sectional view taken along line AA 'in FIG. 1, and FIGS. 3 and 4 are second and third embodiments of the present invention. FIG. 5 is a cross-sectional view showing the structure of the first embodiment, FIG. 5 is a diagram for explaining the manufacturing method of the first and second embodiments,
FIG. 6 is a view for explaining the manufacturing method of the third embodiment, FIG. 7 is a cross-sectional view showing an example of the structure of the prior art, FIG. 8 is a view for explaining the manufacturing method, and FIG. Is a sectional view of the separation groove,
FIG. 9 (b) is a plan view near the island corner. DESCRIPTION OF SYMBOLS 1 ... Single-crystal Si area | region for large-current elements, 2 ... Single-crystal Si area | region for small-current elements, 3,11,12 ... Insulating film, 4 ... High-concentration impurity buried layer, 5 ... Support substrate material, 6 n-type low-concentration growth layer, 7 p-type high-concentration growth layer, 8 main surface of single-crystal region, 9 single-crystal part, 10 n-type medium-concentration growth layer, 13, 14
... N-type high concentration growth layer, 15 n-type single crystal substrate, 17, 18
…… Separation groove, 25… Groove edge window, 32 …… Single crystal island.

Continued on the front page (72) Inventor Toru Ishikawa 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-51-11581 (JP, A) (58) Fields investigated .Cl. ⁶ , DB name) H01L 21/76-21/765 H01L 21/336 H01L 29/78

Claims (4)

(57) [Claims] 1. A first single crystal region covered with an insulating film, a second single crystal region partially covered with an insulating film, and a third single crystal region not covered with an insulating film. And the first
To the third single crystal region have the same impurity concentration,
A single-crystal region covered by a fourth single-crystal region, wherein the fourth single-crystal region includes a low-concentration impurity layer and a high-concentration impurity layer; A dielectric isolation substrate, wherein a low concentration impurity layer is provided in contact with the second and third single crystal regions. 2. The semiconductor device according to claim 1, further comprising: a buried layer provided in said second single crystal region and a buried layer connecting a high concentration impurity layer in said fourth single crystal region. 2. The dielectric isolation substrate according to claim 1, wherein 3. A semiconductor device formed by forming a semiconductor element in a dielectric isolation substrate, wherein the dielectric isolation substrate is exposed on a first main surface of the substrate, and an area other than the exposed surface is an insulating film. A covered first single-crystal region, a second single-crystal region exposed on the first main surface of the substrate and partially covered with an insulating film except for the exposed surface, and a part of the second single-crystal region on the substrate. A third single-crystal region exposed to the second main surface and connected to the second single-crystal region, and a support substrate material whose other portion is made of a polycrystalline region; , A low-concentration impurity layer and a high-concentration impurity layer, and the low-concentration impurity layer is provided in contact with the insulating film, and at least one of the semiconductor elements is connected to the second single-crystal region. Is formed as a vertical semiconductor element in a region extending from Wherein a. 4. A semiconductor device comprising a semiconductor element formed in a dielectric isolation substrate, wherein the dielectric substrate is exposed on a first main surface of the substrate, and a portion other than the exposed surface is covered with an insulating film. A first single-crystal region, a second single-crystal region penetrating the substrate, and a polycrystalline region, wherein the thickness of the lowest concentration region in the second single-crystal region is the first single-crystal region. A semiconductor device, wherein the thickness is larger than the thickness of the lowest concentration region in the crystal region, and at least one of the semiconductor elements is formed as a vertical semiconductor element in the second single crystal region.