JPS6352465B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lateral type semiconductor device, and more particularly to a lateral type transistor with high breakdown voltage and high current amplification rate suitable for integrated circuits.

In conventional integrated circuit devices (hereinafter referred to as ICs), planar structures are widely used as npn transistors. On the other hand, lateral structures are widely used for PNP transistors. This is due in part to the fact that the planar structure and fabrication process are compatible. That is, since it can be formed using a diffusion process for forming the p base of an npn transistor, there is no need to complicate the process.

However, the conventional lateral type pnp transistor having a pn junction isolation structure as shown in FIG. 1 is unsatisfactory in that the current amplification rate is small. This is due to the following reason.

p emitter 4, n base 10 and p substrate 11
As a result, a parasitic pnp transistor is formed, so not all of the minority carriers, that is, holes, injected from the p emitter 4 to the n base are diffused or drifted toward the p collector 5, and some of them are shown in the figure. P substrate 11 as shown by dotted line (a)
leaks to.

Not all of the holes diffused in the direction of the p-collector 5 are collected by the p-collector 5, but some of them diffuse through the n-base between the p-collector 5 and the n ⁺ buried layer 6, and the dotted line in the figure It flows out to the p-substrate 11 as shown in b.

The problem of a small current amplification factor becomes even more serious when a lateral type PNP transistor is made to have a high breakdown voltage. Firstly, in order to increase the breakdown voltage, it is necessary to increase the distance between the p collector 5 and the p emitter 4, that is, the n base width, in order to prevent punch-through when a high voltage is applied.
However, increasing the n-base width further reduces the current amplification rate. Secondly, when the depletion layer reaches the n ⁺ buried layer 6 when a high voltage is applied, the extension of the depletion layer is suppressed, and as a result, the electric field strength near the collector junction (emitter junction when reverse biased) increases and the withstand voltage increases. causing a decline.

Therefore, p collector 5 (and p emitter 4)
It is necessary to make the distance between the n ⁺ buried layer 6 and the depletion layer large enough to prevent the depletion layer from reaching the n ⁺ buried layer 6 when a breakdown voltage is applied. For this reason, there is a tendency that the number of holes flowing into the p-substrate increases as described above and further reduces the current amplification rate.

An object of the present invention is to solve the problems of the prior art and to provide a lateral type semiconductor device with high breakdown voltage and high current amplification rate suitable for IC implementation.

This purpose uses dielectric isolation technology to separate IC components, and creates a highly concentrated semiconductor region of the same conductivity type as the base between the single crystal island forming the lateral transistor and the dielectric film. and the high-concentration semiconductor region are made smaller than the distance between the collector and the high-concentration semiconductor region, and one of the electrodes in contact with the collector and the emitter extends over the high-concentration semiconductor region via a passivation film,
This is achieved by providing electric field relaxation means below this extended electrode.

In other words, high breakdown voltage is achieved by setting the distance between the collector and the highly doped semiconductor region to the distance necessary to obtain a predetermined high breakdown voltage, that is, the distance equivalent to the width of the depletion layer extending within the n-base when a breakdown voltage is applied. can.

On the other hand, the distance between the emitter and the high-concentration semiconductor region can be reduced to the extent that injection from the emitter cannot be prevented, since there is no need to make the emitter junction high withstand voltage. Therefore, the minority carriers injected from the emitter into the base and diffused toward the bottom and sidewalls of the single crystal island are reflected by the diffused electric field from the heavily doped semiconductor region toward the base and proceed toward the collector. In this case, since the thickness of the base interposed between the emitter and the high-concentration semiconductor region can be made narrower than the diffusion length of minority carriers, the number of carriers that recombine and disappear in this region can be significantly reduced. As a result, the current amplification rate can be increased.

Furthermore, in ICs, interconnections are formed on single-crystal islands via a buffering film, and the potential applied to the interconnects changes the spread of the depletion layer formed within the single-crystal islands, causing abnormal electric field concentration. This may lead to a drop in withstand pressure. However, in the present invention, since an electric field relaxation means is provided under the wiring, abnormal electric field concentration can be removed and high breakdown voltage can be ensured. The simplest way to alleviate this electric field is, for example, to provide a stepped portion in the passivation film under the wiring.

Hereinafter, the contents and effects of the present invention will be explained in detail based on specific examples.

FIG. 2 shows one embodiment of the present invention, which is a lateral PNP transistor with high breakdown voltage and high current amplification rate.
A p emitter 4 is formed near the center of a single crystal island 3 insulated from a polycrystalline Si 2 by a SiO ₂ film 1, and a p collector 5 is formed around it. For insulation
An n ⁺ high concentration diffusion region 6 is formed in the single crystal island portion along the SiO ₂ film 1 . Polycrystalline Si under p emitter
2 and n ⁺ region 6 are made to protrude into the single crystal compared to the area below the p collector, and the distance between the p emitter and the n ⁺ region is smaller than other parts.
As a result, the current amplification rate can be increased without impairing the withstand voltage due to the above-described mechanism.

The specific resistance of the single crystal island n region 3 in this example is
20Ω・cm, the diffusion depth of p layers 4, 5 and n ⁺ layer 6 are all 15 μm, the distance between p emitter 4 and p collector 5 is 40 μm, and the distance between p collector 5 and n ⁺ layer 6 is
35μm, distance between p emitter 4 and n ⁺ layer 6 is approximately 10μm
It is.

Electrode 7 of p collector 5 is for passivation
Each of them extends beyond the junction via a SiO ₂ film 8. As is well known, this is what is called a field plate, and is a means of reducing electric field concentration in the vicinity of the Si surface of the collector junction due to the electric field effect, thereby improving the withstand voltage. p emitsuta 4
The electrode 9 is also similar, but this is the collector
This is a means of blocking channels that occur on the Si surface between the emitters using an electric field effect and preventing them from forming under the emitter electrodes, which can further improve the breakdown voltage. In addition, the collector wiring 7 extends over the exposed portion on the surface of the n ⁺ region via the SiO ₂ film 8 and connects other
Connected to IC components. Normally, a channel is generated on the Si surface under the electrode due to the electric field effect.

Also, if there is no n ⁺ region on the side wall of single crystal island 3,
Since the crystallinity near the interface between the insulating SiO ₂ film 1 and the single crystal Si island 3 deteriorates, an inversion layer is formed when the potential of the polycrystalline Si 2 becomes lower than the potential of the single crystal Si island 3. There are often Therefore, in this case, the leakage current increases due to the connection with the channel. In this example, the n ⁺ region was also formed on the sidewall of the single crystal in order to suppress the generation of an inversion layer and to minimize the volume of the channel, that is, the leakage current, to improve the breakdown voltage.

In this case, electric field concentration occurs at the end of the channel in the n ⁺ region below the electrode 7, leading to a drop in breakdown voltage, so the passivation SiO ₂ film 8 on the n ⁺ region 6 is made thicker than on and near the p collector 5. This is intended to alleviate electric field concentration and improve breakdown voltage. In this way, the SiO ₂ film 8 for passivation is applied to the p collector 5.
By making it thinner on and near the n ⁺ region 6 and thicker on and near the n ⁺ region 6, and providing a stepped portion located between the p collector 5 and the n+ region 6, electric field concentration occurs in this region as well. Electric field concentration on the collector 5 side and the n ⁺ region 6 side can be alleviated. It is better to lower the concentration of the n ⁺ region in order to reduce the electric field strength at the end of the channel, but in order to increase the diffusion electric field at the interface with the n base and efficiently reflect the holes injected from the emitter. The higher the concentration, the better. In order to achieve both effects in a compatible manner, in this example, the impurity concentration at the surface of the n ⁺ diffusion region (concentration near the interface with insulating SiO ₂ ) is set to 5×10 ¹⁶
~5×10 ¹⁸ pieces/ ^cm3 .

The pnp transistor in this example has a breakdown voltage of 400~
450v, current amplification rate was 8-12. In FIG. 2, in a transistor with a conventional structure in which the polycrystalline Si2 on the lower side of the p emitter 4 does not protrude, the current amplification factor is 4 to 6 when the breakdown voltage is the same, which clearly shows the effect of the present invention. . In addition, in Figure 2,
The current amplification factor of a conventional dielectrically isolated lateral transistor without the n ⁺ region 6 or its protrusion is 1.5.
It is significantly smaller at ~2.5.

FIG. 3 shows a second embodiment of the invention. The first difference is that the protrusion of the polycrystalline region is increased.
This is the same as the embodiment. If the shortest distance between the p collector 5 and the n ⁺ region 6 is set to about 30 μm, the withstand voltage will decrease slightly to 380 to 420 v, but the current amplification rate will be 15 to 420 v.
I was able to increase it to 18.

FIG. 4 shows a third embodiment of the present invention. As is clear from the comparison with Fig. 3, the p-emitter junction depth is made 5 μm shallower than that of the p-collector 5,
This is almost the same as Example 2 except that the surface concentration was set to 3×10 ¹⁹ cm ^-3 to increase the injection efficiency from the emitter. In the case of this example, the withstand voltage is 380
It is equivalent to ~410v, but the current amplification rate could be further increased to 18-23.

FIG. 5 is a cross-sectional view showing an example of a method for manufacturing a dielectric isolation substrate according to the present invention used in the first to third embodiments in the order of steps.

oxidizing the n-type Si substrate 3 to form a SiO ₂ film 13;
A first resist film 14 is coated thereon and hot-etched to form windows A and B to form windows A and A. Then, the first resist film 14 is removed,
Further, a second resist film 15 is provided, and a second photoetching is performed to leave only the window 1, and b
Process it into the shape of. The opening A is a portion where an insulation isolation groove is to be formed, and its size is made to be larger than the opening formed by the first photoetching.

Next, selective etching of Si is performed to form a separation groove halfway and process it into the shape of c. in this case
The SiO ₂ film 13 is used as a mask for Si etching. After that, the second resist 15 is removed, and selective etching is performed to form the isolation groove A and the polycrystal.
A groove B, which is to become a protrusion of Si, is formed into a shape of d. Thereafter, oxide film 15 is removed to form n ⁺ layer 6, and then oxide film 1 is formed thereon. Next, polycrystalline Si2 is grown, and then the surface on the single crystal side is polished into the shape of e to complete the dielectric isolation substrate. The subsequent device formation process is the same as a known method, so a description thereof will be omitted.

In the manufacturing method explained in Fig. 5, grooves of different depths are simultaneously opened by the first photoetching process.
Since it can be formed using the SiO ₂ film as a mask, the distance between the grooves and their relative positions can be formed with high precision. These points are also features not seen in the prior art. In addition, if the opening B in FIG. 5a is made smaller, the embodiment shown in FIG. 2 can be realized, and if it is made larger, the embodiment shown in FIG. 3 can be realized.

The present invention is not limited to the above-described embodiments, and those skilled in the art will readily recognize that various modifications can be made. The present invention can also be applied to a lateral thyristor in which an n-layer is formed in the p-collector 5, and as a result, the ignition current and FVD can be reduced due to an increase in the current amplification factor.

As described above, according to the present invention, it is possible to realize a lateral type semiconductor device with high breakdown voltage and high current amplification rate suitable for IC implementation.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of a conventional lateral type transistor, FIGS. 2 to 4 are cross-sectional views of an embodiment of the present invention, and FIG. 5 is a cross-sectional view showing an example of a method for manufacturing the transistor of the present invention. It is a diagram. 1...SiO ₂ film for insulation, 2...Polycrystalline Si, 3...
...Single crystal Si island, 4...n emitter, 5...p collector, 6...n ⁺ high concentration region, 13...SiO ₂ film,
14...first resist film, 15...second resist film.

Claims (1)

[Claims] 1. A monocrystalline island of one conductivity type functioning as a base is embedded in a polycrystal through a dielectric film, and has a pair of main surfaces, one of which has a polycrystalline region. ,
In addition, at least a single crystal island and a dielectric film are exposed on the other main surface, and the cross-sectional area of the single crystal island parallel to the main surface gradually decreases from the main surface to the bottom surface. In a semiconductor device in which a first opposite conductivity type semiconductor region functioning as an emitter and a second opposite conductivity type semiconductor region functioning as a collector are provided so as to be exposed on the other main surface, one conductivity type having a carrier reflection function A high concentration semiconductor region of the type is provided between the single crystal island and the dielectric film so as to be exposed on the other main surface, and a semiconductor region of the first opposite conductivity type to the high concentration semiconductor region is provided between the single crystal island and the dielectric film so as to be exposed on the other main surface. A passivation in which the distance is selected to be shorter than the distance from the second opposite conductivity type semiconductor region to the high concentration semiconductor region, and a part of the extraction electrode of at least one of the opposite conductivity type semiconductor regions is formed on the main surface of the other semiconductor region. The passivation film extends over the high concentration semiconductor region through the passivation film, and the thickness of the passivation film below one extraction electrode is made larger on the high concentration semiconductor region side than on the opposite conductivity type semiconductor region side with which one extraction electrode is in contact. What is claimed is: 1. A lateral type semiconductor device, further comprising a stepped portion between both regions. 2. The lateral type semiconductor device according to item 1, wherein the depth of the first opposite conductivity type semiconductor region is smaller than the depth of the second opposite conductivity type semiconductor region. 3. The polycrystalline high concentration semiconductor region under the first opposite conductivity type semiconductor region protrudes into the single crystal island compared to the polycrystalline region and the high concentration semiconductor region under the second opposite conductivity type semiconductor region. 3. The lateral type semiconductor device according to claim 1 or 2, characterized in that: