JPH02308540A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a low resistance region without using an epitaxial method by a method wherein parallel trenches are formed in the main surface of a substrate with a proper distance and the insides of the trenches are enlarged into a cavity-shapes and diffused layers having a higher concentration than the substrate are formed on the inside surfaces of the cavities and the cavity parts are filled with semiconductor material. CONSTITUTION:Parallel trenches 201 are formed in the main surface of an n-type substrate 101 with a proper distance and the inner surfaces of the trenches 201 are etched with alkali anisotropic etchant to form cavities 202. High concentration n-type impurity is deposited on the inner surfaces of the cavities 202 and driven-in in oxidizing atmosphere to form n<+>-type low resistance regions 103 and insulating films 104 composed of SiO2 films and an island region 102. The cavities 202 are filled with polycrystalline Si or amorphous Si and the surface is levelled and a surface insulating film 109 composed of SiO2 is formed by oxidation. With this constitution, the low resistance regions 103 for reducing a collector resistance can be formed on the bottom of the island region 102 which is isolated with dielectric without using an epitaxial method.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device having a low resistance buried region.

(Prior Art) As a conventional semiconductor device having a low-resistance buried region, there is, for example, the one shown in FIG. 4 (edited by Minoru Nagata, [Ultrahigh-speed Bipolar Devices], Baifukan, p. 8, 1986. 11.
, 1.5). In the figure, 1 is a p-type substrate, an n4 buried layer 2 is formed on the p-type substrate 1 by diffusion, and an n4 buried layer 2 is formed on the p-type substrate 1 by diffusion.
A shaped epitaxial layer 3 is formed. A p + isolation region 4 is formed in the n-type epitaxial layer 3 so as to reach the p-type substrate 1 , and an n-type island region junction-isolated from the p-type substrate 1 is formed by the n-type epitaxial layer 3 . ing. In the n-type island region, a p-type base region 5, an n+ emitter region 6, and an n'' collector contact region 7 are formed with the n-type island region as a collector region, and a bipolar transistor is formed by mounting each of these regions. has been done.

The collector resistance of this bipolar transistor is reduced by the n'' buried layer 2.

(Problems to be Solved by the Invention) Conventionally, in order to form the n+ buried layer 2 under the collector region, an epitaxial growth method has been essential in the process. As a result, the number of steps increases and the cost of the board increases.
This led to an increase in chip costs.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device that can form a low resistance region in a semiconductor substrate without using epitaxial growth and can reduce chip cost.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention includes a first step of digging a plurality of parallel grooves at appropriate intervals in the main surface of a semiconductor substrate by etching. a second step of enlarging the inside of the groove into a hollow shape by etching; a third step of forming a diffusion layer with a higher impurity concentration than the semiconductor substrate on an inner surface of the hollow portion; and a fourth step of embedding a polycrystalline or amorphous semiconductor into.

(Operation) A plurality of parallel grooves are etched at appropriate intervals on the main surface of the semiconductor substrate, and the inside of each groove is expanded into a hollow shape by etching. Next, a highly impurity-concentrated diffusion layer serving as a low resistance region is formed on the inner surface of the cavity, and a polycrystalline or amorphous semiconductor is further buried in the cavity.

Thus, it becomes possible to form a low resistance region in a semiconductor substrate without using epitaxial growth.

(Example) Embodiments of the present invention will be described below based on the drawings.

FIG. 1 and FIG. 2 are diagrams showing one embodiment.

This embodiment is applied to a method of manufacturing a bipolar transistor.

First, the structure of a semiconductor device realized by the manufacturing method of this embodiment will be explained using FIG. FIG. 1(a) is a plan view, and FIG. 1(b) is a sectional view taken along the line A--A in FIG. 1(a).

In the figure, 101 is an n-type Si substrate as a semiconductor substrate, and an n-type island region 102 dielectrically isolated by an insulating film 104 made of a 5i02 film is formed on the n-type Si substrate 101. An 04" low resistance region 103 having a higher impurity concentration than the St substrate 101 is formed at the interface with the insulating film 104 in the region 102.n" low resistance region 103
reaches the surface of the Si substrate 101. A p-type base region 105, an n+ emitter region 106, and an n+ collector contact region 107 are formed in the n-type island region 102, using the n-type island region 102 as a collector region, and a bipolar transistor is formed by each of these regions. ing. 108 is a buried region made of polycrystalline St or amorphous St, and 109 is a surface insulating film.

The collector resistance of the bipolar transistor is reduced by the n'' low resistance region 103.

Next, a method for manufacturing the above-mentioned semiconductor device will be explained using FIG. In addition, in the following explanation, (a) to (d)
Each item symbol corresponds to (a) to (d) in FIG. 2, respectively.

(a) For example, (using a 1001-plane n-type St substrate 101, the planned island area on its main surface is S i02-3
A plurality of parallel grooves 201 are formed by reactive ion etching and masked with a multilayer insulating film of i3 N4-5 i02.
dig.

(b) Etch the inner surface of the groove 201 using an alkaline anisotropic etching solution such as hydrazine or ethylenediamine. When the exposed inner surface of the groove 201 on the fl 101 plane and the +1001 plane is etched with an alkaline anisotropic etching solution, the etch rate of the fl 101 plane and the (100) plane is significantly faster than that of the (1111 plane).
(Etching stops when the 1111 plane is exposed, and a cavity 202 with a rhombic cross section is formed in the groove 201.

(C) For example, by depositing an n-type impurity at a high concentration on the inner surface of the cavity 202 using POC (13, etc.) and driving it in in an oxidizing atmosphere, the n" low resistance region 1
Insulating film 10 consisting of 03 and 5i02 film for dielectric isolation
form 4. In this way, island regions 102 are formed.

(d) Fill the cavity 202 with polycrystalline St or amorphous St (an oxide film or an organic material such as PIQ may be used), flatten the surface, form a buried region 108, and further oxidize the surface to form a 5f02 A surface insulating film 109 is formed.

Thereafter, p-type base region 105, n1 is formed in island region 102 according to a normal bipolar transistor formation process.
An emitter region 106 and an n+ collector contact region are formed, and further wiring and surface protection processes are performed.

As described above, according to the method of manufacturing a semiconductor device of this embodiment, an n
A low resistance region 103 is formed.

In addition, in the above-mentioned embodiment, the island region 102 is an insulating film ]04
However, by omitting the formation of the insulating film 104 and using a p-type doped polycrystalline 81 for the buried region 108, and by setting the buried region 108 at a low potential, the pn
It is also possible to use junction separation.

Also, here, as shown in Fig. 2(a), an example was explained in which a groove is dug on the +1001 side, but instead of the +1001 side, fl
Needless to say, an i01-plane substrate may be used.

Next, FIG. 3 shows another embodiment of the present invention. This embodiment is applied to a method of manufacturing a MOSFET.

In this embodiment, a p4 low resistance region 1 is provided under the island region 102.
10 is formed, and p4 type doped polycrystalline Si or amorphous St is used for the buried region 111. A MOSFET is formed within the island region 102 by a p+ source region 112, a p+ drain region 113, a gate s-pole 114, and the like.

In this embodiment, the p+ low resistance region 110 and the p+ buried region 111 eliminate interactions due to minority carriers with other MOSFETs, etc., and improve characteristics such as withstand voltage. Also in this embodiment, the p" low resistance region 110 having the above-mentioned function can be formed without using the epitaxial growth method.

In each of the embodiments described above, anisotropic etching was used to form the cavity 202, but instead of this, isotropic etching may be used to form a cavity having a circular cross section.

[Effects of the Invention] As explained above, according to the present invention, a plurality of parallel grooves are dug at appropriate intervals in the main surface of a semiconductor substrate by etching, and each groove is expanded into a hollow shape by etching. Next, a diffusion layer with a higher impurity concentration than the semiconductor substrate was formed on the inner surface of this cavity, and a polycrystalline or amorphous semiconductor was filled in the cavity, thereby eliminating the need for epitaxial growth. There is an advantage that a low resistance region, for example for reducing collector resistance, can be formed in a semiconductor substrate, thereby reducing substrate cost and, therefore, reducing chip cost.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a semiconductor device manufactured by an embodiment of a semiconductor device manufacturing method according to the present invention, and FIG. 2 is a process diagram showing a semiconductor device manufacturing method according to an embodiment of the present invention. FIG. 3 is a vertical sectional view showing a semiconductor device manufactured according to another embodiment of the present invention, and FIG. 4 is a vertical sectional view showing a conventional semiconductor device. 101: n-type Si substrate (semiconductor substrate), 102: island region, 103.110; low resistance region (diffusion layer with higher impurity concentration than the semiconductor substrate), 108.111. Polycrystalline or amorphous semiconductor buried Inclusive area. Agent Patent Attorney Hidekazu Miyoshi P Figure 1 (a) 1f! ! (b) Figure 2 (a) Figure 2 (b) Figure 2 (C) Figure 2 (d) Figure 3

Claims (1)

[Claims] a first step of digging a plurality of parallel grooves at appropriate intervals in the main surface of a semiconductor substrate by etching; a second step of enlarging the inside of the groove into a hollow shape by etching; and an inner surface of the hollow portion. a third step of forming a diffusion layer with a higher impurity concentration than the semiconductor substrate; and a fourth step of filling the cavity with a polycrystalline or amorphous semiconductor. Method of manufacturing the device.