JPS6124245A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate any irregularly high series resistance between wirings and n<+> buried layers with the buried layers and contact highly concentrated layers overlapped one another by a method wherein diffusion openings to form contact highly concentrated impurity regions are provided from nearly central positions in an insulation separating region. CONSTITUTION:A dielectric separating substrate 10 is thermally oxidized to form a passivating oxide film 8. Firstly the positions of an emitter 9 and a collector 11 of a pnp transistor are made into openings by photoetching process and then boron is diffused in the openings to form respective functional regions. Secondly the other openings 16 for diffusion are formed to provide n<+> contact regions 12 coming into ohmic contact with n<+> buried layers 4 to be an n base and a cross- under wiring 18. The buried layers 4 and the contact regions 12 shall be overlapped one another no minimize the series resistance between them within the openings 16. In order to attain to this purpose, the diffusion openings 16 may be formed within the range from the minimum to the maximum dispersion of the exposed positions of buried layers 4.

Description

[Detailed Description of the Invention] [Original Field of the Invention] The present invention relates to a highly integrated semiconductor device, and particularly relates to a plurality of single crystal silicon devices supported on a polycrystalline silicon support via a dielectric isolation insulating film. This invention relates to a high voltage semiconductor device using a dielectric isolation substrate having regions (islands).

[Background of the invention]

BACKGROUND OF THE INVENTION As semiconductor technology advances, development of high voltage ICs that integrate high voltage circuits that were conventionally composed of individual elements is becoming more active. Dielectric isolation technology is suitable for insulation isolation between elements of such a high voltage semiconductor device. Although dielectric isolation is more complicated to manufacture than pn junction isolation, it has the advantage of being able to reduce parasitic effects to a level that does not interfere with the circuit.

The prior art will be explained with reference to FIG. Generally dielectric isolation substrate
A buried layer 4 having a high impurity concentration is formed on the monocrystalline silicon island 7 in contact with the dielectric film 5. The main purpose of the buried layer 4 is to prevent the occurrence of tear channels due to electric field effects and to improve the characteristics of the functional element. In order to conduct the buried layer 4 with the outside, all holes are provided in a part of the buried layer 4, and a high concentration impurity region 12 is provided to obtain an ohmic contact.

The dielectric isolation substrate 10 is manufactured by mechanical processing such as grinding and polishing, but the amount of polishing varies depending on the processing precision, and the thickness of the single crystal silicon island 7 varies. Therefore, the dielectric isolation substrate 10t
- The position of the buried layer 4 formed in the manufacturing process at which it is exposed on the main surface is undefined. The formation position of the diffusion hole to be provided in the high impurity concentration region 12' for ohmic contact in embedding #4 is determined by assuming the amount of polishing and misalignment during photoetching, but if the hole does not match on the embedding layer 4. There is.

As shown in FIG. 3, a buried layer 4 and a high impurity concentration region 1
If 2 is separated, a series resistance will be present, and the characteristics of the device will be significantly degraded. In addition, because the separation distance varies depending on the processing accuracy and is not constant, there is a problem that the characteristics vary widely.

[Purpose of the invention]

The purpose of the present invention is to more effectively exhibit the effect of a buried layer provided in contact with a dielectric film for insulation isolation.
It is an object of the present invention to provide a semiconductor device having good characteristics with a small variation width.

[Summary of the invention]

In the present invention, by providing a diffusion hole for forming a high concentration impurity region for contact from approximately the center of the insulation isolation region (separation trench), it is ensured that it overlaps with the high concentration impurity region and the buried +11. Features.

[Embodiments of the invention]

FIG. 4 is a schematic diagram of a method for manufacturing a dielectric isolation substrate for explaining the present invention in detail. As shown in FIG. 5A, n-type single crystal silicon is oxidized to form an oxide film 2 on the surface. Next, as shown in Φ), the oxide film 2 is partially opened by photoetching, and the remaining oxide film is used as a protective mask and etched with an alkaline etchant to form a V-shaped separation groove 3.

Next, the oxide film 2 is removed, and an n+ buried layer 4 is formed by diffusion or ion implantation as shown in (C).

Thereafter, an oxide film 5 for dielectric isolation is formed by oxidation. Furthermore, as shown in (d), polycrystalline silicon 6 serving as a support is formed thereon. Next, as shown in (e), the polycrystalline silicon 6 is ground 6A to make the substrate parallel.
Single crystal silicon l' is ground by IA. Finally, by mirror polishing IC, one single crystal silicon island 7 is formed into another single crystal silicon island 7 via oxide film 5 and polycrystalline silicon 6'f.
Separate from. In this way, the dielectric isolation substrate IO is completed. However, the amount of polishing differs between wafers and lots depending on the processing accuracy during polishing, resulting in variations in the dimensions of the portion exposed on the main surface. Insulation separation width W is 1 to 40μ
It varies within a range of m. Therefore, the exposed position on the main surface of the n+ buried layer 4 provided in contact with the isolation dielectric film 5 also changes and becomes unstable.

In a later process, a high concentration impurity region 12 will be formed to make contact with this n1 buried layer 4, but at this time, the sub-regions must be configured so that they overlap regardless of the exposed position of the n0 buried layer 4. No.

FIG. 1 shows an embodiment of the invention. Functional elements are formed on each single crystal silicon island 7 of the completed dielectric isolation substrate 10. Although the buried layer 4 is used as a part of each functional element, an example of a PNP transistor 17 and a cross-under wiring IF 5 will be described here. First, the dielectric isolation substrate lOt is thermally oxidized to form the oxide film 8 for bombardment. Next, holes are formed by photoetching at the positions of the emitter 9 and collector 11 of the transistor (I), III), and boron is diffused to form the respective functional regions. Next, a diffusion hole 16 is formed to provide an n+ region 12 for contact in order to make ohmic contact with the n+ buried layer 4 which will become the cross-under wiring 18 with the n base. The opening 16 is
In order to reduce the series resistance between the n+ buried layer 4 and the contact n+ region 12, both regions must overlap. To this end, the diffusion holes 16 may be formed over the minimum to maximum variation in the exposed position of the n1 buried layer 4.

The minimum dimension of the variation width from the separation groove center 15 is about 2 μm, which is the thickness of the oxide film 5, and the maximum is about 20 μm, which is the maximum of the polishing scattering. Therefore, the holes 16 are from 2 μm to 20 μm with n+ filling/i! It is formed over a length of 30 μm, which is the sum of the diffusion width of 4 and about 10 μm. If you do this, the dielectric isolation substrate lO
Regardless of variations in machining accuracy, the position of the hole 16 is always n
+Constructed on the embedded layer 4. Thereafter, phosphorus is diffused into the hole 16 to form a contact n0 region 12t. next,
30 μm' in the contact window 14 from which the electrode wiring 13 is taken out.
(A hole is opened toward the center 15 of the isolation trench at the c-base point, and a wiring 13 made of At or the like is formed. In this way, a semiconductor device to which the present invention is applied is obtained. According to the present invention, a semiconductor device to which the present invention is applied is obtained.
In transistors, the current amplification factor increases because the n-base resistance becomes smaller, and the improvement was particularly significant in the large current region. Furthermore, a transistor with small variation in characteristics was obtained. The cross-under wiring had a resistance value that did not cause any problems on the circuit, and a uniform resistance value was efficiently obtained.

FIG. 2 shows another embodiment of the invention. An n1 buried layer 4 is provided on a plurality of adjacent single crystal silicon islands 7, 7',
This is an example in which an n4 region 12Th for contact is formed on both of them. The diffusion hole 16 is located in the contact n0 region 12t- of the adjacent single crystal silicon island 7°7'.
It is formed across the positions where it is provided. Thereafter, phosphorus is diffused to form the n1 region 12. Since the contact n4 regions 12 of the single crystal silicon islands 7 and 7' are insulated and separated from each other by the isolation oxide film 5, there is no conduction. Therefore,
Depending on the processing accuracy of the dielectric isolation substrate 10, the N4 buried layer 4
Even if the exposed positions of the contacts vary, the contact n3 regions 12 will always overlap. In this embodiment, two adjacent single-crystal silicon islands 7 have been described, but the present invention is not limited to this, and the present invention can be implemented using a plurality of islands 12 and at a plurality of locations.

In the above embodiments, the description has been limited to the case where the contact n+ region 12t- is provided in the n1 buried layer 4, but the present invention also provides the main structure of the single crystal silicon island 7 in contact with or near the isolation oxide film 5. It can also be applied as a method of providing openings in the diffusion region formed from the surface. It can also be applied as a method for forming holes for contacts leading to external wiring.

In the figure, 3 is an isolation trench, 6 is polycrystalline silicon, and 11 is P.
is a collector.

〔Effect of the invention〕

According to the present invention, since the buried 4 layers and the contact high concentration layer overlap, irregular high series resistance between the wiring and the n+ buried layer and the 47- layer is eliminated. As a result, the width of variation in the characteristics of the functional elements is reduced, and the characteristic values are also improved. This eliminates the need to design circuits that take into account variations.
Device performance will be improved and higher integration will be achieved.

[Brief explanation of drawings]

Fig. 1 is a diagram showing one embodiment of the present invention, Fig. 2 is a diagram showing another embodiment of the present invention, Fig. 3 is a schematic diagram for explaining the entire prior art, and Fig. 4 is a diagram showing the embodiment of the present invention. It is a diagram showing a manufacturing method of a current visitor separation substrate for explanation. l...N-type single crystal silicon, 3... Isolation groove, 4...
- n1 buried layer, 5... oxide film for isolation, 6... polycrystalline silicon, 7... single crystal silicon island, lO... dielectric isolation substrate, 12... n0 region for contact, 13
...At arrangement, 15...Center of separation groove, 16...Diffusion opening, 17...PNP transistor, 18...
Cross under distribution 1m 11 /if Zm

Claims (1)

[Claims] 1. A pair of substantially parallel main surfaces, a single crystal silicon island, a dielectric film for insulation isolation, and polycrystalline silicon are exposed on one of the main surfaces; The polycrystalline silicon is covered with a passivation film, the polycrystalline silicon is exposed on the other main surface, and each of the single-crystalline silicon islands is embedded in the polycrystalline silicon via the dielectric film for isolation, and the single-crystalline silicon is In a semiconductor device configured such that a functional element is formed on a crystalline silicon island, and wiring of the functional element is drawn out from the one main surface and extends on the main surface via the passivation film, A buried region of high concentration impurity is formed inside the single crystal silicon island in contact with the dielectric film for isolation, and the buried region is exposed on the one main surface, and wiring is routed from this exposed portion. A semiconductor device characterized in that a diffusion hole forming a high concentration impurity region for a contact to be drawn out is provided from approximately the center of the insulation isolation region exposed on the one main surface toward the single crystal silicon island. 2. The semiconductor device according to claim 1, wherein the diffusion hole is provided across the one main surface between the adjacent single crystal silicon islands.