JPH10173040A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a low-heat resistance transistor structure. SOLUTION: An SOI substrate 1 has an SOI layer insulation film 3 and semiconductor layer 4 on a semiconductor substrate 2. The semiconductor layer 4 has Si islands 7 surrounded by a U-grooved isolation 5. First element-separated transistors T1 , T2 are formed on the Si islands 7, and second transistors T3 , T4 not separated by the U-grooved isolation 5 are formed on the semiconductor layer 4. The collector is common to the transistors T3 and T4 on the semiconductor layer 4. The collectors of the first transistors T1 , T2 use the Si islands 7, making the collector potential variable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to an SOI (Silicon) device.
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device using a substrate and performing U-groove structure isolation.

[0002]

2. Description of the Related Art In recent years, demands for high-speed response, high integration, and the like for semiconductor integrated circuit devices have been increasing, reflecting the sophistication of applied equipment using the semiconductor integrated circuit devices.

In order to realize a high-speed response of a semiconductor integrated circuit device, it is necessary to reduce the capacitance of elements. As one of the measures, an SOI technique for forming a single-crystal silicon layer on an insulator has attracted attention. ing. For example, SOI technology is published on November 30, 1984 by Ohm Co., Ltd.
As described in “LSI Handbook”, pp. 387-390, a single-crystal silicon layer is formed on an insulator substrate or an insulator layer formed on a semiconductor substrate, and this single-crystal silicon layer is used as an active region. A device such as a transistor is formed by utilizing such a device, and is known as one of ideal device isolation technologies capable of realizing a low device capacitance.

A technique for realizing high integration of a semiconductor integrated circuit device is disclosed in, for example, November 15, 1985.
As described in “Ultra High-Speed Bipolar Device”, published by Baifukan Co., Ltd., p89, an element isolation technique using U-groove isolation can be used. The element isolation technique by U-groove isolation is a technique of forming a deep groove (U-groove) in an element isolation region and forming trench isolation in which a dielectric or the like is filled.
Compared to OS (Local Oxidation of Silicon) isolation, there is no bird's beak, so that the element isolation region can be reduced, and since there is no bird's head, flatness can be improved. Further, since an impurity region for preventing inversion at the interface with the LOCOS oxide film is not required, the isolation capacitance is reduced, and
The wiring capacitance can be reduced by shortening the wiring length with the increase in integration density, and the speed of the semiconductor integrated circuit device can be increased.

The above-described SOI technology and U-groove isolation technology can be used not only independently but also in combination to further increase the speed and integration of the semiconductor integrated circuit device. It is expected.

[0006]

However, the present inventors have recognized that a semiconductor integrated circuit device using the above-described SOI technology and U-groove isolation technology has the following problems. did.

That is, when a semiconductor integrated circuit device is manufactured by using the SOI technology and the U-groove isolation technology, the semiconductor layer on which the transistor constituting the semiconductor integrated circuit device is formed has an insulating film formed by the SOI technology at the bottom. In addition, the side surface is surrounded by an insulator by U-groove isolation technology. Here, the insulating film and the insulator can be generally exemplified by silicon oxide.

An insulator such as silicon oxide generally has a low thermal conductivity and a high thermal resistance. Therefore, when a transistor is surrounded by an insulator, heat generated from the transistor is accumulated in a semiconductor layer surrounded by the insulator. As a result, the temperature at the junction of the transistor increases. To prevent this, lower the thermal resistance of the package, etc., or lower the outside air temperature, and quickly discharge the accumulated heat to the outside, or reduce the heat generation per unit volume of the board. In order to suppress this, it is necessary to reduce the integration density of transistors.

However, there is a limit to the improvement of the package material and the enhancement of the heat radiating device for lowering the outside air temperature.
Further, a decrease in the integration density of the transistors causes a problem of increasing the chip area.

An object of the present invention is to provide a semiconductor integrated circuit device having a transistor structure with low thermal resistance.

Another object of the present invention is to provide a semiconductor integrated circuit device capable of suppressing a temperature rise at a junction of a transistor.

Still another object of the present invention is to provide a semiconductor integrated circuit device in which transistors can be arranged at high density without particularly requiring a heat radiating device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device according to the present invention comprises an upper surface of an insulator layer on a semiconductor substrate, or a semiconductor layer formed on an upper surface of the insulator substrate, and a plurality of transistor elements formed on the semiconductor layer. A first transistor forming region in which the transistor elements are separated from each other by an element separation structure for electrically separating the transistor elements, and a semiconductor integrated circuit device having no element separation structure between the transistor elements. And two transistor formation regions.

According to such a semiconductor integrated circuit device,
Since the first transistor formation region in which the transistor elements are separated from each other by the element isolation structure and the second transistor formation region having no element isolation structure between the transistor elements, the first transistor formation region is formed in the second transistor formation region. The generated heat from the transistor can be quickly exhausted through the semiconductor layer, and as a result, a rise in the temperature of the semiconductor layer can be suppressed and a rise in the junction temperature can be prevented.

(2) The semiconductor integrated circuit device of the present invention is the semiconductor integrated circuit device according to the above (1), wherein the transistor element has an emitter formed in the semiconductor layer and a base formed so as to surround the emitter. And a collector surrounding the base and a collector including a semiconductor layer as a part thereof. The collector of the bipolar transistor element in the second transistor formation region is shared by the bipolar transistor element in the second transistor formation region. , And the same potential as the substrate potential.

According to such a semiconductor integrated circuit device,
Since the collector of the bipolar transistor element in the second transistor formation region is shared by each element in the second transistor formation region and has the same potential as the substrate potential, the collector between the transistors formed in the second transistor formation region Need not be electrically separated. That is,
In such a semiconductor integrated circuit device, it is possible to suppress an increase in the temperature at the junction of the transistor without affecting the element isolation performance between the transistor elements. The substrate potential may be, for example, a ground potential.

(3) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1) or (2), wherein the transistor in the second transistor formation region is the same as the transistor in the first transistor formation region. It is used for a circuit in which a collector current larger than a transistor flows.

According to such a semiconductor integrated circuit device,
Since the transistor in the second transistor formation region is used for a circuit in which a larger collector current flows than the transistor in the first transistor formation region, the amount of heat accumulated in the semiconductor layer can be reduced overall.

That is, a transistor through which a large collector current flows, that is, a transistor having a large amount of heat generation, is arranged in a second transistor formation region having an excellent heat dissipation effect.
Transistors having different collector potentials are arranged in a first transistor formation region in which an element isolation region is formed, and are adjusted so that heat generated from the transistors and heat discharged to a substrate are most effectively balanced.

Therefore, without deteriorating the performance of the semiconductor integrated circuit device, it is possible to optimize the amount of heat accumulated in the semiconductor layer so as to minimize the amount of heat, thereby suppressing a rise in temperature at the junction.

(4) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1) to (3),
The element isolation region is an element isolation region having a U-groove structure.

According to such a semiconductor integrated circuit device,
Since the element isolation region is an element isolation region having a U-groove structure, the area occupied by the element isolation region can be reduced, and the degree of integration of the semiconductor integrated circuit device can be improved.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 shows an example of a semiconductor integrated circuit device having a bipolar transistor according to an embodiment of the present invention. FIG. 1A is a top view showing a layout of the bipolar transistor, and FIG. FIG. 2 is a sectional view taken along line bb in FIG. Although FIG. 1A is not a cross-sectional view, each member is hatched for easy understanding of the drawing. Some members are omitted or shown by dotted lines. Further, the connection of the differential buffer circuit shown in FIG. 2 is schematically shown.

The semiconductor integrated circuit device according to the present embodiment
It includes an OI substrate 1 and a bipolar transistor formed on the SOI substrate 1.

The SOI substrate 1 includes a semiconductor substrate 2, an SOI insulating film 3 formed on the semiconductor substrate 2, and a semiconductor layer 4 formed on the SOI insulating film 3. As the semiconductor substrate 2, a single crystal silicon wafer can be used,
The SOI insulating film 3 can be exemplified by, for example, a silicon oxide film. Further, the semiconductor layer 4 can be, for example, a single crystal silicon thin film grown epitaxially.

The method for manufacturing the SOI substrate 1 is a known SIM method.
OX (Separation by Implanted Oxygen) method, FIPOS
(Full Isolation by Porous Oxidized Silicon) method, deposited film recrystallization method in which amorphous silicon or single crystal silicon thin film is recrystallized by energy such as heat, or epitaxial method in which an epitaxial film is deposited on a spinel structure on a silicon substrate An example is a deposition method. In this embodiment, an SOI substrate is exemplified, but an SOS (Silicon On Sapphire) substrate in which a single crystal silicon film is deposited on sapphire may be used. Further, the semiconductor substrate 2 is used as an insulator, and the semiconductor substrate 2 and S
The OI insulating film 3 may be an integrated insulator.

A U-groove isolation 5 for element isolation is formed in the semiconductor layer 4, and a field insulating film 6 is formed on the main surface of the semiconductor layer 4.

The U-groove isolation 5 is formed by filling a U-shaped groove structure formed in the semiconductor layer 4 with, for example, silicon oxide. The island 7 is formed. The silicon island 7 is made of SO
Since the transistor is completely separated by the I insulating film 3 and the U-groove isolation 5, the floating capacitance of the transistor formed on the silicon island 7 is reduced, and the operation speed of the semiconductor integrated circuit device is improved. Can be.

In this embodiment, the case where the field insulating film 6 is formed is exemplified. However, the field insulating film 6 is formed mainly for stabilizing the silicon surface during the element forming process. It is not formed for element isolation. Therefore, the field insulating film 6
Is not an essential member, and may be a semiconductor integrated circuit device not using this.

The transistors formed on the SOI substrate 1 include first transistors T ₁ and T ₂ surrounded by a U-groove isolation 5 and formed on a silicon island 7 (first transistor formation region). , And second transistors T ₃ and T ₄ formed on the semiconductor layer 4 (second transistor formation region) not surrounded by the U-groove isolation 5.

The first transistors T ₁ and T ₂ include a base region 8 formed near the main surface of the silicon island 7,
It comprises an emitter region 9 surrounded by a base region 8 and a collector region which is a silicon island 7. In the present embodiment, in order to exemplify an npn-type transistor, a silicon region 7 and an emitter region 9 which are collector regions are doped with an impurity having an n-type conductivity, such as phosphorus or arsenic, and a base region 8 is doped with impurities. Impurities having a p-type conductivity, for example, boron are doped.

The second transistors T ₃ and T ₄ include a base region 10 formed near the main surface of the semiconductor layer 4, an emitter region 11 surrounded by the base region 10, and a collector region as the semiconductor layer 4. Consists of Like the transistors T ₁ and T ₂ , the semiconductor layer 4 and the emitter region 11, which are the collector regions, are doped with an n-type impurity such as phosphorus or arsenic, and the base region 10 is doped with the p-type conductivity. , For example, boron.

Since the second transistors T ₃ and T ₄ are not surrounded by the U-groove isolation 5, the transistors T ₃ and T _4
3, even if the transistor T _3, T ₄ is heated by current flowing through the T _4, heat conducting semiconductor layer 4 will not be blocked by the U groove isolation 5. Therefore, the semiconductor layer 4
Of the transistors T ₃ and T ₄ can be suppressed.

The first and second transistors T ₁ ,
T ₂ , T ₃ , and T ₄ are covered with the insulating film 12,
Above, a wiring 13 connected to the emitter, base and collector of each transistor is formed.

The insulating film 12 can be, for example, a silicon oxide film formed by a CVD method.
As 3, a metal thin film mainly composed of aluminum formed by a sputtering method or the like can be exemplified. Silicon or copper or the like can be added to the aluminum. In addition, the wiring 13 can be low-resistance polycrystalline silicon, metal silicide, or a stacked film thereof.

Next, the differential buffer circuit shown in FIG. 2 will be described.

FIG. 2 is a circuit diagram showing an example of the semiconductor integrated circuit device shown in FIG. 1, and is a circuit diagram showing an example of a differential buffer circuit.

The differential input stage of the differential buffer is composed of _first transistors T ₁ and T ₂ surrounded by a U-groove isolation 5, and has an emitter for driving a buffer subsequent to the differential buffer. The follower transistor is composed of second transistors T ₃ and T ₄ formed on the semiconductor layer 4 not surrounded by the U-groove isolation 5.

The collector of the first transistor T ₁ is connected to the ground potential via the resistance element R ₁ and is connected to the base of the second transistor T ₃ . The collector of the first transistor T ₂ are, via a resistor R ₂ is connected to the ground potential, is connected to the base of the second transistor T _4. The emitters of the first transistors T ₁ and T ₂ are both connected to the potential V _EE via the constant current source circuit 14, and the base of the first transistor T ₁ is connected to an input IN which is one of the differential inputs. the base of the first transistor T ₂ are connected to the input bar iN is another one of the differential inputs.

The emitter of the second transistor T ₃ is connected to the potential V _EE via the constant current source circuit 14 and to the output bar OUT, which is one of the differential outputs. Also, the second
The emitter of the transistor T ₄ is connected to the potential V _EE through a constant current source circuit 14 is connected to the output OUT, which is another one of the differential output. Further, the collectors of the second transistors T ₃ and T ₄ are both connected to the ground potential.
Therefore, the collectors of the second transistors T ₃ and T ₄ are always at the same potential.

Here, the first transistors T ₁ and T ₂ , which are the transistors of the differential input stage, have a small area to reduce the input load, and the second transistors T ₃ and T ₄ which are the emitter follower transistors Uses a large-area transistor to drive the next buffer. Therefore, the current of the constant current source is such that the current I ₂ (= I ₃ ) flowing through the second transistors T ₃ and T ₄ is 1.5 to 2 times the current I ₁ flowing through the first transistors T ₁ and T _2. Used as a degree. In addition, the first transistors T ₁ and T ₂ , which are transistors of the differential input stage, must use a structure separated by the U-groove isolation 5 because the collector potential changes. Certain second transistors T ₃ and T ₄ can have a structure that does not use the U-groove isolation 5 because the collector potential is the same as the substrate potential.

Next, a method of manufacturing the semiconductor integrated circuit device will be described with reference to FIGS.

FIG. 3 to FIG. 6 are cross-sectional views of essential parts showing one example of a method of manufacturing the semiconductor integrated circuit device of the present embodiment.

First, a semiconductor substrate 2 made of single crystal silicon is prepared, and oxygen ions are implanted from the main surface direction of the semiconductor substrate 2 by an ion implantation method (FIG. 3). At this time, the implantation energy of oxygen ions is increased so that oxygen does not exist on the main surface of the semiconductor substrate 2. As a result, only the silicon exists on the surface of the semiconductor substrate, and the SOI insulating film 3 is formed at a position slightly deeper than the surface.

Next, a semiconductor layer 4 is formed by epitaxially growing a single-crystal silicon film on silicon on the surface of the semiconductor substrate 2 to form the SOI substrate 1 (FIG. 4). By thus epitaxially growing a single crystal silicon film, a single crystal silicon film with few defects and impurities can be obtained. Further, since the semiconductor layer 4 is doped with an impurity for converting the semiconductor layer 4 into an n-type conductivity type, for example, phosphorus, phosphorus can be ion-implanted into the entire surface of the semiconductor layer 4. May go. Note that in this embodiment, SO
The SIMOX method is exemplified as a method for manufacturing the I-substrate 1.
It may be manufactured by another method, for example, a FIPOS method, a deposited film recrystallization method, or the like.

Next, a groove structure is formed in the semiconductor layer 4, and thereafter, a silicon oxide film is deposited by, eg, CVD to fill the groove structure, and the silicon oxide film is etched back to form a U-groove isolation 5. (FIG. 5). A known etching method can be used for the etch back in forming the groove structure.

Next, field insulating film 6 is formed by, for example, LOCOS, and base regions 8, 10 are formed by, for example, boron ion implantation. Thereafter, emitter regions 9 and 11 are formed in a part of base regions 8 and 10 by, for example, phosphorus ion implantation (FIG. 6). In order to implant ions into a specific region, a photoresist is patterned using a known photolithography technique, and this can be used as a mask.

Next, after a part of the wiring 13 connected to the base regions 8 and 10 is formed on the field insulating film 6, the insulating film 12 is deposited. Further, a contact hole is formed in the insulating film 12, an aluminum thin film is deposited on the entire surface of the SOI substrate 1 by a sputtering method, and the aluminum thin film is patterned to form a wiring 13. Thus, the semiconductor integrated circuit device shown in FIG. 1 is almost completed.

According to the semiconductor integrated circuit device of the present embodiment, the first transistors T ₁ and T ₂ are formed on the silicon island 7 surrounded by the U-groove isolation 5,
Transistors T ₃ and T ₄ are formed on the semiconductor layer 4 not surrounded by the U-groove isolation 5, so that the temperature rise of the semiconductor layer 4 and the silicon island 7 due to the transistor is suppressed, and the temperature rise at the junction of the transistor is suppressed. Can be prevented.

That is, conventionally, all transistors are U
It has a structure in which the elements are separated by the groove isolation 5, that is, a structure similar to the _first transistors T ₁ and T ₂ in the present embodiment. For this reason, the heat generated by the transistor diffuses from the transistor through the semiconductor substrate 2. For example, when the transistor is surrounded by an insulating film such as a silicon oxide film, the thermal conductivity of the silicon oxide film is 0.0033. ~ 0.004 [cal · cm ^-1 · s ^-1 · ° C ^-1 ]
Therefore, the thermal resistance between the transistor and the semiconductor substrate 2 was large. However, in the semiconductor integrated circuit device of the present embodiment, the second transistors T ₃ and T ₄ are not separated, and the semiconductor layer 4 is shared as a collector region. Silicon has a thermal conductivity of 0.2 to 0.35 [cal · cm ^-1]
・ S ^-1 · ℃ ^-1 ], which is larger than silicon oxide film.
The heat conduction of the semiconductor layer 4 is promoted, and the SOI substrate 1
In the plane direction, the thermal resistance becomes smaller. This allows
It is possible to suppress the temperature rise of the junction portion of the first and second transistors _{T 1, T 2, T 3} , T 4 to prevent heat accumulation of the SOI substrate 1.

The collectors of the second transistors T ₃ and T ₄ are shared and form the semiconductor layer 4, so that the second transistors T ₃ and T ₄ are directly supplied not only from the extraction electrodes of the transistors but also from the substrate potential. Become. Therefore, the potential stability of the transistor is improved.

Further, in the semiconductor integrated circuit device according to the present embodiment, the first transistors T ₁ and T ₂ , which are transistors of the differential input stage, have a small area in order to reduce the input load.
Since the second transistors T ₃ and T ₄ , which are emitter follower transistors, have a large area to drive the buffer of the next stage, a large current flows through the second transistors T ₃ and T _4, and a large current flows around the second transistors T ₃ and T _4. In this embodiment, since the second transistors T ₃ and T ₄ have a structure that does not use the U-groove isolation 5, heat generated by a large collector current can be quickly discharged. it can. On the other hand, since the first transistors T ₁ and T ₂ have a structure having the U-groove isolation 5, heat is not quickly discharged, but the collector current is small, so that the problem of heat generation is not remarkable. As described above, in the differential input buffer according to the present embodiment, the transistor in which heat generation is a problem has the U-groove isolation 5 in which the heat is quickly discharged. Since the fluctuating transistor is isolated by the U-groove isolation 5, the performance of the semiconductor integrated circuit device is not impaired, the rise in the substrate temperature can be suppressed, and the problem of the rise in the temperature at the junction of the transistor can be dealt with.

The collector potential of the second transistors T ₃ and T ₄ , which are emitter follower transistors, is the same as the substrate potential, so that the transistors can have low thermal resistance and good collector potential stability.

With these effects, the junction temperature of the transistor can be reduced, and the transistors, which are heat generating sources, can be arranged at a high density.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in this embodiment, a semiconductor integrated circuit device having an SOS structure has been described as an example, but a semiconductor integrated circuit device having an SOS structure may be used.

In this embodiment, the example of the differential input buffer has been described. However, the present invention may be applied to other amplifier circuits, logic circuits, memory circuits, and the like.

[0061]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) A semiconductor integrated circuit device having a transistor structure with low thermal resistance can be provided.

(2) It is possible to provide a semiconductor integrated circuit device capable of suppressing a rise in temperature at a junction of a transistor.

(3) It is possible to provide a semiconductor integrated circuit device in which transistors can be arranged at high density without particularly requiring a heat dissipation device.

[Brief description of the drawings]

FIG. 1 illustrates an example of a semiconductor integrated circuit device having a bipolar transistor according to an embodiment of the present invention.
1A is a top view showing a layout of a bipolar transistor, and FIG. 1B is a cross-sectional view taken along line bb in FIG. 1A.

FIG. 2 is a circuit diagram illustrating an example of the semiconductor integrated circuit device illustrated in FIG. 1, and is a circuit diagram illustrating an example of a differential buffer circuit.

FIG. 3 is a fragmentary cross-sectional view showing one example of the method for manufacturing the semiconductor integrated circuit device of the present embodiment;

FIG. 4 is an essential part cross sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the present embodiment.

FIG. 5 is an essential part cross sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the present embodiment.

FIG. 6 is an essential part cross sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of the present embodiment.

[Explanation of symbols]

Reference Signs List 1 SOI substrate 2 Semiconductor substrate 3 SOI insulating film 4 Semiconductor layer 5 U-groove isolation 6 Field insulating film 7 Silicon island 8 Base region 9 Emitter region 10 Base region 11 Emitter region 12 Insulating film 13 Wiring 14 Constant current source circuit I ₁ Current I ₂ current I ₃ current IN input IN IN OUT OUT output OUT OUT R ₁ resistance element R ₂ resistance element T ₁ first transistor T ₂ first transistor T ₃ second transistor T ₄ second transistor V _EE potential

Claims (4)

[Claims] 1. A semiconductor integrated circuit device having an upper surface of an insulator layer on a semiconductor substrate, or a semiconductor layer formed on an upper surface of the insulator substrate, and a plurality of transistor elements formed on the semiconductor layer. A first transistor formation region in which the transistor elements are separated from each other by an element separation structure for electrically separating the transistor elements, and a second transistor formation region having no element separation structure between the transistor elements. A semiconductor integrated circuit device comprising: 2. The semiconductor integrated circuit device according to claim 1, wherein the transistor element surrounds the emitter formed in the semiconductor layer, a base formed to surround the emitter, and the base. A bipolar transistor element comprising a collector having the semiconductor layer as a part thereof, wherein the collector of the bipolar transistor element in the second transistor formation region is shared by the bipolar transistor element in the second transistor formation region A semiconductor integrated circuit device having the same potential as the substrate potential. 3. The semiconductor integrated circuit device according to claim 1, wherein the transistor in the second transistor formation region is used for a circuit in which a larger collector current flows than the transistor in the first transistor formation region. A semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein said element isolation region is an element isolation region having a U-groove structure.