JPS61265867A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61265867A JPS61265867A JP10861085A JP10861085A JPS61265867A JP S61265867 A JPS61265867 A JP S61265867A JP 10861085 A JP10861085 A JP 10861085A JP 10861085 A JP10861085 A JP 10861085A JP S61265867 A JPS61265867 A JP S61265867A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- layer
- collector
- collector electrode
- buried layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 abstract description 12
- 239000010937 tungsten Substances 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002655 kraft paper Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特にコレクタ直列抵抗が
低くコレクタ占有面積の小さい／（イボーラ型トランジ
スタを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an Ibora type transistor with low collector series resistance and a small collector occupied area.
従来、バイポーラ型トランジスタを有する半導体集積回
路装置は例えば第３図に示すように、半導体基板表面に
厚い絶縁分離酸化膜１１で周囲を囲まれた領域があシ、
この領域下の半導体基板内部ＫＪｍ込層１２がある。埋
込層１２上にエピタキシャル層１３があ夛、エピタキシ
ャル層１３表面は半導体基板表面をなしている。エピタ
キシャル層１３内部に含まれその表面高さが半導体基板
表面と同じ高さのベース層１４がある。ペース層１４内
部に含まれその表面高さが半導体基板表面とそれぞれ同
じ高さのグラフト・ベース層１４′とエミツタ層１５が
ある。グラフト・ベース層１４′はＰ型多結晶シリコン
１８を介してベース電極２２に電気的に接続され、エミ
ツタ層１５はＮ型多結晶シリコン１７を介してエミッタ
電極２１に電気的に接続されている。コレクタ電極下の
エピタキシャル層１３には埋込層１２に達する高濃度拡
散層２３が設けられている。高濃度拡散層２３はＮ型多
結晶シリコン１７を介してコレクタ電極１９と電気的に
接続されている。Conventionally, a semiconductor integrated circuit device having a bipolar transistor has, for example, a region surrounded by a thick insulating isolation oxide film 11 on the surface of a semiconductor substrate, as shown in FIG.
There is a KJm-containing layer 12 inside the semiconductor substrate under this region. An epitaxial layer 13 is formed on the buried layer 12, and the surface of the epitaxial layer 13 forms the surface of the semiconductor substrate. There is a base layer 14 included inside the epitaxial layer 13 and having a surface height that is the same as the surface of the semiconductor substrate. There is a graft base layer 14' and an emitter layer 15 which are contained within the space layer 14 and whose surface heights are the same as the surface of the semiconductor substrate. The graft base layer 14' is electrically connected to the base electrode 22 through the P-type polycrystalline silicon 18, and the emitter layer 15 is electrically connected to the emitter electrode 21 through the N-type polycrystalline silicon 17. . A high concentration diffusion layer 23 reaching the buried layer 12 is provided in the epitaxial layer 13 under the collector electrode. High concentration diffusion layer 23 is electrically connected to collector electrode 19 via N-type polycrystalline silicon 17.
ここで、高濃度拡散層２３Ｆｉ）ランジスタのコレクタ
直列抵抗を低減し、コレクタ応答時間を短縮し、半導体
装置の高速化をはかるためのものである。Here, the high concentration diffusion layer 23Fi) is intended to reduce the collector series resistance of the transistor, shorten the collector response time, and increase the speed of the semiconductor device.
上述した従来のバイポーラ盤トランジスタを有する半導
体装置は、埋込層１２まで達する深い高濃度拡散１２３
が必要であシ、またコレクタとペース間の耐圧を確保す
るため高濃度拡散層２３とベース層１４を離さなければ
ならないという欠点があった。The semiconductor device having the conventional bipolar disk transistor described above has a deep high concentration diffusion 123 that reaches the buried layer 12.
Moreover, there was a drawback that the high concentration diffusion layer 23 and the base layer 14 had to be separated in order to ensure the withstand voltage between the collector and the paste.
ｔた高濃度拡散層２３の抵抗を下げるために、その不純
物濃度を増すと結晶欠陥が発生しトランジスタの歩留シ
が低下するという欠点があった。If the impurity concentration is increased in order to lower the resistance of the high concentration diffusion layer 23, crystal defects will occur and the yield of transistors will decrease.
本発明の半導体装置は、半導体基板表面にコレクタ電極
を有し半導体基板内部に埋込層を有するバイポーラをト
ランジスタを備え、前記コレクタ電極下の前記半導体基
板表面から前記埋込層に達する溝が形成され、溝の側面
は絶縁膜を有し、溝ノ内部は導電体で埋設され、前記導
電体と前記埋込層及び前記コレクタ電極とが一気的に接
続されていることを特徴とする。The semiconductor device of the present invention includes a bipolar transistor having a collector electrode on the surface of the semiconductor substrate and a buried layer inside the semiconductor substrate, and a groove is formed from the surface of the semiconductor substrate below the collector electrode to the buried layer. The side surface of the groove has an insulating film, the inside of the groove is buried with a conductor, and the conductor, the buried layer, and the collector electrode are connected all at once.
次に１本発明について図面を参照して説明する。 Next, one aspect of the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のバイポーラ盤トランジスタ
の縦断面図である。ｍ１図において、半導体基板表面に
厚い絶縁分離酸化膜１１で周囲を囲まれた領域があシ、
この領域下の半導体基板内部Ｋｍ込層１２がある。埋込
４１２上にエピタキシャル層１３かあシ、エピタキシャ
ル層１３の表面は半導体基板表面をなしている。エピタ
キシャル層１３内部に含まれその表面高さが半導体基板
表面と同じ高さのベース層１４がある。ペース層１４内
部に含まれその表面高さがそれぞれ半導体基板表面と同
じ高さのクラフト６ベース層１４′とエミツタ層１５が
ある。グラフト・ベース層１４’はＰｆｊｌｌ多結晶シ
リコン１８を介してペース電極２２に電気的に接続され
、エミツタ層１５はＮ型多結晶シリコン１７を介してエ
ミッタ電極２１に電気的に接続されている。コレクタ電
極１９下の半導体基板には％埋込層１２の内部に達する
溝が形成され、溝の側面にシリコン酸化膜２０が形成さ
れ、溝の残シの部分はタングステン１６で埋設されてい
る。タングステン１６は埋込層１２とは直接に、または
コレクタ電極１９とはＮ型多結晶シリコン１７を介して
電気的に接続されている。FIG. 1 is a longitudinal sectional view of a bipolar disk transistor according to an embodiment of the present invention. In the m1 diagram, there is a region surrounded by a thick insulating isolation oxide film 11 on the surface of the semiconductor substrate.
There is a Km-containing layer 12 inside the semiconductor substrate under this region. An epitaxial layer 13 is formed on the embedding 412, and the surface of the epitaxial layer 13 forms the surface of the semiconductor substrate. There is a base layer 14 included inside the epitaxial layer 13 and having a surface height that is the same as the surface of the semiconductor substrate. There is a Kraft 6 base layer 14' and an emitter layer 15 which are included inside the space layer 14 and whose surface heights are the same as the surface of the semiconductor substrate. The graft base layer 14' is electrically connected to the space electrode 22 through the Pfjll polycrystalline silicon 18, and the emitter layer 15 is electrically connected to the emitter electrode 21 through the N-type polycrystalline silicon 17. A trench reaching the inside of the buried layer 12 is formed in the semiconductor substrate below the collector electrode 19, a silicon oxide film 20 is formed on the side surfaces of the trench, and the remaining portion of the trench is filled with tungsten 16. Tungsten 16 is electrically connected to buried layer 12 directly or to collector electrode 19 via N-type polycrystalline silicon 17.
上記の構造では、コレクタ電流はエピタキシャル層１３
．埋込層１２．タングステン１６．Ｎ型多結晶シリコン
１７．コレクタ電極１９の順に流れる。従って、従来構
造に比べて、埋込層１２からコレクタ電極１９までの抵
抗が下シ、また、ベース層１４が溝の側面に接しても、
溝の側面のシリコン酸化膜２０によルタングステン１６
とは絶縁されている為にペースとコレクタ間の耐圧が劣
化しない。In the above structure, the collector current flows through the epitaxial layer 13
．． Buried layer 12. Tungsten 16. N-type polycrystalline silicon 17. It flows in the order of collector electrode 19. Therefore, compared to the conventional structure, the resistance from the buried layer 12 to the collector electrode 19 is lower, and even if the base layer 14 contacts the side surface of the groove,
Rutungsten 16 is formed by the silicon oxide film 20 on the side surface of the trench.
Since it is insulated from the conductor, the withstand voltage between the pace and the collector does not deteriorate.
次に本実施例の構造の製造方法について第２図（ａ）〜
げ）に示した工程順縦断面図を用いて説明する。Next, the manufacturing method of the structure of this example is shown in FIGS.
This will be explained using the step-by-step longitudinal cross-sectional views shown in Fig.
まず、累子分離酸化膜１１を形成後、′Ｘ子Ｊし成領域
にシリコン酸化膜とシリコン窒化膜３１を成長させ、フ
ォトレジスト３２をマスクにシリコン窒化膜３１．シリ
コン酸化膜及び基板シリコンをエツチングして溝を形成
する。この際、溝の底部は、エピタキシャル層１３を貫
いて埋込層１２まで達するようにする（第２図（ａ））
。First, after forming the isolation oxide film 11, a silicon oxide film and a silicon nitride film 31 are grown in the isolation region, and the silicon nitride film 31 is grown using the photoresist 32 as a mask. A trench is formed by etching the silicon oxide film and the silicon substrate. At this time, the bottom of the groove should penetrate through the epitaxial layer 13 and reach the buried layer 12 (FIG. 2(a)).
.
次に熱酸化を行なうと溝の内部にのみ酸化膜が形成され
る。更に異方性エツチングを行ない、溝の側面のシリコ
ン酸化膜２０のみを残す（第２図（ｂ） ） 。When thermal oxidation is then performed, an oxide film is formed only inside the trench. Furthermore, anisotropic etching is performed to leave only the silicon oxide film 20 on the side surfaces of the trench (FIG. 2(b)).
その後、シリコン窒化膜３１を除去しタングステン１６
を溝内部に充填させる。その方法としては、気相成長法
によるタングステンの選択成長或いは、タングステン族
を充分厚く付着後、エッチバックを行ない溝にのみタン
グステンを残す方法で行々う（第２図（Ｃ））。After that, the silicon nitride film 31 is removed and the tungsten film 16 is removed.
Fill the inside of the groove. This can be accomplished by selectively growing tungsten using a vapor phase growth method, or by depositing a sufficiently thick layer of tungsten and then etching it back to leave tungsten only in the grooves (FIG. 2(C)).
次にフォトレジスト３３をマスクにイオン注入法によシ
ペース層１４を形成する（第２図（ｄ））。Next, a paste layer 14 is formed by ion implantation using the photoresist 33 as a mask (FIG. 2(d)).
その後、ペース電極用とエミッタ電極用の開孔を設け、
多結晶シリコンを成長させ、ベースコンタクト部にはＰ
型不純物を、エミッタコンタクト部にはＮ型不純物を、
それぞれ多結晶シリコンを介して選択的にドーピングさ
せ、クラフト・ベース層１４′及びエミツタ層１５を形
成する。この時、ベースコンタクト部付近ＫｔｉＰＷ多
結晶シリコン３５が形成され、それ以外の領域にはＮ型
多結晶シリコン３４が形成される（第２図（ｅ））。After that, holes were made for the pace electrode and emitter electrode,
Polycrystalline silicon is grown, and P is added to the base contact area.
type impurity, and N-type impurity in the emitter contact area.
A craft base layer 14' and an emitter layer 15 are formed by selectively doping them through polycrystalline silicon. At this time, KtiPW polycrystalline silicon 35 is formed near the base contact portion, and N-type polycrystalline silicon 34 is formed in the other region (FIG. 2(e)).
最後に％配線用のアルミニウムを付着させフォトエツチ
ング法によシＮ型多結晶シリコン１７を介してコレクタ
電極１９とエミッタ電極２１が形成され、ＰＪ多結晶シ
リコン１８を介してベース電極２２が形成され第２図（
ｆ）ｒｃ示す構造が完成するＯ
なお、上記実施例においては導電層としてタングステン
を用いたが、これに＠らず他の金属、金属ケイ化物、又
は埋込ｌと同一導電型の不純物のドーピングされた多結
晶シリコンを使用することができる〇
〔発明の効果〕
以上説明したように本発明は、バイポーラ型トランジス
タを備えた半導体装置において、コレクタ電極下のシリ
コン基板に溝を形成し、溝の側面に絶縁膜が形成され、
溝の内部は導電体で埋設された構造を介してコレクタ電
極と埋込層を電気的に接続している。こζで溝の内部祉
低抵抗の導電体で埋設されているので微細な溝を用いて
もコレクタ直列抵抗を十分下げる事ができる〇また、ベ
ース層を溝の側面に接して形成してもベースとコレクタ
間の耐圧が低下しない。Finally, aluminum for wiring is deposited, and a collector electrode 19 and an emitter electrode 21 are formed via the N-type polycrystalline silicon 17 using a photoetching method, and a base electrode 22 is formed via the PJ polycrystalline silicon 18. Figure 2 (
f) The structure shown in rc is completed. In the above embodiment, tungsten was used as the conductive layer, but other metals, metal silicides, or impurities of the same conductivity type as the buried l can be doped. [Effects of the Invention] As explained above, the present invention provides a method for forming a groove in a silicon substrate under a collector electrode in a semiconductor device equipped with a bipolar transistor. An insulating film is formed on the sides,
Inside the groove, the collector electrode and the buried layer are electrically connected through a structure buried with a conductor. Since the internal structure of the groove is filled with a low-resistance conductor, the collector series resistance can be sufficiently lowered even if a fine groove is used.Also, even if the base layer is formed in contact with the side surface of the groove, the collector series resistance can be sufficiently lowered. The withstand voltage between the base and collector does not drop.
従って、低コレクタ直列抵抗でかつ小面積のバイポーラ
トランジスタが実現でき、高速化、高集積化が可能な半
導体装置が得られる。Therefore, a bipolar transistor with low collector series resistance and a small area can be realized, and a semiconductor device capable of high speed and high integration can be obtained.
第１図は本発明のバイポーラ型トランジスタの一実施例
の縦断面図、第２図（ａｌ〜（ｆ）ｔｉ第１図に示す実
施例の製造方法を説明するための工程順の縦断面図、第
３図は従来のバイポーラ型トランジスタを示す縦断面図
である。
１１・・・・・・絶縁分離酸化膜、１２・・・・・・埋
込層、１３・・・・・・エピタキシャル層、１４・・団
・ベース層、１４′・・・・・・グラフト・ベース層、
１５・・・・・・エミツタ層、１６・・・・・・タング
ステン、１７．３４・・・・・・Ｎ型多結晶シリコン、
１８．３５・・・・・・Ｐ型多結晶シリコン、１９・・
・・・・コレクタ電極、２０・・・・・・シリコン酸化
膜、２１・・・・・・エミッタ電極、２２・・・・・・
ペース電極、２３・・・・・・高濃度拡散層、３１・・
・・・・シリコン窒化膜、３２．３３・・・・・・フォ
トレジスト。
ｚ０ジグ１ン扉しぞ局岨
錆ｌ 図
鴻２図FIG. 1 is a longitudinal sectional view of an embodiment of a bipolar transistor of the present invention, and FIGS. , FIG. 3 is a vertical cross-sectional view showing a conventional bipolar transistor. 11... Insulating isolation oxide film, 12... Buried layer, 13... Epitaxial layer. , 14... group base layer, 14'... graft base layer,
15... Emitter layer, 16... Tungsten, 17.34... N-type polycrystalline silicon,
18.35...P-type polycrystalline silicon, 19...
...Collector electrode, 20...Silicon oxide film, 21...Emitter electrode, 22...
Pace electrode, 23...High concentration diffusion layer, 31...
...Silicon nitride film, 32.33...Photoresist. z0 jig 1 door slot
Claims (1)
に埋込層を有するバイポーラ型トランジスタを備え、前
記コレクタ電極下の前記半導体基板表面から前記埋込層
に達する溝が形成され、溝の側面は絶縁膜を有し、溝の
内部は導電体で埋設され、前記導電体と前記埋込層及び
前記コレクタ電極とが電気的に接続されていることを特
徴とする半導体装置。A bipolar transistor having a collector electrode on the surface of the semiconductor substrate and a buried layer inside the semiconductor substrate is provided, and a groove is formed from the surface of the semiconductor substrate under the collector electrode to the buried layer, and the side surfaces of the groove are insulated. 1. A semiconductor device comprising a film, the inside of a trench is buried with a conductor, and the conductor, the buried layer, and the collector electrode are electrically connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10861085A JPS61265867A (en) | 1985-05-20 | 1985-05-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10861085A JPS61265867A (en) | 1985-05-20 | 1985-05-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61265867A true JPS61265867A (en) | 1986-11-25 |
Family
ID=14489161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10861085A Pending JPS61265867A (en) | 1985-05-20 | 1985-05-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61265867A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6442859A (en) * | 1987-08-11 | 1989-02-15 | Sony Corp | Bipolar transistor and manufacture thereof |
| JPH02152241A (en) * | 1988-12-02 | 1990-06-12 | Nec Corp | Integrated circuit device |
| JPH02220462A (en) * | 1989-02-21 | 1990-09-03 | Takehide Shirato | Semiconductor device |
| JPH04258132A (en) * | 1991-02-13 | 1992-09-14 | Nec Corp | Semiconductor device and its manufacture |
-
1985
- 1985-05-20 JP JP10861085A patent/JPS61265867A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6442859A (en) * | 1987-08-11 | 1989-02-15 | Sony Corp | Bipolar transistor and manufacture thereof |
| JPH02152241A (en) * | 1988-12-02 | 1990-06-12 | Nec Corp | Integrated circuit device |
| JPH02220462A (en) * | 1989-02-21 | 1990-09-03 | Takehide Shirato | Semiconductor device |
| JPH04258132A (en) * | 1991-02-13 | 1992-09-14 | Nec Corp | Semiconductor device and its manufacture |
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