JPH02152241A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH02152241A JPH02152241A JP30639588A JP30639588A JPH02152241A JP H02152241 A JPH02152241 A JP H02152241A JP 30639588 A JP30639588 A JP 30639588A JP 30639588 A JP30639588 A JP 30639588A JP H02152241 A JPH02152241 A JP H02152241A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- collector
- layer
- collector electrode
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 239000012212 insulator Substances 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路装置に関し、特にトランジスター素子
のコレクタ抵抗を低減することを目的としたものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device, and is particularly directed to reducing the collector resistance of a transistor element.
従来、この種の集積回路装置は、埋込拡散層上にエピタ
キシャル層を有し、埋込拡散層から電極をとり出す時は
、エピタキシャル層を介して、埋込拡散層と同じ導電型
の不純物を埋込拡散層まで拡散し、この拡散層からＡｕ
等の金属により電極をとり出す構造となっていた。Conventionally, this type of integrated circuit device has an epitaxial layer on a buried diffusion layer, and when an electrode is taken out from the buried diffusion layer, an impurity of the same conductivity type as the buried diffusion layer is inserted through the epitaxial layer. The Au is diffused to the buried diffusion layer, and the Au
The structure was such that the electrodes were extracted from metals such as.
上述した従来の集積回路装置は埋込拡散層とコレクタ電
極の間に拡散層を有するため、この拡散層の抵抗成分が
無視できないという欠点がある。Since the conventional integrated circuit device described above has a diffusion layer between the buried diffusion layer and the collector electrode, there is a drawback that the resistance component of this diffusion layer cannot be ignored.
本発明の集積回路装置は、埋込拡散層に直接Ａ１等金属
の電極が接続されたコレクタ電極を有している。The integrated circuit device of the present invention has a collector electrode in which a metal electrode such as A1 is directly connected to the buried diffusion layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。集積回路装
置内のＮＰＮ）ランジスタに適用した例である。Ｐ型基
板１にｎ＋埋込層２を形成した後、エピタキシャル層３
を成長させる。ベース５を形成した後、コレクタ電極１
０となる部分をＳｆエツチングする。このエツチングは
ｎ＋埋込層２のところまで行なう。次に酸化等により絶
縁物７′を形成し、ｎ＋埋込層２と接する部分の絶縁物
を除去する。次にエミッタ６を形成する。この時同時に
コレクタコンタクト（ｎ”）４も形成される。その後、
蒸着等の方法によりコレクタ電極１１０′を形成し最後
にベース電極、エミッタ電、極、コレクタ電極ＩＩ
１０を形成する。第２図は本発明の他の実施例２の断面
図である。集積回路装置内の縦型ＰＮＰ ）ランジスタ
のコレクタ電極に適用した例である。構成については実
施例１のＮＰＮトランジスタと重複するため省略する。FIG. 1 is a sectional view of an embodiment of the present invention. This is an example in which the present invention is applied to an NPN transistor in an integrated circuit device. After forming an n+ buried layer 2 on a P-type substrate 1, an epitaxial layer 3 is formed.
grow. After forming the base 5, the collector electrode 1
Sf etching is performed on the portion where the value becomes 0. This etching is performed up to the n+ buried layer 2. Next, an insulator 7' is formed by oxidation or the like, and the insulator in a portion in contact with the n+ buried layer 2 is removed. Next, emitter 6 is formed. At this time, a collector contact (n”) 4 is also formed at the same time. After that,
A collector electrode 110' is formed by a method such as vapor deposition, and finally a base electrode, an emitter electrode, a pole, and a collector electrode II are formed.
form 10. FIG. 2 is a sectional view of another embodiment 2 of the present invention. This is an example in which the present invention is applied to a collector electrode of a vertical PNP transistor in an integrated circuit device. The configuration is the same as that of the NPN transistor of the first embodiment, so a description thereof will be omitted.
以上説明したように本発明は直接ＡＡ等の金属により電
極を引き出す事によって、コレクタ電極■直下の抵抗を
大幅に低減できる効果がある。例えば、コレクタ引き出
し拡散層は通常１０Ω／口の層抵抗であり、コレクタ電
極■にＡ４を使った場合２０ｍΩ／口の層抵抗である。As explained above, the present invention has the effect of significantly reducing the resistance directly under the collector electrode (2) by directly drawing out the electrode using a metal such as AA. For example, the collector lead-out diffusion layer usually has a layer resistance of 10 Ω/hole, and when A4 is used for the collector electrode (2), the layer resistance is 20 mΩ/hole.
このことから本発明の場合、コレクタ電極■直下の抵抗
は従来の１７５００に低減できる効果がある。Therefore, in the case of the present invention, the resistance directly under the collector electrode 1 can be reduced to 17,500 compared to the conventional one.
第１図は本発明の実施例１の断面図、第２図は本発明の
実施例２の断面図である。
１・・・・・・Ｐ型基板、２・・・・・・ｎ＋埋込層、
３・・・・・・エピタキシャル層、４・・・・・・コレ
クタコンタクト（口゛）、訃・・・・・ベース、６・・
・・・・エミッタ、７・・・・・・絶縁物、７′・・・
・・・絶縁物、８・・・・・・ベース電極、９・・・・
・・エミッタ電極、１ｏ・・・・・・コレクタ電極ｎ、
１０’ ・・・・・・コレクタ電極■、１１・・・・・
・Ｐ＋埋込層、１２・・・・・・コレクタコンタクト（
Ｐ”）、１３・・・・・・エミッタ、１４・・・・・・
ベース、１５・・・・・・エミッタ’［１１６・・・・
・・ベース電極、１７・・・・・・コレクタ引き出し拡
散層、１８・・・・・・コレクタコンタクト拡散層。
代理人 弁理士 内 原 晋FIG. 1 is a sectional view of Embodiment 1 of the present invention, and FIG. 2 is a sectional view of Embodiment 2 of the present invention. 1...P type substrate, 2...N+ buried layer,
3...Epitaxial layer, 4...Collector contact (mouth), End...Base, 6...
...Emitter, 7...Insulator, 7'...
...Insulator, 8...Base electrode, 9...
...Emitter electrode, 1o...Collector electrode n,
10'... Collector electrode ■, 11...
・P+ buried layer, 12... Collector contact (
P”), 13... Emitter, 14...
Base, 15...Emitter' [116...
... Base electrode, 17 ... Collector lead-out diffusion layer, 18 ... Collector contact diffusion layer. Agent Patent Attorney Susumu Uchihara
Claims (1)
記半導体層に有し、この溝を介して前記埋込領域に電極
が形成されていることを特徴とする集積回路装置。An integrated circuit device having a buried region in a semiconductor layer, a groove in the semiconductor layer reaching the buried region, and an electrode formed in the buried region through the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30639588A JPH02152241A (en) | 1988-12-02 | 1988-12-02 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30639588A JPH02152241A (en) | 1988-12-02 | 1988-12-02 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02152241A true JPH02152241A (en) | 1990-06-12 |
Family
ID=17956501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30639588A Pending JPH02152241A (en) | 1988-12-02 | 1988-12-02 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02152241A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100832716B1 (en) * | 2006-12-27 | 2008-05-28 | 동부일렉트로닉스 주식회사 | Bipolar junction transistor and method for fabricating the same |
| KR101004801B1 (en) * | 2002-12-26 | 2011-01-04 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor bipolar |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5396766A (en) * | 1977-02-04 | 1978-08-24 | Nec Corp | Semiconductor device |
| JPS61265867A (en) * | 1985-05-20 | 1986-11-25 | Nec Corp | Semiconductor device |
| JPS6386476A (en) * | 1986-09-29 | 1988-04-16 | Mitsubishi Electric Corp | Manufacture of semiconductor integrated circuit device |
| JPS63204649A (en) * | 1987-02-19 | 1988-08-24 | Nec Corp | Semiconductor device |
| JPS63237471A (en) * | 1987-03-26 | 1988-10-03 | Toshiba Corp | Semiconductor device and its manufacture |
-
1988
- 1988-12-02 JP JP30639588A patent/JPH02152241A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5396766A (en) * | 1977-02-04 | 1978-08-24 | Nec Corp | Semiconductor device |
| JPS61265867A (en) * | 1985-05-20 | 1986-11-25 | Nec Corp | Semiconductor device |
| JPS6386476A (en) * | 1986-09-29 | 1988-04-16 | Mitsubishi Electric Corp | Manufacture of semiconductor integrated circuit device |
| JPS63204649A (en) * | 1987-02-19 | 1988-08-24 | Nec Corp | Semiconductor device |
| JPS63237471A (en) * | 1987-03-26 | 1988-10-03 | Toshiba Corp | Semiconductor device and its manufacture |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101004801B1 (en) * | 2002-12-26 | 2011-01-04 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor bipolar |
| KR100832716B1 (en) * | 2006-12-27 | 2008-05-28 | 동부일렉트로닉스 주식회사 | Bipolar junction transistor and method for fabricating the same |
| US7816763B2 (en) | 2006-12-27 | 2010-10-19 | Dongbu Hitek Co., Ltd. | BJT and method for fabricating the same |
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