JPH0484437A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a speed and a frequency by growing an insulating film on one main surface of a first conductivity type single crystalline semiconductor layer, opening the film by selectively anisotropically etching, and then growing a second conductivity semiconductor film thinner than the insulating film by a silicon molecular beam epitaxial method. CONSTITUTION:An insulating film 12 is opened by selectively anisotropically etching by using reactive ion etching to provide a base region 13. Then, P-type silicon MBE films 14a, 14b are formed, for example, 500Angstrom thick by using Si- MBE. In this case, the thickness TB of the film is formed thinner than that tB of the film 12 so as to form a single crystalline MBE film 14a on the region 13 and a polycrystalline MBE film 14b on the film 12 separately. Thereafter, the film 14b is selectively removed by etching, an SiO2 insulating film 17 is formed by a CVD method, and an emitter contact 18 and base contacts 19a, 91b are then opened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an ultra-high frequency, ultra-high speed bipolar transistor.

[Conventional technology]

In recent years, the frequency of bipolar transistors has increased.

Significant progress has been made in increasing speed. As a technology that plays a prominent role in increasing the frequency and speed of bipolar transistors,
Formation of shallow junctions and microfabrication have been performed. In particular, regarding the formation of the former shallow junction, the ion implantation method has been utilized, contributing to higher frequencies of transistors. However, although the ion implantation method has the great advantage of being simple and highly versatile as a process, there is a physically unavoidable phenomenon called channeling of the implanted ions, so it is particularly important for P-type bases. Regarding the layer, it is approximately 0.2
It is impossible to form a shallow junction of less than μm, and the implanted ions have a nearly Gaussian profile, so in order to form a shallow junction, the peak concentration must be lowered. Therefore, the base resistance Since the increase in frequency is unavoidable, this is an obstacle to achieving higher frequencies.

As a solution to this problem, silicon molecular beam epitaxy (Si-MBE) has recently been attracting attention. S
Since i-MBE allows the formation of silicon layers on the atomic order, it is possible to form base layers as thin as 0.2 μm, or even thin base layers of several hundred Å or less (P-type layer for NPN transistors) with extremely good controllability. . Since MBE allows the impurity concentration to be controlled independently of the film thickness, it is possible to control the impurity concentration independently of the film thickness.
It is quite easy to form a base layer with a high concentration of about 0 atoms/cf, and it can be said to be essential for increasing the frequency of bipolar transistors.

For example, a method for manufacturing a transistor using Si-MBE is shown in FIGS. 5(a) to 5(e), which are cross-sectional views in the order of manufacturing steps. An N-type silicon epitaxial layer 51 is grown on an N-type silicon substrate 55, and S is further grown by thermal oxidation.
After forming the insulating film 52 of ing, a photoresist 514 is applied.
is applied and exposed to light (Fig. 5(a)). Next, a portion that will become the base region 53 is coated with ammonium fluoride (NH) in hydrofluoric acid.
4F) The insulating film 52 is opened and provided by etching using a buffer solution containing 1 (FIG. 5(b)). Next, using Si-MBE, silicon and boron as a solid source are ejected with an electron gun at an atmospheric pressure of 10-' Torr, and a P-type silicon M
BE films 54a and 54b are grown (FIG. 5(C)).

Furthermore, an insulating film 57 of Sio□ is grown on this surface by the CVD method, and base contacts 59a, 59b and emitter contact 58 are provided (FIG. 5(d)). Next, an N-type polycrystalline silicon electrode 512 doped with arsenic is formed on the emitter contact 58, and a P-type silicon M
Arsenic is diffused into the BE film 54a to form an N-type silicon layer 51.
Form 1. Furthermore, base contacts 59a, 59b
and a P-type can crystal silicon electrode 513a.

513b (FIG. 5(e)). Thereafter, wiring lines 517, 518, bonding pads 515, 516, etc. are provided using aluminum as shown in the plan view of FIG. 51 CF').

[Problem to be solved by the invention]

In this conventional semiconductor device manufacturing method, the P-type silicon MBE films 54a and 5 of the base layer formed of Si-MEE are
A single-crystal P-type silicon MBE film 54a grows on the base region 53 of 4b, but a polycrystalline P-type silicon MBE film 54b grows on the insulating film 52. There were some problems. (1) At the boundary between the single-crystal MBE film 54a and the polycrystalline MBE film 54b, a region where both phases coexist spreads, and near the outer edge of the base region 53 there are crystal defects due to the coexistence of both phases. There is. For this reason, heavy metals incorporated into this defective structure cause leakage current to flow from the collector to the base through the depletion layer where there are no conductive carriers due to the application of reverse bias, and current amplification as the base recombination current increases. There was a problem in that it led to a decrease in the rate. (2) Since the tapered portion 510 of the insulating film 52 is thinner than other parts of the insulating film 52 where the polycrystalline film 54b is present, it is possible to not only increase the base-collector capacitance but also increase the thickness of the polycrystalline film 54b. Since the single crystal film 54b and the single crystal film 54a are electrically coupled, the capacitance between the pace collectors becomes large, which poses a problem that hinders high speed and high frequency.

An object of the present invention is to provide a method for manufacturing a semiconductor device that is suitable for high speed and high frequency and is less likely to cause crystal defects.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention includes growing an insulating film on one main surface of a single-crystal semiconductor layer of a first conductivity type, selectively opening the insulating film using anisotropic etching, and then The method is characterized in that a semiconductor film of the second conductivity type, which is thinner than the insulating film, is grown by a silicon molecular beam epitaxial method.

In the method for manufacturing a semiconductor device according to the present invention, anisotropic etching is used to selectively form openings in the insulating film.
The opening edge of the insulating film can be made substantially perpendicular to the surface of the semiconductor layer. After that, a second conductivity type semiconductor film is grown using silicon molecular beam epitaxy.
Due to the selectivity of the molecular beam epitaxial method, the semiconductor film is divided into a first part on the single crystal semiconductor layer and a second part on the insulating film at the opening edge of the insulating film. All of the semiconductor layers are substantially single crystal. Therefore, in a transistor in which the first portion of the semiconductor layer is formed as, for example, a base region, leakage current can be reduced, and parasitic capacitance can also be reduced.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views in the order of manufacturing steps, showing a method for manufacturing an individual transistor according to a first embodiment of the present invention. First, an N-type silicon epitaxial layer 11 is grown on a high concentration N-type silicon substrate 15, and an element isolation region 16 is grown.
A trench 119 is provided where
). After filling the trench 119 in FIG. 1(a) with SiC2 to form the element isolation region 16, an insulating film 12 of 5jOz is formed.
For example, the film is formed to a thickness of 1,000 mm using the CVD method.

Next, a photoresist 114 is applied and exposed (FIG. 1(b)). Next, anisotropic etching is performed using reactive ion etching (RIE) to selectively open the insulating film 12 and form the base region 13. When anisotropic etching is used, the shape of the vertical cross section of the opening edge portion of the insulating film becomes almost vertical. As the etching gas, a gas obtained by adding H2 to CF4 is used.

The etching gas containing CF and 02 also etches the photoresist that serves as a mask, so the insulating film 1
This is not preferable because a tapered portion is formed at the opening of No. 2. In this way, as shown in Figure 1 (C), the null is formed. Next S i −
P-type silicon MBE films 14a and 14b using MBE
For example, the thickness is 500. At this time, the film thickness T
B is thinner than the thickness 1B of the insulating film 12<('rB<tB)
A single crystal MBE film 14a is formed in the base region 13.
Polycrystalline MBE films 14b are formed separately on the insulating film 12 (FIG. 1(d)). Next, the P-type silicon polycrystalline MBE film 14'b is selectively removed by etching, and a 5iCh insulating film 17 is formed to a thickness of, for example, 1,600 by CVD, and then the emitter contact 18 and base contacts 19a, 19b are formed. Open. In this way, it becomes as shown in FIG. 1(e). Furthermore, an N-type polycrystalline silicon electrode doped with arsenic is formed on the emitter contact 18 in the same way as that formed in FIG.
An N-type silicon layer to serve as an emitter is formed by diffusing into the E film 14a, P-type can crystal silicon electrodes are formed on the space contacts 19a and 19b, and wiring, bonding pads, etc. are provided with aluminum. Individual transistors are manufactured in this way.

Here, the element isolation region 16 may be formed by selectively oxidizing the N-type silicon epitaxial layer 11.
When using i3N+, it is only necessary to change the RIE etching material. The insulating film 17 may also have a two-layer structure of 51xNt and SiO□. Furthermore, in order to form a PNP transistor, the conductivity types of the semiconductor layers may be reversed.

FIGS. 2(a) to 2(e) are cross-sectional views showing the steps of manufacturing a semiconductor integrated circuit according to a second embodiment of the present invention. After forming an N-type silicon buried layer 221 on a P-type silicon substrate 220, an N-type silicon epitaxial layer 21 is grown, and an element isolation region 26 is formed by selective oxidation. More 5i0
After forming the second insulating film 22 to a thickness of, for example, 1,000 layers by CVD, a collector contact 222 is opened (FIG. 2(a)). Next, a collector lifting portion 223 is formed by arsenic ion implantation followed by heat treatment, and a photoresist 214 is applied and exposed to light (FIG. 2(b)). Next, as in the first embodiment, anisotropic etching, such as RIE, is performed.
The insulating film 22 is opened to provide a base region 23 (second
Figure (C)). Furthermore, using Si-MBE, P-type silicon)7
MBE film 24a.

After that, the P-type silicon polycrystalline MBE film 24b is selectively removed by etching (FIG. 2(d)). Then, an insulating film 27 of 5iOz is formed with a thickness of, for example, 1600A by the CVD method, an emitter contact and a base contact are opened, an N-type polycrystalline silicon electrode 212 doped with arsenic is formed as the emitter contact, and the arsenic is removed by heat treatment. An N-type silicon 7 layer 211, which will become an emitter, is formed by diffusing into the P-type silicon MBE film 24a of the base layer. Then, P-type polycrystalline silicon electrodes 213a and 21 are used as base contacts.
3b, and an N-type polycrystalline silicon electrode 223 is provided on the collector contact 222 (FIG. 2(e)). Finally, wiring and bonder pads are formed using aluminum to form the transistors of the integrated circuit.

Note that the element isolation region 26 is made of SiO2 or S in the trench structure.
The insulating film 22 may be formed by filling I3N4, or when the element isolation region 26 is made of SiO2, the insulating film 22 may be formed by thermal oxidation of the surface of the semiconductor element.

FIGS. 3(a) to 3(c) are cross-sectional views of the third embodiment of the present invention in the order of manufacturing steps, and are examples in which the method is applied to the formation of a base of a self-aligned transistor. As in the first embodiment, after forming the P-type base silicon single crystal MBE film 34a as shown in FIG.
It serves as an electrical contact point with the BE film 34a. After this, a second insulating film 37 is grown, followed by emitter contact 3.
8. Opening the base contacts 39a, 39b, etc. is the same as in the first example (Fig. 3(b)).Furthermore, the N-type polycrystalline silicon electrode 3 is formed in the emitter contact 38.
12, and the impurities in the electrode are diffused into the P-type base by heat treatment to form an N-type 9977 layer 311 that becomes an emitter.
P-type polycrystalline silicon electrodes 313a and 313b are formed on base contacts 39a and 39b (FIG. 3(C)). After this, the wiring and the Bondi P-type polycrystalline silicon layer 325 are anisotropically etched with aluminum, and the insulating film 32 and the P-type silicon polycrystalline silicon layer 325 are etched on the base region 33.
A polycrystalline silicon layer 325 is left only on the side wall portion of the film 34b, and this is formed into a P-type silicon polycrystalline MBE for base extraction.
FIG. 4 is a cross-sectional view of the film 34b and the film 34b when applied to emitter formation in a fourth embodiment of the present invention. As in the first embodiment, after forming a base and growing an insulating film 47, an emitter contact 48a is opened and a Nu Si-MBEI is formed.
This figure shows the state immediately after IiK44a' and 44b' are formed to be thinner than the insulating film 47, and then the N-type polycrystalline film 44b' on the insulating film 47 is selectively etched. Subsequently, a base contact is opened and an electrode is formed to complete the transistor.

In this example, Si-MB is used to form the base layer 44a'.
Although an example using E is shown, it goes without saying that the same can be achieved by forming by ion implantation or diffusion.

C Effects of the Invention] As explained above, the present invention utilizes the steps of the opening formed in the insulating film on the semiconductor layer of the first conductivity type by anisotropic etching to form the second conductivity type by Si-MBE. Since the single crystal layer and the polycrystalline layer of the conductive type semiconductor layer are separated, the MBE single crystal layer is free from crystal defects due to coexistence with polycrystals, and there is no need to increase leakage current or base recombination current. Since the capacitance between the pace and collector can be reduced, it has the effect of increasing the frequency and speed of the transistor.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are cross-sectional views of the manufacturing process order of the first embodiment of the present invention, and FIGS. 2(a) to (e) are sectional views of the manufacturing process order of the second embodiment of the present invention. 3(a) to (
c) is a cross-sectional view of the transistor according to the third embodiment of the present invention in the order of manufacturing steps, FIG. 4 is a cross-sectional view of the transistor according to the fourth embodiment of the present invention, and FIGS. 5(a) to (e) are FIG. 5 O'), which is a sectional view showing the order of manufacturing steps in a conventional semiconductor device manufacturing method, is a plan view of the semiconductor device. 11.21, 31, 41.51... N-type silicon epitaxial layer, 12, 22, 32, 42° 52.
17, 27, 37, 47.57... Insulating film, 1
3.23, 33.53...Base area, 14a
, 24a, 34a, 44a, 54a=--P-type silicon single-crystal MBE film, 44a'...N-type silicon single-crystal MBE film, 14b, 24b, 34b. 44b, 54b...P-type silicon polycrystalline MBE
film, 44b'...N-type silicon polycrystalline MBE film,
15.35, 45.55...High concentration N-type silicon substrate, 16,26,36.46...Element isolation region, 18.38.58...Emitter contact , 19a, 19b, 39a, 39b, 59a, 59b
...Pace contact), 510...Taber portion, 211.311, 511...N-type silicon layer, 212.312,512,224...
N-type polycrystalline silicon electrodes, 213a, 213b, 313
a. 313b, 513a, 513b - P-type can crystal silicon electrode, 114, 214, 514... Photoresist, 515... Bonding butt for emitter, 516... Bonding for base. Pa F゛,
517.518...Aluminum wiring, 119.
,.・Trench, 220...P type! , 1 core board, 2
21... N-type silicon buried layer, 222...
Collector contact, 223... Collector pull-up portion, 325... P-type polycrystalline silicon layer. Agent Susumu Uchihara, Patent Attorney Figure 1 ((L) Figure 1 (first close (b) Figure 7 (e) Figure cb) Figure 2 (e) Figure 2 (d) Figure 30 ( α) Figure 3 CC) Figure 4 Figure 5 <C) Figure 5 (d) Figure S (0-) Figure (b) Figure ! ; to ce) Figure 5 (f)

Claims (1)

[Claims] After growing an insulating film on one main surface of a single crystal semiconductor layer of a first conductivity type and selectively opening the insulating film using anisotropic etching, a second conductive film having a thickness thinner than that of the insulating film is formed. 1. A method for manufacturing a semiconductor device, characterized in that a semiconductor film of a mold type is grown by a silicon molecular beam epitaxy method.