KR940007657B1 - Manufacturing method of high-speed bipolar transistor - Google Patents

Abstract

The method is for manufacturing a high speed bipolar transistor by using a selective thin film growth method and a heterojunction method. The method includes the steps of: (A) forming N+ silicon layer (31) and N-silicon layer (32) and defining an active region; (B) forming an ohmic contact (33) by injecting ion on an N-silicon layer (32); (C) forming an emitter region; (D) forming a side insulating layer (40) and forming an oxide layer; (E) polishing a polysilicon layer (42) to expose an insulating layer (38); (F) oxiding a polysilicon (42); (F) forming a silicon-germanium layer (45) on an exposed emitter region by using a gas source molecular beam epitaxy; (G) forming an emitter region by spraying polysilicon; and (H) vaporizing a metal to form an electrode.

Description

Manufacturing method of high speed dipole transistor device

1 is a cross-sectional view of a self-aligned heterojunction dipole device manufactured by a conventional selective thin film growth method.

2 is a cross-sectional view of a completed self-aligned heterojunction dipole device according to the present invention.

3 is a cross-sectional view of a fabrication process sequence of a self-aligned heterojunction dipole device using the selective thin film growth method according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a high speed bipolar transistor (Transistor) that can be used in a next generation high speed information processing system such as a computer or a communication device. A method of manufacturing an ordered heterojunction high speed dipole transistor.

In general, unlike a homojunction dipole transistor, a heterojunction dipole device using an energy bandgap difference by using an emitter and a base material different from each other is used. Intensive research as a next-generation high-speed dipole device.

In this heterojunction dipole device design, the most important thing to consider is to reduce the parasitic resistance and parasitic capacitance due to mask misalignment.

Recently, heterojunction dipole devices reduce the size of the horizontal and vertical devices by simultaneously using polysilicon as emitter, base electrode and diffusion source. Is composed of silicon germanium instead of silicon, resulting in energy band gap between emitter and base, increasing emitter injection efficiency, and growing base to high impurity concentration ultra-thin film to amplify device current Current gain and operating speed have been greatly improved.

An example of such a representative self-aligned heterojunction device is shown in FIG.

1 is a cross-sectional view of a conventional n-p-n heterojunction dipole device manufactured by Super Self-aligned Selectively Grown Base.

In FIG. 1, a silicon source maenyum (SiGe) base (selectively only exposed to silicon (Si) and polysilicon) using a gas source Molecular Beam Epitaxy (MBE) method 12), the polycrystalline silicon 14 and the silicon low maenyum base 12 for the base electrode are connected by selectively growing the polycrystalline silicon 16 only in the polycrystalline silicon or the polycrystalline silicon low maenyum portion to fill the remaining empty space. Was completed.

The next step is to dry-etch silicon oxide anisotropically while protecting the silicon low maenyum, an ultra-thin film, to form a side insulating film 17 to form the polysilicon 14 for the base electrode. The emitter portion 11 made of polycrystalline silicon was self-aligned.

In addition, in order to reduce the contact resistance between the polysilicon emitter and the metal, a tungsten layer 18 was applied by chemical vapor deposition (CVD) and inserted between the emitter and the metal.

However, the wet etch process for forming the side grooves to be selectively grown by growing the silicon low maenyum (12) and the polycrystalline silicon (16) must be perfect, otherwise the performance of the device is fatal, By applying the relatively difficult selective thin film growth process twice to the growth of silicon low maenyum and polysilicon thin film, the yield of the device or IC (Integranted Circuit) is reduced and the polycrystalline silicon to be selectively grown when the side grooves are filled It involves the difficulty of precisely adjusting the thickness.

Therefore, in order to solve the above-mentioned problems, the present invention uses a selective thin film growth method and emitter-base and base-collector are self-aligned so that the device manufactured by using gas source molecular beam crystal thin film growth method. It is an object of the present invention to provide a method for manufacturing a heterojunction high speed dipole transistor having improved structural problems.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows, as in FIG. 1, an emitter portion of polycrystalline silicon and polycrystalline silicon for the base electrode as a cross-section of a self-aligned heterojunction dipole element using a gas source molecular beam crystal thin film growth method.

Since the device shown in FIG. 2 uses a very simple and reliable process, the device shown in FIG. 2 has an advantage of greatly increasing the reproducibility of the manufacturing process. That is, in FIG. 1, it is difficult to precisely adjust the groove depth because the wet etching is used when defining the side groove portion.

This causes the parasitic capacitance between the base collector (Collector) and the conventional device is difficult to reduce or adjust it. On the other hand, in the structure of FIG. 2 manufactured by the present invention, after the collector 23 is grown, the emitter layer is deposited and etched to define the emitter region, and the side insulating film is formed to form the polycrystalline silicon 24 for the base electrode. Since the area in contact with the silicon low maenyum 22 base is secured, it becomes a parasitic capacitance component between the base and the collector by the thickness of the side insulating film.

At this time, the thickness of the side insulating film can be reduced within the limit of minimizing the influence of the Bird's Bick thermal silicon oxide film formed during the thermal oxidation process of the collector silicon layer 23, thereby reducing the parasitic capacitance between the base and the collector. There are advantages in device design that can be achieved.

In addition, the structure of FIG. 2 thermally oxidizes 25 a portion of the polycrystalline silicon 24 for the base electrode to isolate the polycrystalline silicon emitter 21 deposited later from the polycrystalline silicon 24 for the base electrode. Since the silicon low maenyum base 22 is grown after the insulating film is etched, the parasitic resistance of the base is small at a given base impurity concentration because the portion of the intrinsic base other than the device active region is smaller than the structure of FIG. Therefore, an increase in cutoff frequency and maximum oscillation frequency, which are highly dependent on parasitic capacitance and parasitic resistance, are expected.

Subsequently, as shown in FIG. 1, a side insulating film is formed on the base portion, isolated from the polycrystalline silicon emitter 21 deposited in the next step, and then the insulating film is applied to the polysilicon emitter portion for metal wiring. Form a contact. Then, metal wiring is completed to complete the device.

Therefore, the structure of FIG. 2 uses the selective thin film growth technology only in forming the silicon low maenyum base layer, and the process is simplified and the yield is increased by not using the relatively difficult selective polysilicon thin film growth process as shown in FIG. do.

As such, the present invention (FIG. 2) self-aligns the emitter and the base, and the base parasitic resistance and the collector parasitic capacitance are greatly reduced compared to the device of FIG.

In addition, since a very simple and reliable process was used as compared with FIG. 2, the manufacturing process became stable.

Figure 3a-i is a manufacturing process flow chart of an embodiment of the present invention will be described in detail as follows.

In FIG. 3A, after implanting impurity ions into the P ⁺ -type silicon substrate 30 to form an N ⁺ -type silicon layer 31, which is a connecting portion between the collector and the metal, the molecular beam crystal thin film growth method is used. The collector thin film 32, an N-silicon layer, is grown, and the device is isolated by trench 35 isolation process, then an insulating film is applied, masking, dry etching and local oxidation isolation process (Local oxidation) are performed. of silicon (LOCOS), and then the collector is connected to the surface of the collector layer 31 vertically to the surface by ion implantation (36) The process is shown.

3b shows a process for defining an emitter region. First, the multilayer insulating films 37, 38, and 39 are sequentially applied, and the emitter region is defined by a mask operation and an etching process.

Subsequently, the insulating film on the partially exposed active region is etched and removed.

3C shows a process of applying an insulating film, leaving the side insulating film 40 by anisotropic dry etching, and thermally oxidizing the remaining exposed silicon portion 41.

FIG. 3 shows a process of removing the side insulating film 40 by etching, depositing a polysilicon film 42, and performing a planarization process using a photoresistor 43.

3E shows a process of removing the photoresist film 43 and the polysilicon film 12 until the insulating film 38 is exposed by the planarization process, and then etching the polysilicon.

FIG. 3 shows a process of thermally oxidizing the polycrystalline silicon 42 after removing the photosensitive film 43 and the insulating film 38.

FIG. 3G shows that the insulating films 37 and 33 of the emitter region are etched to partially expose the collector 32 and the polysilicon 42 for the base electrode, and then using a gas source molecular beam crystal thin film growth method. The side insulating film 46 is formed by etching the insulating film while protecting the ultra-thin silicon silicon maenyum layer 45 selectively grown only in the exposed emitter region.

This achieves self alignment by isolating the emitter to be applied in the next step from the polycrystalline silicon for the base and base electrode.

FIG. 3 shows a process of defining and forming an emitter by applying a polycrystalline silicon to be used as an emitter and then masking and etching.

3 is a completed cross-sectional view of the device process.

After the emitter definition process, an insulating film is deposited on the substrate, and a mask operation and an etching process are performed to make contacts in the emitter, base, and collector regions, and the metal 48 is deposited to define wiring using a mask to etch the metal.

In the above description of the manufacturing process of one embodiment, it will be apparent to those skilled in the art that the present invention may be implemented differently without departing from the spirit of the present invention.

Claims (1)

The N ⁺ type silicon layer 31 and the N ⁻ type silicon layer 32 are sequentially stacked on the P ⁺ type silicon substrate 30, and the device is isolated by the isolation process of the trench 35, and then the device is activated. A process of defining a region, an ion implantation into the N ^- type silicon layer 32 to form an ohmic contact 33 for metal contact, and then applying a multilayer insulating film 37, 38, 39 to a mask And defining an emitter region by an etching process, subsequently applying an insulating film, and then forming an insulating layer 40 by anisotropic dry etching and thermally oxidizing the exposed silicon portions. And then depositing a polysilicon film 42 and planarizing the exposed insulating film 38 using the coated photosensitive film 43, and removing the photosensitive film 43 and the insulating film 38 and then polycrystalline silicon. Thermally oxidizing (42) and etching the insulating films (37) (33) in the emitter region In addition, by using a gas source molecular beam crystal thin film growth method, the ultra-thin silicon silicon maenyum layer 45 is grown and the side insulating film 46 is formed only in the exposed emitter region, and polycrystalline silicon is applied to the emitter region. Forming a emitter, and depositing a metal to form an electrode.