JP2633374B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a bipolar transistor is operated at high speed and miniaturized, and a method of manufacturing the same.

2. Description of the Related Art In recent years, bipolar transistors have been miniaturized beyond the limits of photolithography by self-alignment technology, and have realized extremely high-speed and high-performance characteristics. FIGS. 2 (a) to 2 (d) show a conventional semiconductor device and a method of manufacturing the same.
An example of a method for manufacturing an NPN transistor is shown in FIG.

First, as shown in FIG. 2A, a P-type silicon substrate 18 is formed.
After the N-type buried collector layer 19 is formed on the surface of the substrate, an N-type epitaxial layer 20 is grown. Next, element isolation LOCOS film 21
Is formed on the surface of the N-type epitaxial layer 20, a P ⁺ polysilicon 22 serving as a base extraction electrode, and then a CVD oxide film 2 are formed.
3 grow on the whole surface. Next, the CVD oxide film 23 and subsequently the P ⁺ polysilicon 22 are selectively etched away using a photoresist by photolithography as a mask to expose an intrinsic base region 24 on the surface of the N-type epitaxial layer 20.

Next, as shown in FIG. 2B, the side surfaces of the P ⁺ polysilicon base extraction electrode 22 and the exposed surface of the intrinsic base region 24 are oxidized to form oxide films 25 and 26, respectively. P ⁺
The impurity concentration of the polysilicon 22 is equal to that of the N-type epitaxial layer 20.
Very high compared to the oxide film on the surface of the intrinsic base region 24
26 can be formed thinner than the oxide film 25 on the side surface of the P ⁺ polysilicon 22. In order to suppress the diffusion of impurities in the P ⁺ polysilicon 22 into the N-type epitaxial layer 20 in this step, oxidation is performed.
Perform at a low temperature of about 800 to 850 ° C.

Next, as shown in FIG. 2C, an oxide film is left only on the side surface of the P ⁺ polysilicon 22 by anisotropic etching of the oxide film, and an oxide film sidewall 27 and an emitter lead-out opening 28 are formed. Further, heat treatment is performed to convert P ⁺ polysilicon 22 to P
A type impurity is introduced into the N-type epitaxial layer 20 to form a P-type external base layer 29.

Finally, as shown in FIG. 2 (d), the polysilicon grown on the entire surface is selectively etched away using a photoresist by photolithography as a mask to form an emitter extraction electrode 30, and then a polysilicon emitter extraction electrode. P-type impurities are ion-implanted into the semiconductor substrate 30, and P-type impurities are introduced from the polysilicon emitter extraction electrode 30 through the emitter extraction hole 28 by heat treatment to form a P-type intrinsic base layer 31.
To form In addition, polysilicon emitter extraction electrode 30
N-type impurities are ion-implanted, and a polysilicon emitter extraction electrode is passed through an emitter extraction hole 28 by heat treatment.
An N-type impurity is introduced from 30 to form an N-type emitter layer 32.

According to the semiconductor device and the manufacturing method described above, the external base layer 29, the emitter layer 32, the base electrode lead portion 22, and the emitter electrode lead portion 30 of the bipolar transistor having the extremely shallow junction intrinsic base layer 31 are all self-aligned. , And it is possible to dramatically increase the speed and miniaturization of the bipolar transistor.

SUMMARY OF THE INVENTION In such a conventional semiconductor device, a base extraction electrode is provided.
22 The thickness of the oxide film sidewall 27 and the thickness of the external base layer 29 or the intrinsic base layer are so set that the external base layer 29 and the intrinsic base layer 31 sufficiently overlap under the oxide film sidewall 27 on the side wall.
The junction depth of 31 has been optimized to avoid punch-through leakage between the collector and emitter and increase in base resistance at the overlap. For example, the depth of the external base layer 29 is 0.3 μm,
When the depth of the intrinsic base layer 31 is about 0.2 μm, the thickness of the oxide film sidewall 27 is optimally 0.2 to 0.25 μm.
However, in such a case, since the high-concentration external base layer 29 is very close to the emitter layer 32, the hFE and the cutoff frequency are reduced, and the base is also formed by the overlap between the external base layer 29 and the emitter layer 32. There has been a problem that it leads to an increase in the capacitance between the emitters and a decrease in reliability due to the hot carrier effect.

The present invention has been made to solve the above problems, and avoids punch-through leakage between a collector and an emitter and an increase in base resistance.
It is an object of the present invention to provide a semiconductor device in which a decrease in E or cutoff frequency and a decrease in reliability due to a hot carrier effect are suppressed.

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention has a structure in which an intrinsic base layer is surrounded between an external base layer and an intrinsic base layer, and the intrinsic base layer and the external base layer overlap with each other. According to a configuration in which a link base layer having a low impurity concentration is provided.

Effect of the Invention According to the present invention, a high-concentration external base layer can be removed from an emitter layer while avoiding punch-through leakage between a collector and an emitter and a large increase in base resistance by a link base that sufficiently overlaps both the intrinsic base layer and the external base layer. You can keep it away.

Embodiment FIGS. 1A to 1D are cross-sectional views showing an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1 (a), a P-type silicon substrate 1
After the N-type buried collector layer 2 is formed on the surface of the substrate, an N-type epitaxial layer 3 is grown. Next, element isolation LOCOS (Loc
After forming an Al Oxidation of Silicon (Si) film 4 on the surface of the N-type epitaxial layer 3, a base extraction electrode 5 made of P ⁺ polysilicon (first semiconductor film) and a CVD oxide film 6 are grown on the entire surface. Next, the CVD oxide film 6 and, subsequently, the base lead-out electrode 5 made of P ⁺ polysilicon are selectively etched away using a photoresist by photolithography as a mask to expose the intrinsic base region 7 on the surface of the N-type epitaxial layer 3. . And heat treatment at about 900-950 ° C
A P-type first impurity is introduced into the N-type epitaxial layer 3 from a base extraction electrode 5 made of P ⁺ polysilicon (first semiconductor film) to form a P-type link base layer 8.

Next, as shown in FIG. 1B, the side surfaces of the base extraction electrode 5 and the exposed surface of the intrinsic base region 7 are oxidized to form oxide films 9 and 10, respectively. The impurity concentration of the base extraction electrode 5 is much higher than that of the N-type epitaxial layer 3, and the oxide film 10 on the surface of the intrinsic base region 7 can be formed thinner than the oxide film 9 on the side surface of the base extraction electrode 5. In order to suppress diffusion of impurities in the base extraction electrode 5 into the N-type epitaxial layer 3 in this step, oxidation is performed at 800 to 850.
Perform at a low temperature of about ° C.

Next, as shown in FIG. 1C, the oxide film is left only on the side surface of the base extraction electrode 5 by anisotropic etching of the oxide film.
A side wall insulating film 11 and an emitter lead-out portion opening 12 are formed. Further, the P-type first impurity is again introduced into the N-type epitaxial layer 3 from the base extraction electrode 5 through the base extraction portion opening formed by the inner edge of the element isolation LOCOS film 4 and the outer edge of the sidewall insulating film from the base extraction electrode 5 by heat treatment at about 1000 ° C. Then, a P-type external base layer 13 having a higher concentration than the P-type link base layer 8 is formed. Here, the external base layer 13 is formed outside the emitter region by an amount corresponding to the oxidized side surface of the base extraction electrode 5, and a P-type link base layer 14 having a lower concentration than the P-type external base layer 13 is formed under the side wall insulating film 11. Will be left.

Finally, as shown in FIG. 1 (d), the polysilicon (second semiconductor film) grown on the entire surface is selectively etched away using a photoresist by photolithography as a mask, and an emitter composed of the second semiconductor film is formed. After the extraction electrode 15 is formed, a P-type impurity is ion-implanted into the emitter extraction electrode 15 made of the second semiconductor film, and P is implanted from the emitter extraction electrode 15 through the emitter extraction hole 12 by heat treatment.
A second type impurity is introduced to form a P-type intrinsic base layer 16. Further, an N-type impurity is ion-implanted into the emitter extraction electrode 15, and an N-type impurity is introduced from the emitter extraction electrode 15 through the emitter extraction portion opening 12 by heat treatment to form an N-type emitter layer 17.

For example, when the depth of the P-type external base layer 13 is 0.3 μm, the depth of the P-type intrinsic base layer 16 is about 0.2 μm, and the depth of the N-type emitter layer 17 is about 0.05 μm, P ^{+ serving as the} sidewall insulating film 11 is formed. The thickness of the oxide film 9 on the side surface of the base extraction electrode 5 made of polysilicon is formed to about 0.30 to 0.35 μm, and the link base layer 14 is formed.
By setting the depth to about 0.25 μm, a region of the P-type link base layer 14 having a lower concentration than the P-type external base layer 13 can be formed with a width of about 0.1 μm below the sidewall insulating film 11. .

Effects of the Invention As is clear from the above embodiments, according to the present invention, since the link base layer which sufficiently overlaps both the intrinsic base layer and the external base layer is provided, punch-through leakage between the collector and the emitter and large base resistance are caused. The high-concentration external base layer can be kept away from the emitter region while avoiding an increase, and the high-concentration external base layer is extremely close to the emitter region, which lowers the hFE and cutoff frequency, and further reduces the external base layer. It is possible to provide a semiconductor device in which an increase in base-emitter capacitance due to overlap between layers and emitter layers and a decrease in reliability due to a hot carrier effect are suppressed.

[Brief description of the drawings]

1 (a) to 1 (d) are process sectional views of a semiconductor device according to one embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are process sectional views of a conventional semiconductor device. 1 ... P-type silicon substrate (semiconductor substrate), 4 ... Element isolation LOCOS film (first insulating film), 5 ... Base lead electrode made of P ⁺ polysilicon (first semiconductor film), 6 ...
CVD oxide film (second insulating film), 7 ... intrinsic base region,
8, 14 link base layer, 11 side wall insulating film, 12 emitter opening portion opening, 13 external base layer, 15 (comprising second semiconductor film) emitter extraction electrode, 16 ... intrinsic base layer, 17 ... emitter layer.

Claims (2)

(57) [Claims] A first insulating film on the semiconductor substrate extending from an outer edge of an external base region surrounding an intrinsic base region formed on a surface portion of the semiconductor substrate to an outer edge of the surface of the semiconductor substrate; A base extraction electrode formed of a first semiconductor film extending from the external base region to the outer edge of the semiconductor substrate, and a second insulating film and sidewall insulation formed on the surface and side surfaces of the base extraction electrode An emitter extraction electrode formed of a second semiconductor film electrically separated from the external base region and the base extraction electrode by a film, and a base extraction portion opening formed by an inner edge portion of the first insulating film and the side wall; A semiconductor device comprising an outer edge portion of an insulating film, and an emitter layer formed by introducing impurities from the emitter extraction electrode through the emitter extraction portion opening. An inner wall of the base lead portion opening and an outer wall of the emitter lead portion opening are formed at an equal distance at any position around the emitter lead portion opening, and the base drawer electrode passes through the base lead portion opening. An external base layer formed by introducing a first impurity into the external base region, and formed by introducing a second impurity from the emitter extraction electrode to the intrinsic base region through the emitter extraction portion opening. And has an impurity concentration lower than that of the external base layer surrounding the intrinsic base layer between the external base layer and the intrinsic base layer and overlapping the intrinsic base layer and the external base layer. A semiconductor device having a link base layer formed by introducing a third impurity from the base extraction electrode through the base extraction portion opening; . 2. An intrinsic base region formed on a surface portion of a semiconductor substrate, an external base region surrounding the intrinsic base region, and a first portion on the semiconductor substrate extending from an outer edge of the external base region to an outer edge of the semiconductor substrate. Growing a first semiconductor film and subsequently a second insulating film over the entire surface of the insulating film, and following the second insulating film so that the intrinsic base region on the surface of the semiconductor substrate is exposed. Forming a base extraction electrode by selectively etching away the first semiconductor film, and forming a link base layer by introducing a first impurity from the base extraction electrode to the external base region; An emitter extraction electrode formed on a side surface of the base extraction electrode by oxidation of a side surface of the base extraction electrode and a surface of the intrinsic base region and subsequent anisotropic etching of an oxide film; Forming an oxide film for electrical isolation and an emitter lead-out opening formed by an inner edge of the oxide film; and forming an opening on the inner edge of the first insulating film and a side surface of the base lead electrode from the base lead electrode. An external base layer having a higher impurity concentration than the link base layer by introducing the first impurity again into the external base region through a base lead-out portion opening formed by an outer edge of the formed sidewall insulating film made of the oxide film. Forming a second semiconductor film on the intrinsic base region and the base lead-out electrode via the second insulating film and the sidewall insulating film to form the emitter lead-out electrode, Introducing a second impurity from the emitter extraction electrode through the emitter extraction portion opening to the intrinsic base region to form an intrinsic base layer. Method of manufacturing a conductor arrangement.