JP2002026029A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device superior in high speed performance and its manufacturing method. SOLUTION: The manufacturing method comprises a step for forming single crystal silicon oxide island regions 13a and a surrounding oxide film 13b on an SOI substrate, a step for forming an oxide film 14 on island regions 13c, a step for laminating a second polycrystalline silicon layer 17 thereon, a step for covering this layer with a first insulation layer 20, etching it, selectively doping to form n-type collector parts 19, 29, a step for forming trenches reaching the island regions 13a, forming side walls 21a, 21b, a step for implanting ions therefrom to diffuse an n-type impurity, thereby forming emitter parts 15b, 27, forming oxide side walls 23a, 23b, implanting a p-type impurity to form base regions 28, filling base electrodes 24 in the trenches, laminating a second insulation layer, opening contact holes 26, and filling a wiring material therein.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, bipolar type LSIs are more advantageous than MOS type LSIs in terms of high speed performance. In recent years, MOS type LSIs have been greatly improved in high speed performance as design rules become finer. 50 GHz
MOS type LSIs having the above cutoff frequencies have also appeared. For example, a CMOS-LS having a gate length of 0.2 μm or less
It is said that I is more than a bipolar LSI in high-speed performance.

However, a bipolar LSI is superior in principle with respect to driving capability for a load, that is, a mutual conductance (gm). Therefore, a bipolar type LSI is not used in an ideal ring oscillator having an extremely small resistance and capacitance load. However, in the case of a general system LSI that is subject to a considerable load including internal and external factors, the bipolar LSI is still more advantageous than the MOS LSI in high-speed performance. Therefore, it is necessary to further improve the high-speed performance of a bipolar LSI useful as a high-speed device in the future.

Heretofore, the speeding up of the bipolar type LSI has been mainly advanced by two approaches.
The first approach is to speed up the current amplification function (bipolar action), which is the basic performance of a transistor, or to shorten the signal delay in its active region. The first approach is mainly promoted by shortening the base width to increase the cutoff frequency, that is, by improving the figure of merit (fT). (Shortening).

[0005] The second approach is to thoroughly remove the inactive portion inside the transistor, which has been promoted by miniaturization of design rules and application of self-alignment technology. not enough. Here, paying attention to the single crystal region inside the vertical transistor, it is understood that the active region directly involved in the transistor operation is less than 10%, that is, the unnecessary region occupies most. This is a factor that reduces the speed of the transistor.

[0006] Therefore, even if it is the most advanced vertical transistor at present, most of the transistor is composed of the active region, and the ideal region of the transistor in which the inactive region which is a parasitic and causes a speed reduction is thoroughly reduced. It is far from structure.

However, in recent years, there have been reported R & D results on a horizontal bipolar transistor formed on an SOI substrate and a method of manufacturing the same, which are breakthrough techniques for approaching the ideal structure. .

Hereinafter, three examples of the results of the research and development will be described.

A first example is a lateral bipolar transistor on an SOI substrate also having a CMOS structure, which is described in Japanese Patent Application Laid-Open No. Hei 9-149771. As shown in FIG. From the end, the single crystal region 100 has a contrasting conduction type structure of N ⁺ , N, P, N, N ⁺ , and an ideal structure having no inactive portions in all PN junction regions. I have.

A second example is a Bi-CMOS described in Japanese Patent Application Laid-Open No. 6-244365, in which a lateral bipolar transistor 102 is formed on an SOI substrate 101, as shown in FIG. As in the first example, P
The structure has no inactive portion in the N junction region. Further, in the first example, since the base width is formed using a resist pattern also serving as gate etching as a mask, the second example is different from the first example in which the reduction of the base width strongly depends on the design rule. In the above example, the base width is determined by the self-alignment technique based on the sidewall formation of the insulating film. Therefore, the base width can be controlled by the thickness of the sidewall, which is difficult to achieve with the current exposure technology. It can be 0.1 μm or less. Furthermore, since the impurity profiles on the emitter side and collector side centering on the base can be controlled independently, it is possible to reduce the base-collector junction capacitance that reduces the speed performance while having a sufficient current amplification factor. Can and
Large CE withstand voltage characteristics can be obtained.

A third example is a horizontal bipolar transistor on an SOI substrate 203 described in Japanese Patent Application Laid-Open No. Hei 5-21446. As shown in FIG.
Although it does not have the OS structure, it does have the mellit of the second example. Further, since the connection between the intrinsic base 204 and the polysilicon composed of the external base 205 is made directly above the intrinsic base 204, the base resistance can be extremely reduced as compared with the second example. Further, even if the emitter length is increased, the base resistance does not increase.

As described above, by forming a lateral bipolar transistor on an SOI substrate, a junction capacitance can be reduced, and a transistor mainly composed of an active region can be obtained.

[0013]

However, in the above-described conventional semiconductor device and the method of manufacturing the same, the merit of the "transistor consisting mostly of active region" has not been fully exploited.

As a general index indicating the high-speed performance of a transistor, fmax, which is a frequency at which the power gain of the transistor is 1, is generally used. The fmax is represented as follows by the sub-parameter of the transistor.

Fmax∝ {fTmax / (8π × Rb × Cbc)} (1) where fTmax is a maximum cutoff frequency, Rb is a base resistance, and Cbc is a base-collector capacitance.

From the above equation (1), it is clear that it is necessary to increase fTmax and reduce Rb and Cbc in order to improve the high-speed performance of the transistor.
It should be noted that even if some parameters in the above equation (1) are improved, if the other parameters are further deteriorated, the high-speed performance of the transistor will not be improved.

From this viewpoint, in the first example, the fTmax is low because the base width is wide, the Rb is high due to the structural characteristics resulting from the method of extracting the base electrode, and the Rb depends on the emitter length. Have the problem that Next, in the second example, although the base width is narrow, the method of extracting the base electrode is the same as in the first example.
And high speed performance has not been improved overall. Lastly, in the third example, although there is no problem as in the first and second examples, a long path and a large-area polysilicon wiring are used in order to draw out the intrinsic base to the outside. The polysilicon wiring forms a parasitic capacitance via the collector portion and the insulating film. Although the area of the parasitic capacitance occupies most of the area of the transistor, the parasitic capacitance cannot be reduced due to a margin for alignment in an exposure process, a design rule, and the like. However, the total capacitance between the base and the collector cannot be reduced.

The present invention eliminates the above-mentioned problems, and not only optimizes the active single crystal region, but also provides a three-dimensional structure including the interaction of the region from which various electrodes are extracted with the single crystal region. An object of the present invention is to provide a semiconductor device excellent in high-speed performance and a method for manufacturing the same by performing optimization as a geometric structure.

[0019]

According to the present invention, there is provided a semiconductor device comprising: an SOI substrate;
A first layer including an island region of single crystal silicon formed on the substrate and having an emitter region, a base region, and a collector region formed thereon; and a first layer stacked on the first layer and in contact with the emitter region as an electrode. A second island including a first island region of polycrystalline silicon functioning and a second island region of polycrystalline silicon contacting the collector region and functioning as an electrode;
A first insulating layer laminated on the second layer, a second insulating layer laminated on the first insulating layer, and a wiring material filled therein; 1st and 2nd which penetrate the 2nd insulating layer and reach said 1st and 2nd island region.
A groove having an insulating film formed on an inner wall thereof, penetrating the first insulating layer and the first island region of the second layer, and reaching the island region of the first layer; A base electrode having one end in contact with the base region and the other end laminated on a part of the first insulating layer, and a wiring material filled therein, and the second insulating layer And a third hole that penetrates through and reaches the base electrode.

[2] In the method of manufacturing a semiconductor device, S
A first region including an island region of single crystal silicon on which an emitter region, a base region, and a collector region are formed on an OI substrate;
A first island-like region of polycrystalline silicon, which functions as an electrode in contact with the emitter region, and a polycrystalline silicon, which functions as an electrode in contact with the collector region, on the first layer A second layer including a second island-shaped region is stacked, a first insulating layer is stacked on the second layer,
Forming a groove that penetrates through the insulating layer and the first island region of the second layer to reach the island region of the first layer; forms an insulating film on the inner wall of the groove; Impurities are diffused from the island region to form an emitter region in the adjacent island region of the first layer, and the impurity is implanted into the first insulating layer and the inner wall of the groove using an insulating film as a mask. Forming a base region adjacent to the emitter region in the island region of the first layer, filling a base electrode in the groove having the inner wall, and forming a second insulating layer on the first insulating layer; The first and second holes penetrating the first and second insulating layers to reach the first and second island regions, and the second insulating layer penetrating the second insulating layer. A third hole reaching the base electrode is formed, and the first, second, and third holes are filled with a wiring material.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device showing a first embodiment of the present invention in a manufacturing process (part 1), and FIG. 2 is a sectional view of a semiconductor device showing a first embodiment of the present invention in a manufacturing process. (Part 2).

In this embodiment, a lateral bipolar transistor is manufactured.

First, as shown in FIG.
X (Separation by Implanted
SOI (Silico) formed by Oxygen)
A non-insulator substrate is prepared. Here, the silicon oxide film 12 on the silicon substrate 11 has a thickness of about 1000.
Has a phosphorus concentration of about 1 × 10 ¹⁵ / cm ³ and a thickness of about 10
00 °.

Next, as shown in FIG. 1 (b), the single crystal silicon layer 13 is selectively oxidized to separate elements to form an island region 13a and an oxide film 13b around the island region 13a. The thickness 1 is formed on the single crystal silicon island region 13a.
An insulating film 14 made of a silicon thermal oxide film having a thickness of about 00 ° is formed, a polycrystalline silicon layer 15 not doped is formed to a thickness of about 1000 °, and a silicon nitride film 16 is formed to a thickness of about 1000 °.

Next, the silicon nitride film 16 is partially removed by etching using a photolithography technique,
Further, after the exposed polysilicon layer 15 is etched by about 500 °, it is selectively oxidized to form thermal oxide films 17a and 17b, thereby forming island-like polysilicon region 15a. Thereafter, the remaining silicon nitride film 16 is entirely removed with phosphoric acid, and then a new silicon nitride film 18 is formed to a thickness of about 1000 ° on the entire surface as shown in FIG.

Next, as shown in FIG. 1D, an opening is formed by partially removing the silicon nitride film 18 and the thermal oxide film 17b by anisotropic etching using a photolithography technique. A part of the region 13a is exposed to a width of about 0.4 μm.

Next, a polycrystalline silicon layer having a thickness of 50
After forming about 00 °, etching back is performed to obtain FIG.
As shown in (e), the polysilicon layer 19 is left only in the opening, and the silicon nitride film 1 is
8 is exposed. Further, phosphorus is ion-implanted into the polycrystalline silicon layer 19 at a dose condition of about 2 × 10 ¹⁶ ions / cm ² , and then annealed at 850 ° C. for about 30 minutes in a nitrogen atmosphere to convert the phosphorus made of single crystal silicon. The collector 29 is formed as an N-type region by diffusing it into a part of the island region 13a.

Next, 1% was added to a 5% HF (hydrogen fluoride) solution.
After dipping for about a minute to remove the oxide layer on the surface,
All the nitride film on the surface is removed by hot phosphoric acid, and a new silicon nitride film 20 is formed to a thickness of about 1000 ° on the entire surface. The silicon nitride film 20 and the polycrystalline silicon region 1 are provided in a range where the island region 13a and the island polycrystalline silicon region 15a overlap.
5a is partially removed by anisotropic etching by photolithography to form a groove having a width of about 0.3 μm as shown in FIG. 1 (f), and the polycrystalline silicon region 15a is divided into two regions. 15b and 15c. Here, the insulating film 14 is left by adjusting the etching selectivity.

Next, after a new silicon nitride film is formed on the entire surface including the silicon nitride film 20, the new silicon nitride film is etched back by anisotropic etching, as shown in FIG. Thus, only the sidewalls 21a and 21b covering the side surfaces of the groove formed in the silicon nitride film 20 and the polycrystalline silicon region 15a are left. After that, by photolithography technology,
A portion other than the polycrystalline silicon region 15b is masked with a resist. And 150 keV, 3 × 10 ¹⁶ io
Phosphorus is ion-implanted into the polycrystalline silicon region 15b through the silicon nitride film 20 under a dose condition of about ns / cm ^{2 and then} annealed at 800 ° C. for about 30 minutes.

Next, when the insulating film 14 exposed at the bottom of the groove is removed by side-etching by dipping in an HF solution, as shown in FIG.
A void 22 is formed over about 00 °. Then, in a high-purity hydrogen gas atmosphere, silicon is selectively grown to a thickness of about 100 ° in the gap 22 with SiH ₂ Cl ₂ as a source gas and HCl added. Then, single-crystal silicon grows epitaxially from the island region 13a, and polycrystalline silicon grows from the polycrystalline silicon regions 15b and 15c, and the voids 22 are completely filled.

Next, RTA (Rapid Thermo)
l Annealing) method at 1000 ° C.
Annealing is performed for about 0 seconds to diffuse N ⁺ from the polycrystalline silicon region 15b to a part of the island region 13a, thereby forming the emitter 27 as an N type region in the island region 13a.
Then, after a silicon oxide film is formed on the entire surface to a thickness of about 1000 ° by a method such as CVD, the oxide film is etched back, and as shown in FIG. 2C, sidewalls 21a, Only the additional sidewalls 23a and 23b on the upper portion 21b are left. Here, the width of the groove between the sidewalls 23a and 23b is 50.
It is about 0 °. Further, using the sidewalls 23a and 23b as a mask, 30 keV, 5 × 10 ¹³ ion is applied to the island-shaped region 13a exposed at the bottom of the groove.
Boron (B) ions are implanted under a dose condition of about s / cm ² to form a base 28 which is a P-type region.

Next, after forming a polycrystalline silicon layer doped with boron at 1 × 10 ²⁰ / cm ³ or more over the entire surface, the polycrystalline silicon layer is partially removed by etching using a photolithography technique, as shown in FIG. Thus, the base electrode 24 is formed.

Next, after a silicon oxide film 25 is formed on the entire surface by a method such as CVD, a 100
Anneal at 0 ° C. for about 20 seconds to redistribute and activate the diffusion layer. Finally, contact holes for the emitter 27, the base 28, and the collector 29 are formed in the oxide film 25 and the silicon nitride film 20 by etching using a photolithography technique, and a metal such as TiN or W is formed in the contact holes. To form metal wirings 26 for the emitter 27, the base 28, and the collector 29, respectively.

Thus, a lateral bipolar transistor as shown in FIG. 2E is obtained.

In the bipolar transistor, the polycrystalline silicon region 15b contains the same N-type dopant (impurity) as the emitter 27, functions as an emitter electrode for conducting the emitter 27 and the metal wiring 26, and the polycrystalline silicon layer 19 , The collector 29 has the same N-type dopant, and functions as a collector electrode for conducting the collector 29 and the metal wiring 26. The base electrode 24 contains the same P-type dopant as the base 28, and has the base 28 and the metal wiring 26. And are conducted.

In the present embodiment, since the lateral bipolar transistor is manufactured as described above, the following effects are obtained.

(1) Since the base 28 and the emitter-base junction are formed in a self-alignment manner by the self-alignment technique, the base 28 and the emitter 27 can be formed with high positional accuracy and high reproducibility, and are stable. A transistor having a current amplification factor can be manufactured. Further, the position of the emitter-base junction can be freely controlled.

(2) Until the end of the process, the polysilicon region 15b and the island region 13a made of single crystal silicon are separated by the insulating film 14, and N
⁺ Diffusion is blocked. Therefore, since the thermal budget is extremely small, the increase can be suppressed by the thermal diffusion of the width of the base 28, so that the high-speed performance of the transistor does not deteriorate. Until immediately before the base 28 is formed, the emitter 2 in the island region 13a is
Since the diffusion of N ⁺ into the portion 7 is suppressed, the impurity concentration profile of the emitter-base junction becomes ideal, and a sufficient current amplification factor can be obtained.

(3) The base 28 is formed in a self-aligned manner by using the sidewalls 23a and 23b as masks by the self-alignment technique, so that the width of the base 28 can be freely controlled to be less than the design rule. The cutoff frequency can be made the same level as that of the vertical bipolar transistor. Further, since the distance between the sidewalls 23a and 23b is determined by the resist pattern, a plurality of types of transistors having different widths of the base 28 can be easily formed in the same chip only by changing the resist pattern. Therefore, the maximum cutoff frequency fTmax, the base resistance Rb, and Vbe (base
Since a plurality of types of transistors having different emitter-to-emitter voltages can be easily designed, design flexibility is high.

(4) Since the base electrode 24 is drawn out from just above the base 28, the base resistance Rb as an input impedance including a general parasitic portion should be suppressed to about twice the value generally called a physical limit. Can be. In addition, the routing portion of the base electrode 24 and the collector 2
9 can be made extremely small. Therefore, the base resistance Rb and the base-collector capacitance Cbc, which are important factors for improving the high-speed performance of the transistor, can be suppressed to an extremely low level.
Since the structures of the extraction electrodes 8 and the collector 29 can be made ideal, it is possible to provide a horizontal bipolar transistor having high speed performance.

(5) A structure in which the emitter 27 side and the collector 29 side have an asymmetrical profile with respect to the base 28, for example, the emitter 28 is n = 10 ²⁰ / cm ³
Since the level, the base 28 can be at the p = 10 ¹⁸ / cm ³ level, and the collector 29 can be at the n = 10 ¹⁶ / cm ³ level, a transistor having a sufficient amplification factor and withstand voltage can be provided. Further, the emitter 27, the base 28 and the collector 2
Since the interval 9 can be changed only by changing the resist pattern, a plurality of types of transistors having different breakdown voltage characteristics and different speed performances can be easily formed in the same chip.

The lateral bipolar transistor manufactured by the manufacturing method of the present embodiment has the following structural features, and therefore has excellent high-speed performance and low power consumption.

(1) Since the junction capacitance of a transistor is determined substantially by the junction capacitance of the active region, it is extremely small.

(2) Since the base electrode 24 is drawn out from just above the base 28, the external base resistance is negligibly small.

(3) Since the emitter electrode and the collector electrode are located outside, EM (Electro-migrate)
(ion), the reduction in wiring life is small, the element size can be reduced, and the transistor can be miniaturized.

(4) The parasitic capacitance between the routing portion of the base electrode 24 and the collector 29 is extremely small.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

The present embodiment has the same steps as the steps in the first embodiment, and the description thereof will be omitted. Also, components having the same configuration as in the first embodiment are given the same reference numerals, and description thereof is omitted.

FIG. 3 is the same as FIG. 2 (e).

The manufacturing method according to this embodiment is similar to that shown in FIG.
In the step shown in FIG. 3B, after forming an undoped polycrystalline silicon layer 15 to a thickness of about 1000 °, a W (tungsten) silicide film 30 having a thickness of 10
The difference from the first embodiment lies only in the point formed at about 0 °. Other than that, the lateral bipolar transistor is manufactured by the same steps as those of the first embodiment.

The lateral bipolar transistor according to the present embodiment manufactured as described above has a W silicide film 30 on polycrystalline silicon regions 15b and 15c, as shown in FIG.

The bipolar transistor of the present embodiment has the following effects in addition to the effects of the first embodiment.

That is, the bipolar transistor according to the first embodiment has a high emitter resistance because the distance of the polysilicon region 15b between the emitter 27 and the metal wiring 26 is long, whereas the bipolar transistor according to the present embodiment has a high emitter resistance. The bipolar transistor is connected to the polysilicon region 15.
Since the W silicide film 30 having a low electric resistance is provided on b, the emitter resistance is low and the current amplification factor is high.

Next, a third embodiment of the present invention will be described in detail with reference to FIG. Note that this embodiment is different from the first embodiment in FIGS.
Since the same steps as those shown in FIG. 2 (f) and FIGS. 2 (c) to 2 (e) are included, description thereof will be omitted. Also, components having the same configuration as in the first embodiment are given the same reference numerals, and description thereof is omitted.

FIG. 4 is a sectional view of a semiconductor device showing a second embodiment of the present invention in a manufacturing process.

The step shown in FIG. 4A is the same as that shown in FIG. That is, a new silicon nitride film
After forming the entire surface including the silicon nitride film 20, this new silicon nitride film was etched back by anisotropic etching to form the new silicon nitride film on the silicon nitride film 20 and the polycrystalline silicon region 15a as shown in the figure. Only the sidewalls 21a and 21b that cover the side surfaces of the groove are left. Thereafter, portions other than the polycrystalline silicon region 15b are masked with a resist by photolithography. And 150 keV, 3 × 10 ¹⁶ ions / cm
^Under a dose condition of about ² , phosphorus ions (P ⁺ ) are passed through the silicon nitride film 20 through the polycrystalline silicon region 15.
Then, annealing is performed at 800 ° C. for about 30 minutes.

Next, the insulating film 14 exposed at the bottom of the groove is removed by side-etching by dipping in an HF solution, and a void is formed in the lateral direction by about 2000 °. Then, as shown in FIG. 4B, when an undoped polycrystalline silicon film 31 having a thickness of about 100 ° is formed on the entire surface, the voids are completely filled with the undoped polycrystalline silicon film 31. .

Next, the polysilicon film 31 is dipped in a potassium hydroxide solution and removed by etching. As shown in FIG. 4C, only the polysilicon film 31 in the gap is removed. So that it remains. At this time, since the <111> crystal plane is exposed in the island region 13a made of single crystal silicon, the island region 13a is hardly etched by the potassium hydroxide solution. If the exposed surface of the island-shaped region 13a is a <100> crystal surface, the surface is etched by a potassium hydroxide solution, and
A groove is formed.

Thereafter, FIGS. 2 (c) to 2 (e)
A horizontal bipolar transistor is manufactured by the same steps as those shown in FIG.

The present embodiment has the following effects in addition to the effects of the first embodiment.

That is, in the second embodiment, all the voids obtained by removing the insulating film 14 by side etching are filled with the undoped polycrystalline silicon film 31. For this reason, in the first embodiment, monocrystalline silicon and polycrystalline silicon are selectively grown to fill the voids. In order to obtain a sufficient growth rate, it was necessary to perform heat treatment at a high temperature of about 800 ° C. in a hydrogen atmosphere, whereas in the second embodiment, heat treatment was performed at a high temperature. It is not necessary to perform the heat treatment, and the heat treatment may be performed at a relatively low temperature of about 600 ° C. in order to grow the polycrystalline silicon film 31.
Therefore, thermal diffusion of impurities in silicon can be suppressed, so that a transistor having a high cutoff frequency fT can be provided.

Next, a fourth embodiment of the present invention will be described in detail with reference to FIG. Note that this embodiment includes the same steps as the steps in the first embodiment, and thus the description thereof is omitted. Also, components having the same configuration as in the first embodiment are given the same reference numerals and description thereof is omitted.

FIG. 5 (a) is the same as FIG. 2 (e),
FIG. 5B is an enlarged view of a main part of FIG.

In this embodiment, the insulating film 14 is not a thermal oxide film of silicon as in the first embodiment, but has a three-layered structure as shown in FIG. 5B. Here, the lower layer 14a is a 30 ° thick silicon oxide film formed by CVD, the intermediate layer 14b is a 30 ° thick silicon nitride film, and the upper layer 14c is a 50 ° thick silicon oxide film formed by CVD.

The process of this embodiment is different from that of the first embodiment only in the step of removing the insulating film 14 exposed at the bottom of the groove by side etching.

That is, when the insulating film 14 is removed by side-etching to form a gap of about 2000 ° in the lateral direction, first, the upper layer 1 is dipped in an HF solution.
4c, the intermediate layer 14b is side-etched with hot phosphoric acid, and finally, the lower layer 14a is side-etched with a 0.3% HF solution for about 1 minute.

The other steps are the same as those in the first embodiment to manufacture a lateral bipolar transistor.

This embodiment has the following effects in addition to the effects of the first embodiment.

That is, in the fourth embodiment,
The insulating film 14 has a three-layer structure. Therefore, the first
In the first embodiment, when the single-layer insulating layer 14 made of a silicon thermal oxide film is side-etched, the end of the insulating film 14 may seep into the end and gouge. In contrast, in the present embodiment, the end of the insulating film 14 is not digged.

Next, a fifth embodiment of the present invention will be described in detail with reference to FIG. Note that this embodiment is different from the first embodiment in FIGS.
(D) and the same steps as those shown in FIGS. 2 (c) to 2 (e), and the description thereof is omitted. Also, components having the same configuration as in the first embodiment are given the same reference numerals, and description thereof is omitted.

FIG. 6 is a sectional view showing a semiconductor device manufacturing process according to a fifth embodiment of the present invention.

In the present embodiment, the manufacturing method
1A to 1E have the same steps as those shown in FIGS. 1A to 1E, and those shown in FIG. 6A and those shown in FIG. 6 (a), the thickness of the insulating film 14, which is a silicon thermal oxide film, is about 5 to 50 °, and the silicon film having a thickness of about 200 ° is formed on the insulating layer 14. Nitride film 3
1 (e), the thickness of the insulating film 14 is about 100.degree. And the only difference is that the silicon nitride film 32 is not formed. ing.

Next, after removing the nitride film 18 on the surface with phosphoric acid, a silicon oxide film 33 is formed on the entire surface by CVD at a thickness of about 1000 °. And the island-shaped region 1
The silicon oxide film 33 and the polycrystalline silicon region 15a are partially removed by anisotropic etching using photolithography technology in a range where 3a and the island-shaped polycrystalline silicon region 15a overlap each other. 6
As shown in (b), a groove having a width of about 0.3 μm is formed,
The polycrystalline silicon region 15a is divided into two regions 15b, 1
5c. Here, the silicon nitride film 32 is
It is left by adjusting the etching selectivity.

Next, a silicon oxide film is formed on the entire surface by CVD or by thermally oxidizing the silicon oxide film 33 to increase the volume, and then the silicon oxide film is anisotropically etched. The silicon oxide film 33 is etched back as shown in FIG.
And, only the side walls 34a and 34b that cover the side surfaces of the groove formed in the polycrystalline silicon region 15a are left. After that, a portion other than the polycrystalline silicon region 15a including the regions 15b and 15c and the groove is masked with a resist by a photolithography technique. And
Phosphorus ions (P ⁺ ) are added to the silicon oxide film 33 at a dose of about 70 keV and about 3 × 10 ¹⁶ ions / cm ^2.
And then implanted into the polycrystalline silicon region 15a, followed by annealing at 800 ° C. for about 30 minutes.

Then, the silicon nitride film 32 is dipped in a hot phosphoric acid solution to remove the silicon nitride film 32 by side etching about 2000 ° in the lateral direction. When a certain insulating film 14 is removed by side etching in the same manner, 2,000 mm
To some extent, voids form. Then, in a high-purity hydrogen gas atmosphere, SiH ₂ Cl ₂ is used as a source gas, and HC
1 with silicon added to the gap to a thickness of 3
Selectively grow about 00 °. Then, single-crystal silicon grows epitaxially from the island-like region 13a, and polycrystalline silicon grows from the polycrystalline silicon regions 15b and 15c. As shown in FIG. 6D, all the voids are filled.

Next, 3 times at 1000 ° C. by the RTA method.
Anneal for about 0 seconds to make the polycrystalline silicon region 15
b, 15c, N ⁺ is diffused into a part of the island-shaped region 13a, so that the emitter 27, which is an N-type region, is
Form within. Then, after a silicon oxide film is formed on the entire surface to a thickness of about 1000 ° by a method such as CVD or the like, the oxide film is etched back, and as shown in FIG. Only the further sidewalls 23a and 23b on the upper side of 34b are left. Here, the width of the groove between the sidewalls 23a and 23b is about 500 °. Further, using the sidewalls 23a and 23b as a mask, 40 keV, 5 keV is applied to the island-shaped region 13a exposed at the bottom of the groove.
Boron ions (B ⁺ ) are implanted under a dose condition of about × 10 ¹⁵ ions / cm ² to form a base 28 which is a P-type region.

Thereafter, FIGS. 2 (d) to 2 (e)
A horizontal bipolar transistor is manufactured by the same steps as those shown in FIG.

This embodiment has the following effects in addition to the effects of the first embodiment.

That is, in the fifth embodiment,
A silicon nitride film 32 is formed on the very thin insulating film. For this reason, in the first embodiment, when the single-layer insulating layer 14 is side-etched, the HF solution may permeate into the end of the insulating film 14 and the end may go away. On the other hand, in the present embodiment, the end of the insulating film 14 does not gouge, although the configuration is simple.

An oxide film for forming the sidewalls 34a and 34b is thermally oxidized to form a silicon oxide film 33.
When the volume is increased, the manufacturing process is simplified.

Next, a sixth embodiment of the present invention will be described in detail with reference to FIG. Note that, in the present embodiment, the manufacturing method has the same steps as those in the first embodiment, and a description thereof will be omitted.
Also, components having the same configuration as in the first embodiment are given the same reference numerals, and description thereof is omitted.

FIG. 7A is a plan view schematically showing the arrangement of the lateral emitter, base and collector of the semiconductor device according to the first embodiment. FIG. 7B is a plan view showing the sixth embodiment. FIG. 3 is a plan view schematically showing an arrangement of an emitter, a base, and a collector of the semiconductor device.

FIG. 7A schematically shows the arrangement of the emitter 27, the base 28 and the collector 29 when the lateral bipolar transistor as the semiconductor device according to the first embodiment is viewed from above in the drawing. It is shown.
Here, the emitter 27, the base 28, and the collector 29
Are each rectangular and are arranged in parallel at an interval from each other.

On the other hand, in the lateral bipolar transistor according to the present embodiment, as shown in FIG. 7B, the emitter 27, the base 28 and the collector 29 each have a ring shape, that is, an annular shape. And are spaced apart from each other so as to be substantially concentric. The shape of the emitter 27, the base 28 and the collector 29 is not limited to an annular shape, but may be, for example, an elliptical shape or a polygonal shape as long as it forms a closed loop.

The present embodiment has the following effects in addition to the effects of the first embodiment.

That is, in the first embodiment,
When the insulating layer 14 is side-etched, the HF solution may seep into the portion corresponding to the ends 28a and 28b of the base of the insulating film 14 and go through.
In the lateral bipolar transistor according to the present embodiment, the shape of the base 28 is a closed loop,
Since the shape has no edge, the insulating film 14 does not penetrate into the insulating film 14 and go through.

Next, a seventh embodiment of the present invention will be described in detail with reference to FIGS.

Since the present embodiment has the same steps as those in the first embodiment, the description of the same steps will be omitted. Also, components having the same configuration as in the first embodiment are given the same reference numerals, and description thereof is omitted.

FIGS. 8 (a-1-1) to 9 (a-5-1)
10 is a diagram showing a process for manufacturing an NPN transistor in this embodiment, and FIGS. 8A to 9A to 9A and FIGS. FIG. 12 shows a step of manufacturing a PNP transistor, and FIG.
FIG. 13 shows a configuration of an nMOS transistor, and FIG.
FIG. 3 is a diagram illustrating a configuration of an OS transistor. FIG.
(A-1-1) to FIG. 9 (a-5-1) and FIG. 10 and FIG. 8 (a-1-2) to FIG. 9 (a-5-2) and FIG.
1 to 3 in the first embodiment show corresponding steps, respectively.

In the present embodiment, in order to manufacture a complementary transistor, N
A PN transistor and a PNP transistor are manufactured simultaneously. FIGS. 8 (a-1-1) to 9 (a-5-1) and FIG. 10 show a region where an NPN transistor is manufactured, that is, an NPN region. a-
5-2) and FIG. 11 show a region where a PNP transistor is manufactured, that is, a PNP region.

In the present embodiment, FIG.
1) and the steps shown in FIG.
And the description is omitted.

Next, FIGS. 8 (a-2-1) and 8 (a-
As shown in 2-2), the single-crystal silicon layer 13 is selectively oxidized, the elements are separated, and the island-shaped regions 13n and 13p and the oxide film 13b around the islands are formed. A portion other than the region is masked with a resist. And 30 keV, 5 × 10 ¹¹ ions
After ion implantation of boron into the PNP region under a dose condition of about / cm ^2, annealing is performed at 1000 ° C. for about 30 minutes to diffuse boron all over the island-like region 13p.
^- to the region. Thereafter, similarly to the step shown in FIG. 1B, the insulating film 14 made of a thermal oxide film and the polycrystalline silicon layer 1 are formed.
5 and a silicon nitride film 16 are formed.

Next, FIGS. 8 (a-3-1) to 8 (a-4)
-1) and the steps shown in FIG. 8 (a-3-2) to FIG. 8 (a-4-2) are the same as the steps shown in FIG. 1 (c) to FIG. .

Next, FIG. 8 (a-5-1) and FIG.
In 5-2), the polycrystalline silicon layers 19n and 19p are formed only in the openings in the same manner as in the step shown in FIG.
The silicon nitride film 18 is left in other portions. Then, a portion other than the NPN region is masked with a resist by a photolithography technique, and phosphorus is added to 2 × 10 ¹⁶ io.
Under a dose condition of about ns / cm ² , the polycrystalline silicon layer 1
9n is ion-implanted. In the same manner, boron is changed to 3
Ions are implanted into the polycrystalline silicon layer 19p under a dose condition of about × 10 ¹⁶ ions / cm ² . Then 850 ° C
For about 30 minutes to form a polycrystalline silicon layer 19n, 1
Phosphorus and boron implanted into 9p are diffused into a part of the island region 13a made of single crystal silicon, and FIG.
1) and as shown in FIG. 8 (a-5-2), a collector 29n that is an N-type region and a collector 2 that is a P-type region
9p is formed.

Next, FIG. 9 (a-1-1) and FIG.
The process shown in 1-2) is the same as the process shown in FIG.

Next, FIGS. 9 (a-2-1) and 9 (a-
The step shown in 2-2) is the same as the step shown in FIG. 2A, and the silicon nitride film 20 and the polycrystalline silicon region 15 are formed.
side wall 21a that covers the side surface of the groove formed in a.
21b is formed. Then, after a portion of the NPN region other than the polycrystalline silicon region 15b is masked with a resist by a photolithography technique, 60 keV, 3 × 10
Boron, NP at a dose condition of about ¹⁶ ions / cm ²
The silicon nitride film 2 is formed on the polycrystalline silicon region 15b in the N region.
0 is implanted. Similarly, 15
Phosphorus is ion-implanted into the polycrystalline silicon region 15b in the PNP region under a dose condition of about 0 keV and about 2 × 10 ¹⁶ ions / cm ² . Thereafter, annealing is performed at 800 ° C. for about 30 minutes.

Next, FIG. 9 (a-3-1) and FIG.
The step shown in 3-2) is the same as the step shown in FIG.

Next, FIGS. 9 (a-4-1) and 9 (a-
In the step shown in 4-2), as in the step shown in FIG. 2C, N ⁺ and P ⁺ are diffused from the polycrystalline silicon region 15b to a part of the island regions 13n and 13p to form an N-type. Emitter 27n as a region and emitter 27 as a p-type region
Form p. 9 (a-4-1) and 9 (a-4-4) in the same manner as in the step shown in FIG.
As shown in 2), the sidewalls 23a and 23b are formed on the sidewalls 21a and 21b. afterwards,
After a portion other than the NPN region is masked with a resist by a photolithography technique, the sidewall 23 is removed.
Using a and 23b as masks, 30 keV, 5 × 10 ¹³ ions /
boron ions are implanted in cm ^2, a dose conditions, P
A base 28p as a mold region is formed. Similarly, after a portion other than the PNP region is masked with a resist, 120 keV, 3 × 10 ¹³ io is applied to the island region 13p.
Phosphorus is ion-implanted under a dose condition of about ns / cm ² to form a base 28n which is an N-type region.

Next, after an undoped polycrystalline silicon layer is formed on the entire surface, a portion other than the NPN region is masked with a resist by a photolithography technique. ¹⁶ ion
Boron is ion-implanted under a dose condition of about s / cm ² . Similarly, portions other than the PNP region are masked with a resist, and 50 keV, 3 × 10 ¹⁶ i
Phosphorus ions are implanted under a dose condition of about ons / cm ² . Thereafter, the polycrystalline silicon layer is partially removed by etching using photolithography technology, and FIG.
(A-5-1) and FIG. 9 (a-5-2),
Base electrodes 24p and 24n are formed, and 800
Anneal at 30 ° C. for about 30 minutes to diffuse the impurities in the base electrodes 24p and 24n.

The subsequent steps are the same as those shown in FIG. 3, as shown in FIG. Note that FIG.
Indicates a PNP transistor.

Thus, an NPN transistor and a PNP transistor can be obtained.

This embodiment has the following effects in addition to the effects of the first embodiment.

That is, in the present embodiment, a lateral complementary bipolar transistor can be obtained by simultaneously manufacturing an NPN transistor and a PNP transistor on one substrate.

Therefore, when manufacturing a vertical complementary transistor, the thermal budget at the time of impurity diffusion becomes large, and the NPN transistor and the PN
Although both of the manufacturing processes of the P-type transistor could not be optimized, in the present embodiment, the impurity diffusion process at the emitter can be controlled.
Both the PN transistor and the manufacturing process of the PNP transistor can be optimized.

Further, in the present embodiment, nMO
The S transistor and the pMOS transistor can be manufactured simultaneously.

Here, the nMOS transistor corresponds to FIG.
As shown in the figure, the source 37n and the gate 3
8, and a drain 39n as an N-type region.
It has a source 37p that is a type region, a gate 38, and a drain 39p that is a P-type region.

As described above, when an NPN transistor, a PNP transistor, an nMOS transistor, and a pMOS transistor are simultaneously manufactured on one substrate,
A Bi-CMOS including a lateral bipolar transistor and a CMOS (complementary MOS) can be obtained. The NPN transistor, PNP transistor, nMOS transistor, and pMOS transistor
Only some of the transistors may be manufactured.

In this case, a MOS transistor having a fine structure and a bipolar transistor having excellent high-speed performance can be easily manufactured on the same substrate by a small number of steps.

Therefore, various functions and performances can be easily realized by one chip as required by, for example, a system LSI.

Next, an eighth embodiment of the present invention will be described in detail with reference to the drawings.

Note that this embodiment is different from the first embodiment in FIGS. 1A to 1G and FIGS.
Since (e) has the same steps as those shown in FIG. 3, the description thereof is omitted. Also, components having the same configuration as in the first embodiment are given the same reference numerals, and description thereof is omitted.

FIGS. 14 (a) to 4 (c) are views showing steps of manufacturing a semiconductor device in the present embodiment.

The one shown in FIG. 14A is the same as the one shown in FIG. 2B.

First, the surface of the island region 13a made of single crystal silicon exposed at the bottom of the groove is thermally oxidized,
A thermal oxide film 41 having a thickness of about 100 ° is formed. Next, R
Annealing is performed at 1000 ° C. for about 30 seconds by the TA method to diffuse N ⁺ from the polycrystalline silicon regions 15b and 15c to a part of the island region 13a. Then, a silicon oxide film 42 is formed on the entire surface by CVD at a thickness of about 1000 .ANG.
A degree of polycrystalline silicon film 43 is formed. Further, the surface of the polycrystalline silicon film 43 is thermally oxidized to
As shown in (b), a thermal oxide film 44 having a thickness of about 200 ° is formed.
To form

Next, the thermal oxide film 44 is etched back by anisotropic etching to leave only the sidewalls 44a and 44b covering the side surfaces of the groove, as shown in FIG.

Next, the polycrystalline silicon film 43 is etched back by anisotropic etching to form the oxide film 42 and the sidewalls 44a and 44a as shown in FIG.
The intermediate sidewalls 43a and 43b are formed while being left only in the gap 44b.

Next, when the oxide film 42 is etched back and removed by anisotropic etching, only the portion covering the side surface of the groove remains, and sidewalls 42a and 42b are formed. Further, using the sidewalls 43a and 43b as a mask, the surface of the thermal oxide film 41 exposed at the bottom of the groove is also etched and removed.
As shown in (e), the island region 13a has a width of 0.5 μm.
It is exposed with a width of about m.

Thereafter, FIGS. 2 (c) to 2 (e)
A lateral bipolar transistor is manufactured by the same steps as those shown in FIG.

The present embodiment has the following effects in addition to the effects of the first embodiment.

That is, in the present embodiment, the sidewalls 42a, 42b and the sidewalls 4a are further placed on the sidewalls 21a, 21b covering the side surfaces of the groove.
Since 3a, 43b and sidewalls 44a, 44b are overlapped, the innermost sidewalls 44a, 44b are nearly vertical. Therefore, when the base 28 is formed by ion implantation using the sidewall as a mask, the contrast between the region into which the ions are implanted and the region to be masked becomes clear, so that the base profile can be sharply raised. Thus, a base having a small width and a high impurity concentration can be formed, and the performance of the transistor in an ultra-high-speed region can be improved.

The present invention is not limited to the above embodiments, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0123]

As described above in detail, according to the present invention, optimization of a region from which various electrodes are extracted to a three-dimensional geometric structure including interaction with a single crystal region is achieved. By doing so, a semiconductor device with excellent high-speed performance and a manufacturing method thereof can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view (part 1) of a semiconductor device showing a first embodiment of the present invention in the manufacturing process.

FIG. 2 is a sectional view (part 2) of a semiconductor device according to the first embodiment of the present invention, which illustrates a manufacturing step.

FIG. 3 is a cross-sectional view obtained in a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 7 is a top view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 8 is a cross-sectional view (part 1) of a semiconductor device showing a seventh embodiment of the present invention in the manufacturing process.

FIG. 9 is a sectional view (part 2) of a semiconductor device illustrating a seventh embodiment of the present invention in the manufacturing process.

FIG. 10 is a sectional view of a semiconductor device (NPN transistor) according to a seventh embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor device (PNP transistor) according to a seventh embodiment of the present invention.

FIG. 12 is a sectional view of a semiconductor device (nMOS transistor) according to a seventh embodiment of the present invention.

FIG. 13 is a sectional view of a semiconductor device (pMOS transistor) according to a seventh embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 15 is a sectional view of a first conventional semiconductor device.

FIG. 16 is a sectional view of a second conventional semiconductor device.

FIG. 17 is a configuration diagram of a third conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 11 silicon substrate 12, 25, 33, 42 silicon oxide film 13 single crystal silicon layer (first layer) 13a, 13n, 13p island region 13b oxide film 14 insulating film 14a lower layer 14b intermediate layer 14c upper layer 15 polycrystalline silicon layer 15a , 15b, 15c Island-shaped polycrystalline silicon regions 16, 18, 20, 32 Silicon nitride films 17a, 17b, 41, 44 Thermal oxide film (second layer) 19, 19n, 19p Polycrystalline silicon layers 21a, 21b, 23a , 23b, 34a, 34b, 4
3a, 43b, 44a, 44b Side wall 22 Air gap 24, 24p, 24n Base electrode 26 Metal wiring 27 Emitter 28 Base 28a, 28b Base end 29, 29n, 29p Collector 30 W (tungsten) silicide film 31, 43 Polycrystalline silicon Film 37n, 37p Source 38 Gate 39n, 39p Drain

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8228 27/082 (72) Inventor Hirohisa Kitaguchi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric F term in Industrial Co., Ltd. (reference) EA22

Claims (2)

[Claims] 1. A first semiconductor device comprising: (a) an SOI substrate; and (b) a single crystal silicon island region formed on the SOI substrate and having an emitter region, a base region, and a collector region formed thereon.
And (c) a first island region of polycrystalline silicon, which is stacked on the first layer and functions as an electrode in contact with the emitter region, and functions as an electrode in contact with the collector region. A second region including a second island region of polycrystalline silicon;
A layer, (d) a first insulating layer laminated on the second layer,
(E) a second insulating layer laminated on the first insulating layer;
(F) first and second holes which are filled with a wiring material and penetrate the first and second insulating layers to reach the first and second island regions, and (g) an inner wall. An insulating film is formed on the first insulating layer, and a groove penetrating the first insulating region of the second layer and reaching the island region of the first layer; (h)
Filling the groove, a base electrode having one end in contact with the base region and the other end laminated on a part of the first insulating layer, and (i) an interior filled with a wiring material; A third hole penetrating a second insulating layer and reaching the base electrode. 2. A first layer including an island region of single crystal silicon on which an emitter region, a base region, and a collector region are formed is laminated on an SOI substrate, and A first island region of polycrystalline silicon that functions as an electrode in contact with the emitter region, and a second island region of polycrystalline silicon that functions as an electrode in contact with the collector region
(C) laminating a first insulating layer on the second layer, and (d) a first island of the first insulating layer and the second layer. Forming a groove that penetrates the island region to reach the island region of the first layer; (e) forming an insulating film on the inner wall of the groove; and (f) diffusing impurities from the first island region. Forming an emitter region in an adjacent island region of the first layer, and (g) implanting an impurity into the first insulating layer and the inner wall of the groove using an insulating film as a mask, thereby forming the first region.
Forming a base region in the island region of the layer adjacent to the emitter region, (h) filling a base electrode in the groove having the inner wall, and (i) forming a second insulating layer on the first insulating layer. (J) first and second holes penetrating the first and second insulating layers to reach the first and second island regions, and the second insulating layer Forming a third hole that penetrates through the first electrode and reaches the base electrode; and (k) forming the first and second holes.
And filling the third hole with a wiring material.