CN102244078B - Controlled silicon chip structure of mesa technology and implementation method - Google Patents
Controlled silicon chip structure of mesa technology and implementation method Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 121
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 121
- 239000010703 silicon Substances 0.000 title claims abstract description 121
- 238000005516 engineering process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 21
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 55
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 55
- 238000009792 diffusion process Methods 0.000 claims abstract description 55
- 239000011521 glass Substances 0.000 claims abstract description 33
- 239000013078 crystal Substances 0.000 claims abstract description 31
- 239000004411 aluminium Substances 0.000 claims description 47
- 238000002955 isolation Methods 0.000 claims description 39
- 238000001259 photo etching Methods 0.000 claims description 32
- 230000007797 corrosion Effects 0.000 claims description 20
- 238000005260 corrosion Methods 0.000 claims description 20
- 238000005245 sintering Methods 0.000 claims description 20
- 238000001704 evaporation Methods 0.000 claims description 14
- 230000008020 evaporation Effects 0.000 claims description 14
- 238000011049 filling Methods 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 11
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
- 239000011574 phosphorus Substances 0.000 claims description 11
- 238000012545 processing Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000000637 aluminium metallisation Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 238000001459 lithography Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 8
- 238000012856 packing Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 5
- 230000009477 glass transition Effects 0.000 claims description 3
- 230000008961 swelling Effects 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 229910001392 phosphorus oxide Inorganic materials 0.000 claims description 2
- VSAISIQCTGDGPU-UHFFFAOYSA-N tetraphosphorus hexaoxide Chemical compound O1P(O2)OP3OP1OP2O3 VSAISIQCTGDGPU-UHFFFAOYSA-N 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 34
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 17
- 239000000377 silicon dioxide Substances 0.000 abstract description 17
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000002161 passivation Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 230000001681 protective effect Effects 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 33
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 21
- 229910052760 oxygen Inorganic materials 0.000 description 21
- 239000001301 oxygen Substances 0.000 description 21
- 229910052757 nitrogen Inorganic materials 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- 238000004140 cleaning Methods 0.000 description 12
- 238000001035 drying Methods 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 12
- 239000008367 deionised water Substances 0.000 description 9
- 229910021641 deionized water Inorganic materials 0.000 description 9
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 229910052799 carbon Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000010894 electron beam technology Methods 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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Abstract
The invention relates to a controlled silicon chip structure of a mesa technology. The structure comprises an N+ type cathode region, a front surface P-type short base region, a glass passivation film, front surface grooves, a SiO2 protective film, a silicon single crystal chip, a gate pole aluminum electrode and a cathode aluminum electrode, wherein the front side of the silicon single crystal chip is provided with the front P-type short base region; the back side of the silicon single crystal chip is provided with a P-type region; the surface of the front surface P-type short base region isprovided with the SiO2 protective film, the gate pole aluminum electrode and the cathode aluminum electrode; the front grooves are arranged on the front surface P-type short base region and the silicon single crystal chip, and are positioned at two sides of the gate pole aluminum electrode and the cathode aluminum electrode; and the N+ type cathode region is arranged between the cathode aluminum electrode and the front P-type short base region. The structure is characterized in that the bottom part of a dual-pass insulation diffusion region is provided with a back side stress balance groove. The structure provided by the invention has the advantages of mature structure and technology, simple manufacturing process, good breakdown voltage property of the manufactured chip, high percent of pass, and high reliability of products.
Description
Technical field
The present invention relates to a kind of controlled silicon chip structure of mesa technology, also relate to a kind of mesa technology controlled silicon chip implementation method, belong to power semiconductor device manufacturing technology field.
Background technology
The power controllable silicon is in the manufacture of middle high-pressure electric power semiconductor device chip, so far still extensively adopt the mesa technique manufacturing technology, as Figure 1-4, the thick passivation glass film of one deck 30～50 μ m of having grown in the groove in silicon wafer front, due to the coefficient of expansion of this glass-film, than silicon, much larger (coefficient of expansion of general passivation glass is 4.4 ± 0.4 * 10
-6/ ℃, and the coefficient of expansion of silicon is 2.6 * 10
-6/ ℃); after glass sintering completes; glass-film in the groove of front has produced a very large shrinkage stress; pull silicon wafer to be bent upwards, because the bending of silicon wafer makes silicon chip central area and lithography mask version not to be adjacent to, produce gap, cause waste product to produce; often can fall sheet; and the silicon wafer percentage of damage is very high, this method is only suitable in the processing procedure of 4 inches silicon wafers of 2 inches～Φ of Φ, is difficult to the silicon wafer processing procedure for 4 inches of 5 inches～Φ of Φ by above technology.
Summary of the invention
The purpose of this invention is to provide a kind of controlled silicon chip structure of mesa technology, a kind of mesa technology controlled silicon chip implementation method also is provided.
The technical solution used in the present invention is: controlled silicon chip structure of mesa technology comprises N
+type cathodic region, the short base of positive P type, glassivation film, front groove, SiO
2diaphragm, silicon single crystal flake, gate pole aluminium electrode and negative electrode aluminium electrode, described silicon single crystal flake front is provided with the short base of positive P type, and the described silicon single crystal flake back side is provided with back side p type island region, and the short base region surface of described positive P type is provided with SiO
2diaphragm, gate pole aluminium electrode and negative electrode aluminium electrode, the short base of described positive P type and silicon single crystal flake are provided with the front groove, and described front groove is positioned at gate pole aluminium electrode and negative electrode aluminium electrode both sides, between described negative electrode aluminium electrode and the short base of positive P type, is provided with N
+the type cathodic region, be provided with back side stress equilibrium groove to bottom, logical isolation diffusion district, and stress equilibrium groove top, the described back side and sidewall are provided with glass-film, and described back side p type island region and glassivation film surface are provided with multilayer metallic electrode.
Described is 100-180 μ m to the logical isolation diffusion district degree of depth, and the described minimum value to logical isolation diffusion sector width is 80-200 μ m.
The mesa technology controlled silicon chip implementation method, comprise growth oxide layer step, photoetching is to logical isolation diffusion district window step, to logical isolation diffusion step, the positive short base of P type and P type tegmen district, back side diffusing step, photoetching cathodic region window step, cathodic region phosphorus diffusing step, photoetching trench openings and trench etching step, filling glass and sintering step in groove, the lithography fair lead step, positive AM aluminum metallization film step, anti-carve aluminium electrode step, back side evaporation metal electrode step and subsequent processing steps, described growth oxide layer step is the silicon single crystal flake chemical polishing, clean and the growth oxide layer, described is to logical isolation diffusion to logical isolation diffusion step, forms P type isolation strip, the short base of described positive P type and P type tegmen district, back side diffusing step are the short base of positive P type and p type anode district, the back side oxide layer that spreads simultaneously and grow, described cathodic region phosphorus diffusing step is N
+the type cathodic region phosphorus oxide layer that spreads and grow, the corrosion window that described photoetching trench openings and trench etching step are the photoetching front, and go out the ring-shaped groove of certain depth at front etch, the interior filling glass of described groove and sintering step are for filling glass in groove and carry out sintering, and the glass-film after burning till is as the terminal passivating film of P-N knot, and growth LTO passivating film, protected glass-film, described lithography fair lead step is the fairlead in positive photoetching gate pole district and cathodic region, at positive AM aluminum metallization film, anti-carves positive aluminium electrode, and alloy is removed back side oxide layer, back side evaporation metal electrode, described subsequent processing steps is chip testing and sorting, and the chip separation is carried out in scribing, check, packing, described photoetching cathodic region window step be photoetching just, the corrosion window at the back side, and just, the back side erodes away groove simultaneously, gash depth is 100-180 μ m, groove width is 80-200 μ m, backside trench necessarily be in the back side in logical isolated area, and on the silicon face in groove, any point is more than or equal to 30 μ m with the beeline to logical isolation P-N knot, filling glass carry out sintering in the groove of front and back, burn till the passivating film of the glass-film of rear front groove as the P-N knot, burn till the glass-film of rear backside trench as balance front convergent force leveling silicon chip, 3-6h anneals under glass transition point-(10～20) ℃, realize reducing the glass swelling coefficient.
Advantage of the present invention is: structure and technical maturity, manufacture process is simple, the chip breakdown voltage characteristics of manufacturing is good, qualification rate is higher, and product reliability is higher, chip passive region at silicon chip back side has dug out a groove that adjacent chips is shared, we are referred to as to call the stress equilibrium groove, glass sintering have been filled in this stress equilibrium groove, formed one deck glass-film at its top and sidewall, this glass-film utilizes its larger shrinkage stress to offset the shrinkage stress of face glass film, make silicon chip smooth, processing procedure after glassivation is accessible, reduce the percentage of damage of silicon wafer in processing procedure, the method that has adopted two sides simultaneously to process, in the temperature-fall period of glass sintering, having increased at " glass transition point-(10～20) ℃ " lower annealing process further reduces the glass swelling coefficient.
The accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the controlled silicon chip structure of mesa technology schematic diagram that background technology is mentioned.
Fig. 2 is the mesa technology controlled silicon chip manufacture process schematic diagram that background technology is mentioned.
Fig. 3 is the silicon chip flexibility schematic diagram of background technology after for the major diameter silicon wafer.
The glass sintering temperature curve that Fig. 4 is background technology.
Fig. 5 controlled silicon chip structure of mesa technology schematic diagram of the present invention.
Fig. 6 mesa technology controlled silicon chip manufacture process of the present invention schematic diagram, a, silicon single crystal flake growth oxide layer wherein, b, the photoetching window to logical isolation diffusion district, c, to logical isolation diffusion, d, p-type short base diffusion, e, photoetching cathodic region window, f, N
+the diffusion of type cathodic region phosphorus, g, photoetching corrosion window etching tank, filling glass sintering in h, groove, i, photoetching front fairlead, j, positive AM aluminum metallization film, k, anti-carve front side aluminum electrode, l, back side evaporation metal electrode.
Fig. 7 is the silicon chip flexibility schematic diagram of the technology of the present invention after for the major diameter silicon wafer.
The glass sintering temperature curve that Fig. 8 is the technology of the present invention.
Wherein: 1, N
+the type cathodic region, 2, the short base of positive P type, 3, the glassivation film, 4 front grooves, 5, SiO
2diaphragm, 6, silicon single crystal flake, 7, gate pole aluminium electrode, 8, negative electrode aluminium electrode, 9, the back metal electrode, 10, back side p type island region, 11, the glass-film in the stress equilibrium groove of the back side, 12, to logical isolation diffusion district, 13, back side stress equilibrium groove.
Embodiment
As shown in Figure 5, controlled silicon chip structure of mesa technology of the present invention, comprise N
+type cathodic region 1, the short base 2 of positive P type, glassivation film 3, front groove 4, SiO
2diaphragm 5, silicon single crystal flake 6, gate pole aluminium electrode 7 and negative electrode aluminium electrode 8, silicon single crystal flake 6 fronts are provided with the short base 2 of positive P type, and silicon single crystal flake 6 back sides are provided with back side p type island region 10, and 2 surfaces, the short base of positive P type are provided with SiO
2diaphragm 5, gate pole aluminium electrode 7 and negative electrode aluminium electrode 8, the short base 2 of positive P type and silicon single crystal flake 6 are provided with front groove 4, and front groove 4 is positioned at gate pole aluminium electrode 7 and negative electrode aluminium electrode 8 both sides, between negative electrode aluminium electrode 8 and the short base 2 of positive P type, is provided with N
+type cathodic region 1,12 bottoms, logical isolation diffusion district are provided with to back side stress equilibrium groove 13, to logical isolation diffusion district 12 degree of depth, be 100 μ m, minimum value to logical isolation diffusion district 12 width is 80 μ m, stress equilibrium groove 13 tops, the back side and sidewall are provided with glass-film 11, and back side p type island region 10 and glassivation film 11 surfaces are provided with multilayer metallic electrode 9.
As shown in Fig. 6, Fig. 7 and Fig. 8, the mesa technology controlled silicon chip implementation method comprises:
Growth oxide layer step: silicon single crystal flake is carried out to chemical polishing, the silicon chip after polishing is carried out to RCA cleaning, drying, silicon chip is placed in to oxidation under the oxygen atmosphere under 1100 ℃, oxidization time is 5 hours, and requiring the oxidated layer thickness of growth is 1.0 μ m;
Photoetching is to leading to isolation diffusion district window step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 95 ℃/20min, utilize double face photoetching machine, mask plate to be exposed, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, removes cull, clean, dry;
To leading to isolation diffusion step: a, silicon chip being carried out to the RCA cleaning, use deionized water rinsing 15 times; B, drying; C, in the Tu Peng source, positive and negative two sides of silicon chip; D, boron give deposition, under 1070 ℃, nitrogen and oxygen atmosphere, spread 1.6 h, form P type sedimentary deposit, require R
□=4.5 Ω/; E, knot, under 1270 ℃, nitrogen and oxygen atmosphere, diffusion 130h, form P type isolation diffusion district;
The positive short base of P type and P type tegmen district, back side diffusing step: a, silicon chip is carried out to the RCA cleaning, with deionized water rinsing 15 times; B, drying; C, in the Tu Peng source, positive and negative two sides of silicon chip; D, boron give deposition, under 9405 ℃, nitrogen and oxygen atmosphere, spread 0.9 h, form P type sedimentary deposit, require R
□=25 Ω/; E, knot, under 1250 ℃, nitrogen and oxygen atmosphere, diffusion 18h, form p type diffusion region on the positive and negative two sides of silicon chip;
Photoetching cathodic region window step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, through the front baking of 95 ℃/20min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, remove cull, clean, dry;
Cathodic region phosphorus diffusing step: a, silicon chip is carried out to the RCA cleaning, with deionized water rinsing 15 times; B, drying; C, phosphorus give deposition, under 950 ℃, pass into and carry POCL
3nitrogen and oxygen, diffusion 1.3h, form N
+sedimentary deposit, require R
□=1 Ω/; D, knot, under 1195 ℃, nitrogen and oxygen atmosphere, diffusion 3.4h, form the cathodic region diffusion layer;
Photoetching trench openings and trench etching step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 95 ℃/20min, utilize mask aligner, mask plate to carry out double-sided exposure, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, cleans, dry, utilize HF:HN0
3: CH
3the corrosive liquid of COOH=3:1:1 erodes away the groove of front and back simultaneously, removes cull, cleans, and dries;
Filling glass and sintering step in groove: prepare glass and stick with paste, glass is stuck with paste and scraped silicon chip surface, wipe the outer glass of groove and stick with paste, according to the temperature curve shown in Fig. 8, carry out sintering;
Lithography fair lead step: utilize sol evenning machine that photoresist is coated in to front side of silicon wafer, front baking through 95 ℃/20min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize buffered hydrofluoride acid to erode the silicon dioxide film of front window, simultaneously that the silicon dioxide erosion at the back side is clean, remove cull, clean, dry;
Positive AM aluminum metallization film step: utilize the high vacuum electron beam evaporator at the thick rafifinal film of the front of silicon chip evaporation one deck 5 μ m;
Anti-carve aluminium electrode step: utilize sol evenning machine photoresist to be coated in to the front of silicon chip, through the front baking of 95 ℃/20min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize the phosphoric acid corrosion corrosion to remove the aluminium of window, removes cull, cleans, and dries;
Back side evaporation metal electrode step: the oxide layer at the back side is removed in sandblast, cleans up, and utilizes the multilayer metallic electrode of high vacuum electron beam evaporator at the back side of silicon chip evaporation titanium (0.1 μ m is thick)-nickel (0.5 μ m is thick)-silver (1.2 μ m are thick);
Subsequent processing steps: a, chip testing and sorting; B, scribing, carry out the chip separation; C, check; D, packing.
As shown in Figure 5, controlled silicon chip structure of mesa technology of the present invention, comprise N
+type cathodic region 1, the short base 2 of positive P type, glassivation film 3, front groove 4, SiO
2diaphragm 5, silicon single crystal flake 6, gate pole aluminium electrode 7 and negative electrode aluminium electrode 8, silicon single crystal flake 6 fronts are provided with the short base 2 of positive P type, and silicon single crystal flake 6 back sides are provided with back side p type island region 10, and 2 surfaces, the short base of positive P type are provided with SiO
2diaphragm 5, gate pole aluminium electrode 7 and negative electrode aluminium electrode 8, the short base 2 of positive P type and silicon single crystal flake 6 are provided with front groove 4, and front groove 4 is positioned at gate pole aluminium electrode 7 and negative electrode aluminium electrode 8 both sides, between negative electrode aluminium electrode 8 and the short base 2 of positive P type, is provided with N
+type cathodic region 1,12 bottoms, logical isolation diffusion district are provided with to back side stress equilibrium groove 13, to logical isolation diffusion district 12 degree of depth, be 140 μ m, minimum value to logical isolation diffusion district 12 width is 140 μ m, stress equilibrium groove 13 tops, the back side and sidewall are provided with glass-film 11, and back side p type island region 10 and glassivation film 11 surfaces are provided with multilayer metallic electrode 9.
As shown in Fig. 6, Fig. 7 and Fig. 8, the mesa technology controlled silicon chip implementation method comprises:
Growth oxide layer step: silicon single crystal flake is carried out to chemical polishing, the silicon chip after polishing is carried out to RCA cleaning, drying, silicon chip is placed in to oxidation under the oxygen atmosphere under 1150 ℃, oxidization time is 8 hours, and requiring the oxidated layer thickness of growth is 1.5 μ m;
Photoetching is to leading to isolation diffusion district window step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 100 ℃/25min, utilize double face photoetching machine, mask plate to be exposed, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, removes cull, clean, dry;
To leading to isolation diffusion step: a, silicon chip being carried out to the RCA cleaning, use deionized water rinsing 15 times; B, drying; C, in the Tu Peng source, positive and negative two sides of silicon chip; D, boron give deposition, under 1080 ℃, nitrogen and oxygen atmosphere, spread 1.8 h, form P type sedimentary deposit, require R
□=5 Ω/; E, knot, under 1275 ℃, nitrogen and oxygen atmosphere, spread 140 h, forms P type isolation diffusion district;
The positive short base of P type and P type tegmen district, back side diffusing step: a, silicon chip is carried out to the RCA cleaning, with deionized water rinsing 15 times; B, drying; C, in the Tu Peng source, positive and negative two sides of silicon chip; D, boron give deposition, and under 955 ℃, nitrogen and oxygen atmosphere, diffusion 1.0h, form P type sedimentary deposit, requires R
□=35 Ω/; E, knot, under 1260 ℃, nitrogen and oxygen atmosphere, diffusion 25h, form p type diffusion region on the positive and negative two sides of silicon chip;
Photoetching cathodic region window step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 100 ℃/25min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, removes cull, clean, dry;
Cathodic region phosphorus diffusing step: a, silicon chip is carried out to the RCA cleaning, with deionized water rinsing 15 times; B, drying; C, phosphorus give deposition, under 1000 ℃, pass into and carry POCL
3nitrogen and oxygen, diffusion 1.5h, form N
+sedimentary deposit, require R
□=3 Ω/; D, knot, under 1205 ℃, nitrogen and oxygen atmosphere, diffusion 4.0h, form the cathodic region diffusion layer;
Photoetching trench openings and trench etching step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 100 ℃/25min, utilize mask aligner, mask plate to carry out double-sided exposure, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, cleans, dry, utilize HF:HN0
3: CH
3the corrosive liquid of COOH=4:1:1 erodes away the groove of front and back simultaneously, removes cull, cleans, and dries;
Filling glass and sintering step in groove: prepare glass and stick with paste, glass is stuck with paste and scraped silicon chip surface, wipe the outer glass of groove and stick with paste, according to the temperature curve shown in Fig. 8, carry out sintering;
Lithography fair lead step: utilize sol evenning machine that photoresist is coated in to front side of silicon wafer, front baking through 100 ℃/25min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize buffered hydrofluoride acid to erode the silicon dioxide film of front window, simultaneously that the silicon dioxide erosion at the back side is clean, remove cull, clean, dry;
Positive AM aluminum metallization film step: utilize the high vacuum electron beam evaporator at the thick rafifinal film of the front of silicon chip evaporation one deck 6 μ m;
Anti-carve aluminium electrode step: utilize sol evenning machine photoresist to be coated in to the front of silicon chip, through the front baking of 100 ℃/25min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize the phosphoric acid corrosion corrosion to remove the aluminium of window, removes cull, cleans, and dries;
Back side evaporation metal electrode step: the oxide layer at the back side is removed in sandblast, cleans up, and utilizes the multilayer metallic electrode of high vacuum electron beam evaporator at the back side of silicon chip evaporation titanium (0.1 μ m is thick)-nickel (0.5 μ m is thick)-silver (1.2 μ m are thick);
Subsequent processing steps: a, chip testing and sorting; B, scribing, carry out the chip separation; C, check; D, packing.
As shown in Figure 5, controlled silicon chip structure of mesa technology of the present invention, comprise N
+type cathodic region 1, the short base 2 of positive P type, glassivation film 3, front groove 4, SiO
2diaphragm 5, silicon single crystal flake 6, gate pole aluminium electrode 7 and negative electrode aluminium electrode 8, silicon single crystal flake 6 fronts are provided with the short base 2 of positive P type, and silicon single crystal flake 6 back sides are provided with back side p type island region 10, and 2 surfaces, the short base of positive P type are provided with SiO
2diaphragm 5, gate pole aluminium electrode 7 and negative electrode aluminium electrode 8, the short base 2 of positive P type and silicon single crystal flake 6 are provided with front groove 4, and front groove 4 is positioned at gate pole aluminium electrode 7 and negative electrode aluminium electrode 8 both sides, between negative electrode aluminium electrode 8 and the short base 2 of positive P type, is provided with N
+type cathodic region 1,12 bottoms, logical isolation diffusion district are provided with to back side stress equilibrium groove 13, to logical isolation diffusion district 12 degree of depth, be 180 μ m, minimum value to logical isolation diffusion district 12 width is 200 μ m, stress equilibrium groove 13 tops, the back side and sidewall are provided with glass-film 11, and back side p type island region 10 and glassivation film 11 surfaces are provided with multilayer metallic electrode 9.
As shown in Fig. 6, Fig. 7 and Fig. 8, the mesa technology controlled silicon chip implementation method comprises:
Growth oxide layer step: silicon single crystal flake is carried out to chemical polishing, the silicon chip after polishing is carried out to RCA cleaning, drying, silicon chip is placed in to oxidation under the oxygen atmosphere under 1200 ℃, oxidization time is 10 hours, and requiring the oxidated layer thickness of growth is 1.8 μ m;
Photoetching is to leading to isolation diffusion district window step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 105 ℃/30min, utilize double face photoetching machine, mask plate to be exposed, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, removes cull, clean, dry;
To leading to isolation diffusion step: a, silicon chip being carried out to the RCA cleaning, use deionized water rinsing 15 times; B, drying; C, in the Tu Peng source, positive and negative two sides of silicon chip; D, boron give deposition, and under 1090 ℃, nitrogen and oxygen atmosphere, diffusion 2h, form P type sedimentary deposit, requires R
□=5.5 Ω/; E, knot, under 1280 ℃, nitrogen and oxygen atmosphere, diffusion 150h, form P type isolation diffusion district;
The positive short base of P type and P type tegmen district, back side diffusing step: a, silicon chip is carried out to the RCA cleaning, with deionized water rinsing 15 times; B, drying; C, in the Tu Peng source, positive and negative two sides of silicon chip; D, boron give deposition, under 970 ℃, nitrogen and oxygen atmosphere, spread 1.1 h, form P type sedimentary deposit, require R
□=45 Ω/; E, knot, under 1270 ℃, nitrogen and oxygen atmosphere, spread 38 h, on the positive and negative two sides of silicon chip, forms p type diffusion region;
Photoetching cathodic region window step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 105 ℃/30min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, removes cull, clean, dry;
Cathodic region phosphorus diffusing step: a, silicon chip is carried out to the RCA cleaning, with deionized water rinsing 15 times; B, drying; C, phosphorus give deposition, under 1080 ℃, pass into and carry POCL
3nitrogen and oxygen, spread 1.7 h, form N
+sedimentary deposit, require R
□=4.0 Ω/; D, knot, under 1215 ℃, nitrogen and oxygen atmosphere, diffusion 4.6h, form the cathodic region diffusion layer;
Photoetching trench openings and trench etching step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 105 ℃/30min, utilize mask aligner, mask plate to carry out double-sided exposure, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, cleans, dry, utilize HF:HN0
3: CH
3the corrosive liquid of COOH=4:1:1 erodes away the groove of front and back simultaneously, removes cull, cleans, and dries;
Filling glass and sintering step in groove: prepare glass and stick with paste, glass is stuck with paste and scraped silicon chip surface, wipe the outer glass of groove and stick with paste, according to the temperature curve shown in Fig. 8, carry out sintering;
Lithography fair lead step: utilize sol evenning machine that photoresist is coated in to front side of silicon wafer, front baking through 105 ℃/30min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize buffered hydrofluoride acid to erode the silicon dioxide film of front window, simultaneously that the silicon dioxide erosion at the back side is clean, remove cull, clean, dry;
Positive AM aluminum metallization film step: utilize the high vacuum electron beam evaporator at the thick rafifinal film of the front of silicon chip evaporation one deck 8 μ m;
Anti-carve aluminium electrode step: utilize sol evenning machine photoresist to be coated in to the front of silicon chip, through the front baking of 105 ℃/30min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize the phosphoric acid corrosion corrosion to remove the aluminium of window, removes cull, cleans, and dries;
Back side evaporation metal electrode step: the oxide layer at the back side is removed in sandblast, cleans up, and utilizes the multilayer metallic electrode of high vacuum electron beam evaporator at the back side of silicon chip evaporation titanium (0.1 μ m is thick)-nickel (0.5 μ m is thick)-silver (1.2 μ m are thick);
Subsequent processing steps: a, chip testing and sorting; B, scribing, carry out the chip separation; C, check; D, packing.
Claims (2)
1. controlled silicon chip structure of mesa technology, comprise N
+type cathodic region, the short base of positive P type, glassivation film, front groove, SiO
2diaphragm, silicon single crystal flake, gate pole aluminium electrode and negative electrode aluminium electrode, described silicon single crystal flake front is provided with the short base of positive P type, and the described silicon single crystal flake back side is provided with back side p type island region, and the short base region surface of described positive P type is provided with SiO
2diaphragm, gate pole aluminium electrode and negative electrode aluminium electrode, the short base of described positive P type and silicon single crystal flake are provided with the front groove, and described front groove is positioned at gate pole aluminium electrode and negative electrode aluminium electrode both sides, between described negative electrode aluminium electrode and the short base of positive P type, is provided with N
+the type cathodic region, it is characterized in that: bottom, logical isolation diffusion district is provided with to back side stress equilibrium groove, stress equilibrium groove top, the described back side and sidewall are provided with glass-film, described back side p type island region and glassivation film surface are provided with multilayer metallic electrode, described is 100-180 μ m to the logical isolation diffusion district degree of depth, and the described minimum value to logical isolation diffusion sector width is 80-200 μ m.
2. mesa technology controlled silicon chip implementation method, comprise growth oxide layer step, photoetching is to logical isolation diffusion district window step, to logical isolation diffusion step, the positive short base of P type and P type tegmen district, back side diffusing step, photoetching cathodic region window step, cathodic region phosphorus diffusing step, photoetching trench openings and trench etching step, filling glass and sintering step in groove, the lithography fair lead step, positive AM aluminum metallization film step, anti-carve aluminium electrode step, back side evaporation metal electrode step and subsequent processing steps, described growth oxide layer step is the silicon single crystal flake chemical polishing, clean and the growth oxide layer, described is to logical isolation diffusion to logical isolation diffusion step, forms P type isolation strip, the short base of described positive P type and P type tegmen district, back side diffusing step are the short base of positive P type and p type anode district, the back side oxide layer that spreads simultaneously and grow, described cathodic region phosphorus diffusing step is N
+the type cathodic region phosphorus oxide layer that spreads and grow, the corrosion window that described photoetching trench openings and trench etching step are the photoetching front, and go out the ring-shaped groove of certain depth at front etch, the interior filling glass of described groove and sintering step are for filling glass in groove and carry out sintering, and the glass-film after burning till is as the terminal passivating film of P-N knot, and growth LTO passivating film, protected glass-film, described lithography fair lead step is the fairlead in positive photoetching gate pole district and cathodic region, at positive AM aluminum metallization film, anti-carves positive aluminium electrode, and alloy is removed back side oxide layer, back side evaporation metal electrode, described subsequent processing steps is chip testing and sorting, and the chip separation is carried out in scribing, and check, packing is characterized in that: described photoetching cathodic region window step be photoetching just, the corrosion window at the back side, and just, the back side erodes away groove simultaneously, gash depth is 100-180 μ m, groove width is 80-200 μ m, backside trench necessarily be in the back side in logical isolated area, and on the silicon face in groove, any point is more than or equal to 30 μ m with the beeline to logical isolation P-N knot, filling glass carry out sintering in the groove of front and back, burn till the passivating film of the glass-film of rear front groove as the P-N knot, burn till the glass-film of rear backside trench as balance front convergent force leveling silicon chip, 3-6h anneals under glass transition point-(10～20) ℃, realize reducing the glass swelling coefficient.
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