CN110581057A

CN110581057A - Manufacturing method of single-chip double-channel protection assembly

Info

Publication number: CN110581057A
Application number: CN201810597483.6A
Authority: CN
Inventors: 李运鹏; 郭小红; 陈智伟; 黄传传
Original assignee: Jiangxi Sari Microelectronic Technology Co Ltd
Current assignee: Jiangxi Sari Microelectronic Technology Co Ltd
Priority date: 2018-06-11
Filing date: 2018-06-11
Publication date: 2019-12-17

Abstract

The invention discloses a manufacturing method of a single-chip double-channel protection component, which comprises the following steps: (1) taking a silicon wafer as a substrate, wherein the substrate is P-type or N-type, (2) putting the silicon wafer into a diffusion furnace or an ion implanter, doping a layer of N-type or P-type impurities, (3) putting the silicon wafer into an oxidation furnace, heating and oxidizing to form another layer of oxide layer, (4) putting the silicon wafer into the diffusion furnace, doping and continuing driving to form a PN junction, (5) irradiating the surface of the substrate with first light, and (6) obtaining a diffusion region and a cutting path pattern through lithography exposure. After the original silicon wafer is diffused, the front side and the back side of the chip are etched by using two sets of U-shaped groove photoetching plates to form an effective PN section, then the PN section is protected by a passivation technology, and a cutting path is cut to form a double-channel integrated chip, so that the cost is low.

Description

Manufacturing method of single-chip double-channel protection assembly

Technical Field

The invention relates to a manufacturing method, in particular to a manufacturing method of a single-chip double-channel protection component.

Background

Chips, also known as microcircuits (microcircuits), microchips (microchips), and Integrated Circuits (ICs). Refers to a silicon chip containing integrated circuits, which is small in size and is often part of a computer or other electronic device.

With the increasing miniaturization of electronic devices, the demand for integration of electronic components used therein is also increasing. This applies in particular to memory elements or extended memories, which typically consist of a plurality of memory chips electrically contacted by a common contact substrate.

the prior single-chip double-channel protection component mostly adopts a manufacturing method of superposing two crystal grains, the production of the chip component is correspondingly complex and comprises a plurality of continuous method steps, so that different tools are required to manufacture the laminated arrangement, the cost is higher, and the yield is low.

Disclosure of Invention

the present invention is directed to a method for manufacturing a single-chip dual-channel protection device, so as to solve the above-mentioned problems in the prior art.

In order to achieve the purpose, the invention provides the following technical scheme:

a manufacturing method of a single-chip dual-channel protection component comprises the following steps: (1) taking a silicon wafer as a substrate, wherein the substrate is P-type or N-type, (2) placing the silicon wafer into a diffusion furnace or an ion implanter, doping a layer of N-type or P-type impurities, (3) placing the silicon wafer into an oxidation furnace, heating and oxidizing to form another layer of oxide layer, (4) placing the silicon wafer into the diffusion furnace, doping and continuing driving to form a PN junction, (5) irradiating the surface of the substrate with first light, (6) obtaining a diffusion region and a cutting channel pattern through lithography exposure, (7) etching the oxide layer in the cutting channel pattern region to form an etching region, (8) etching the silicon in the formed etching region to form a cutting channel and a double-channel reverse bias region, (9) thermally growing an oxide layer on each of the front surface and the reverse surface of the substrate to protect the PN junction, (10) irradiating the surface of the substrate with a second photomask to obtain an electrode region pattern through lithography exposure, etching the oxide layer of the electrode area pattern to form an electrode area, (10) plating electrode metal on the electrode areas on the front and back sides of the substrate, placing the silicon wafer into a sintering furnace to bond the metal with the substrate, etching the metal on the surface of the silicon wafer, plating the electrode metal on the electrode areas on the front and back sides of the substrate, and cutting the silicon wafer into single chips along the cutting channels, thus forming the double-channel protection element formed by integrating two bidirectional transient suppressors into a single chip for packaging.

as a further scheme of the invention: and (3) when the substrate in the step (1) is of a P type, the impurity in the step (2) is of an N type.

As a still further scheme of the invention: and (3) when the substrate in the step (1) is of an N type, the impurity in the step (2) is of a P type.

compared with the prior art, the invention has the beneficial effects that: after the original silicon wafer is diffused, the front side and the back side of the chip are etched by using two sets of U-shaped groove photoetching plates to form an effective PN section, then the PN section is protected by a passivation technology, and a cutting path is cut to form a double-channel integrated chip, so that the cost is low.

Drawings

FIG. 1 is a schematic diagram of a silicon wafer after being placed in a diffusion furnace or an ion implanter according to the present invention.

fig. 2 is a schematic view of the structure of the silicon wafer of the present invention after being placed in an oxidation furnace.

FIG. 3 is a schematic diagram of a structure of forming scribe lines by etching silicon in the etched region according to the present invention.

FIG. 4 is a schematic diagram of the structure of the electrode region formed by etching the oxide layer of the region pattern according to the present invention.

FIG. 5 is a schematic structural diagram of the present invention for dicing a silicon wafer into single chips along dicing streets.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1 to 5, in an embodiment of the present invention, a method for manufacturing a single-chip dual-channel protection device includes the following steps:

Step 1: a silicon wafer is used as a substrate 302, which is P-type or N-type (in this case, N-type);

Step 2: as shown in fig. 1, a silicon wafer is placed in a diffusion furnace or ion implanter and doped with a layer of P-type impurities 304;

and step 3: referring to fig. 2, the silicon wafer is placed in an oxidation furnace, and is heated and oxidized to form another oxide layer 306;

And 4, step 4: placing the silicon wafer into a diffusion furnace for doping and continuing driving in to form a PN junction 308;

And 5: irradiating the surface of the substrate with first light, and exposing by lithography to obtain a diffusion region and a scribe line pattern;

Step 6: etching the oxide layer in the patterned region formed in step 5 to form an etched region 310;

and 7: referring to fig. 3, the silicon in the etched region formed in step 6 is etched to form a scribe line 312 and a dual-channel reverse bias region 314;

And 8: thermally growing an oxide layer 316 on the front surface and the back surface of the substrate respectively to protect the PN junction;

And step 9: irradiating the substrate surface with a second mask, and exposing by photolithography to obtain an electrode region pattern;

Step 10: referring to fig. 4, the oxide layer of the region pattern formed in step 9 is etched to form an electrode region 318;

Step 11: plating electrode metal 320 on the electrode areas of the front and back surfaces of the substrate;

step 12: placing the silicon wafer into a sintering furnace to bond the metal 320 and the substrate 302;

Step 13: etching the metal on the surface of the chip, and plating electrode metal 320 on the electrode areas on the front surface and the back surface of the substrate;

Step 14: referring to fig. 5, the silicon wafer is diced into single chips along the dicing streets, so that the single chip is formed into a dual-channel protection device integrating two bi-directional transient suppressors for packaging.

In summary, after the original silicon wafer is diffused, the front and back sides of the chip are etched by using two sets of U-shaped groove photoetching plates to form an effective PN node, then the PN node is protected by a passivation technology, and a cutting path is cut to form a dual-channel integrated chip, so that the cost is low.

it will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. a method of manufacturing a single-chip dual-channel protection device, comprising the steps of: (1) taking a silicon wafer as a substrate, wherein the substrate is P-type or N-type, (2) placing the silicon wafer into a diffusion furnace or an ion implanter, doping a layer of N-type or P-type impurities, (3) placing the silicon wafer into an oxidation furnace, heating and oxidizing to form another layer of oxide layer, (4) placing the silicon wafer into the diffusion furnace, doping and continuing driving to form a PN junction, (5) irradiating the surface of the substrate with first light, (6) obtaining a diffusion region and a cutting channel pattern through lithography exposure, (7) etching the oxide layer in the cutting channel pattern region to form an etching region, (8) etching the silicon in the formed etching region to form a cutting channel and a double-channel reverse bias region, (9) thermally growing an oxide layer on each of the front surface and the reverse surface of the substrate to protect the PN junction, (10) irradiating the surface of the substrate with a second photomask to obtain an electrode region pattern through lithography exposure, etching the oxide layer of the electrode area pattern to form an electrode area, (10) plating electrode metal on the electrode areas on the front and back sides of the substrate, placing the silicon wafer into a sintering furnace to bond the metal with the substrate, etching the metal on the surface of the silicon wafer, plating the electrode metal on the electrode areas on the front and back sides of the substrate, and cutting the silicon wafer into single chips along the cutting channels, thus forming the double-channel protection element formed by integrating two bidirectional transient suppressors into a single chip for packaging.

2. The method as claimed in claim 1, wherein if the substrate in step (1) is P-type, the impurity in step (2) is N-type.

3. the method as claimed in claim 1, wherein if the substrate in step (1) is N-type, the impurity in step (2) is P-type.