JP4856419B2 - Bidirectional planar diode - Google Patents

Description

  The present invention relates to a high breakdown voltage of a bidirectional planar diode.

  In order to reduce the number of parts and reduce the number of assembly steps, a diode that has two-way voltage blocking capability and was used by connecting two diodes in anti-series can be realized with a single element. Technology is in general use. For this reason, for example, in the surface mount semiconductor device described in Japanese Patent Application Laid-Open No. 7-254620 (Patent Document 1), the opposite second conductive type semiconductor regions formed on one surface of the first conductive type semiconductor substrate apart from each other. By connecting the lead frame to the surfaces of the two semiconductor regions, the entire surface excluding a part of the lead frame is sealed and integrated with a resin. It is supposed to be obtained.

  Further, as this type of diode, for example, in a bidirectional Zener diode described in Japanese Patent Application Laid-Open No. 2004-179572 (Patent Document 2), two electrodes are formed on both surfaces of the substrate, and the two diodes are arranged on the surface side of the substrate. And then mounted on a lead frame by die bonding and wire bonding to obtain a bidirectional Zener diode.

Further, as a diode capable of blocking voltage in both directions, for example, in the bidirectional constant voltage diode described in Japanese Patent Laid-Open No. 2002-37392 (Patent Document 3) or a manufacturing method thereof, breakdown is caused at a constant voltage in both directions of a pnp or npn structure. The pn junction side surface of the bevel-type diode pellet has a negative bevel structure with curvature, and is processed so that the intermediate semiconductor region is the outermost periphery of the diode pellet in the projection projected from one main surface. It is said that a diode having excellent reverse blocking characteristics can be obtained by coating the bevel surface with polyimide silicone or glass.
JP-A-7-254620 JP 2004-179572 A JP 2002-37392 A

  By the way, each of the bidirectional diodes has a transistor structure having a pnp structure or an npn structure, and causes a breakdown when a reverse bias voltage is applied to pn junctions connected in series in opposite directions to each other. A constant voltage can be blocked. However, the present inventor has found that the above-described bidirectional diode has a problem in that the withstand voltage decreases due to the influence of the transistor action. That is, the breakdown voltage of the bidirectional diode is not determined purely by the breakdown voltage of the pn junction, and the current that flows during breakdown becomes the base current of the transistor structure, and breakdown occurs below the breakdown voltage of the pn junction (so-called transistor action). Accordingly, there is a problem that the withstand voltage of the bidirectional diode is lowered.

  Accordingly, an object of the present invention is to provide a technique capable of improving the breakdown voltage of a bidirectional diode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, according to the present invention, a first semiconductor region of a first conductivity type and a second conductivity type semiconductor region opposite to the first conductivity type are provided so as to be in contact with the first semiconductor region. In a bidirectional diode having a second conductivity type second semiconductor region and a first conductivity type third semiconductor region provided in contact with the second semiconductor region, a lifetime killer is introduced into the second semiconductor region. It is a thing.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, since the lifetime of the second semiconductor region can be reduced by introducing a lifetime killer into the second semiconductor region, when a voltage is applied between the first and third semiconductor regions, The current amplification factor can be lowered in the pnp structure or npn structure transistor structure formed by the first, second, and third semiconductor regions. As a result, the current amplification factor can be reduced as compared with the case where no lifetime killer is introduced, so that the withstand voltage of the bidirectional diode can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the first embodiment, in order to improve the blocking characteristics of the bidirectional planar diode, the lifetime of the other conductive type semiconductor region interposed between one conductive type semiconductor region is introduced as a lifetime killer. The technology to reduce by (light element ion implantation and heavy metal diffusion) will be described.

  FIG. 1 is a plan view seen from the top surface of a semiconductor chip having a bidirectional planar diode according to an embodiment of the present invention, and FIG. 2 is an AA line of the semiconductor chip having the bidirectional planar diode of FIG. FIG. In the plan view of FIG. 1, hatching is given to a part in order to make the drawing easy to see.

  The bidirectional planar diode according to the first embodiment is a diode having a characteristic of blocking voltage in both directions. The semiconductor chip SC having this bidirectional planar diode is made of, for example, silicon (Si) single crystal, and has a first main surface and a second main surface located on opposite sides along the thickness direction. Yes.

Further, the semiconductor chip SC is formed, the said n ⁺⁺ type semiconductor region of high impurity concentration having a second main surface (first semiconductor region of a first conductivity type) 1, by an epitaxial method or the like on the n ⁺⁺ type semiconductor region The p ⁺ type semiconductor region (second conductivity type second semiconductor region) 2 having the first main surface and the first main surface of the p ⁺ type semiconductor region 2 are selectively separated from each other by diffusion. And n ⁺⁺ type semiconductor regions (first conductivity type third semiconductor regions) 3 and 4 having two high impurity concentrations formed in such a manner.

The two n ⁺⁺ type semiconductor regions 3 and 4 are formed in a substantially triangular shape when seen in a plan view, and are symmetrical about the line connecting the diagonals of the semiconductor chip SC. Are arranged such that the obtuse angles of the triangular n ⁺⁺ type semiconductor regions 3 and 4 face the corners of the semiconductor chip SC.

The semiconductor chip SC has an n ⁺ type semiconductor region (first conductive type fourth semiconductor region) 5. The n ⁺ -type semiconductor territory 5 is apart from each of the two n ⁺⁺ type semiconductor regions 3 and 4, through the p ⁺ -type semiconductor region 2 from the first main surface of the p ⁺ -type semiconductor region 2 and it is formed further above n ⁺⁺ type semiconductor region 1 in contact (or reach) the n ⁺⁺ type semiconductor region 1 in a state of being electrically connected, by selectively diffused.

Further, the semiconductor chip SC is among the two ^{n ++} type semiconductor regions 3 and ^4, a first electrode 8 which is ohmic connected to the ^{n ++} type semiconductor region ^3, the is ohmic connected to the ^{n ++} type semiconductor region 4 Two electrodes 9 and a third electrode 10 ohmically connected to the second main surface of the n ⁺⁺ type semiconductor region 1 are provided.

The first electrode 8 is formed on the n ⁺⁺ type slightly larger flat, substantially triangular shape than the semiconductor region 3 is disposed so as to cover the n ⁺⁺ type semiconductor region 3. The first electrode 8 is ohmically connected to the n ⁺⁺ type semiconductor region 3 through an opening 11a opened in the first passivation film 11 deposited on the first main surface.

The second electrode 9 has a main part 9a and a connection part 9b. Main portion 9a of the second electrode 9 is formed on the n ⁺⁺ type semiconductor region slightly larger flat, substantially triangular shape than 4, is disposed so as to cover the n ⁺⁺ type semiconductor region 4. The main portion 9 a of the second electrode 9 is ohmically connected to the n ⁺⁺ type semiconductor region 4 through an opening 11 b opened in the passivation film 11. On the other hand, the connection portion 9b of the second electrode 9 extends from each of the two acute corner portions of the main portion 9a to a position overlapping the n ⁺ type semiconductor region 5 at the corner portion of the semiconductor chip SC, and opens to the passivation film 11. Through the opened opening 11c, the n ⁺ type semiconductor region 5 is ohmically connected. That is, the second electrode 9 is electrically connected to the n ⁺ -type semiconductor region 5 through the connecting portion 9b, is connected through it to the n ⁺⁺ type semiconductor region 1 electrically, yet a third electrode of the second main surface 10 is electrically connected. Thus, the third electrode 10 is designed to have the same potential as the second electrode 9. Reference numeral 12 denotes a second passivation film, which is formed on the first passivation film 11, the first electrode 8, and the second electrode 9, and a part of the first electrode 8 and the second electrode 9 is exposed for electrode extraction. Such openings 12a and 12b are provided.

Incidentally, in Embodiment 1, n ⁺⁺ type semiconductor regions 3 and 4 and the adjacent its, n ⁺⁺ type semiconductor region 1 lifetime control region over a wide range of p ⁺ -type semiconductor region 2 between the 13 Is formed. This lifetime control region 13, the n ⁺⁺ type semiconductor region 3 that is ohmic connected to at least the first electrode 8 because of the characteristics described below, the is between the n ⁺⁺ type semiconductor region 1 p ⁺ Preferably, it is formed in the type semiconductor region 2. The lifetime control region 13 is a region for controlling (shortening) the so-called lifetime until the excess fractional carriers in the semiconductor disappear due to recombination. In the lifetime control area 13, a lifetime killer is introduced. The lifetime killer is made of, for example, a light element such as helium ion or proton, or a heavy metal such as gold or platinum. Although this lifetime killer itself may contribute to the control (shortening) of the lifetime, it itself does not contribute directly but changes into the semiconductor crystal structure by being introduced into the semiconductor (Si). (For example, crystal defects) may contribute to lifetime control (shortening).

  Next, the operation of the bidirectional planar diode of the first embodiment formed on such a semiconductor chip SC will be described.

First, problems found by the inventors will be described. In the absence of the lifetime control region 13, when a voltage is applied so that the first electrode 8 is positive and the third electrode 10 is negative, a pn junction composed of the p + -type semiconductor region 2 and the n ⁺⁺ -type semiconductor region 3 is applied. Are reversely biased, and a pn junction composed of the p ⁺ type semiconductor region 2 and the n ⁺⁺ type semiconductor region 4 and a pn junction composed of the p ⁺ type semiconductor region 2 and the n ⁺⁺ type semiconductor region 1 are forward biased.

Now, consider an npn transistor structure comprising an n ⁺⁺ type semiconductor region 3, a p ⁺ type semiconductor region 2, and an n ⁺⁺ type semiconductor region 1. When a breakdown occurs when a positive voltage is applied to the first electrode 8 and a negative voltage is applied to the third electrode 10, a breakdown phenomenon occurs when the p ⁺ type semiconductor region 2 assumed to be a base is opened in the npn transistor structure. Can be considered. In this state, the leak current generated at the reverse bias junction accelerates the forward bias of the pn junction of the n ⁺⁺ type semiconductor region 1 serving as the emitter of the transistor and the p ⁺⁺ semiconductor region 2 serving as the base, and the leak current is purely a diode. Compared to increase. Furthermore, electrons injected from the n ⁺⁺ type semiconductor region 1 serving as the emitter of the pn junction serving as the forward bias junction are minority carriers in the p ⁺ type semiconductor region 2 serving as the p base region. When electrons, which are injected minority carriers, reach the depletion layer, there is a multiplication effect in the depletion layer where the electric field strength is strong. Therefore, the leak current suddenly becomes infinitely large at a voltage value lower than the breakdown voltage of the pn junction. A decrease in breakdown voltage due to so-called transistor operation is observed.

The main reason for this is that injected minority carriers reach the depletion layer. To prevent this, either increase the base width or reduce (shorten) the lifetime of minority carriers. Thus, it is necessary to devise a method for preventing the injected minority carriers from reaching the depletion layer. When the base width is increased, the breakdown voltage drop due to the transistor operation can be prevented. However, the thickness of the p ⁺ type semiconductor region 2 must be increased in the structure shown in FIG. 2, and the p ⁺ type semiconductor region 2 is formed by epitaxial growth. In this case, there is a problem that not only the thickness of the epitaxial growth layer having a thickness that can originally obtain a diode breakdown voltage is required, but also the time for forming the n ⁺ -type semiconductor region 5 for connection described above becomes very long.

Therefore, in the first embodiment, the lifetime control region 13 for electrons serving as minority carriers in the p ⁺ type semiconductor region 2 is provided so that the electrons that are injected minority carriers do not reach the depletion layer. As a result, the current amplification factor in the pnp structure or the npn structure transistor structure formed by the n ⁺⁺ type semiconductor region 1, the p ⁺ type semiconductor region 2, and the n ⁺⁺ type semiconductor regions 3 and 4 can be reduced. Since the transistor operation can be prevented, the breakdown voltage of the bidirectional planar diode can be improved. According to the present inventor, the lifetime is shortened by providing the lifetime control region 13 by ion implantation of light metal other than impurities used in normal diffusion, or by introducing heavy metals, compared to the case where lifetime control is not performed. It was found that the breakdown voltage drop due to the transistor operation can be prevented. Further, it has been found that the secondary breakdown of the transistor at a high current density can be reduced and the reliability is very high.

  Next, an example of a method for manufacturing the bidirectional planar diode of the first embodiment will be described with reference to FIG. FIGS. 3A to 3E are cross-sectional views after the main manufacturing process of the bidirectional planar diode shown in FIGS.

  FIG. 3A shows a cross-sectional view of the main part of the semiconductor wafer during the manufacturing process of the bidirectional planar diode of the first embodiment. The semiconductor wafer is a flat semiconductor plate having a substantially circular shape, and the semiconductor chip SC is formed by dividing (cutting) the semiconductor wafer into a plurality of pieces. The first main surface of the semiconductor chip SC corresponds to the first main surface of the semiconductor wafer, and the second main surface of the semiconductor chip SC corresponds to the second main surface of the semiconductor wafer.

Here, first, a p ⁺ type semiconductor region 2 is formed by epitaxial method on an n ⁺⁺ type semiconductor region 1 having a high impurity concentration, and then, for example, silicon oxide (SiO ₂ ) is formed on the p ⁺ type semiconductor region 2. An insulating film 15 is formed. Subsequently, a part of the insulating film 15 is removed by a normal photolithography (a series of steps including application of a photoresist film, exposure and development) technique and an etching technique to form an opening 15a. Thereby, the formation region of the n ⁺ type semiconductor region 5 is exposed from the insulating film 15. After that, for example, phosphorus (P) is diffused (introduced) through the opening 15a of the insulating film 15 so as to contact (reach) the n ⁺⁺ type semiconductor region 1 from the first main surface of the p ⁺ type semiconductor region 2. Then, the n ⁺ type semiconductor region 5 is selectively formed.

Next, in FIG. 3B, after the insulating film 15 shown in FIG. 3A is removed, an insulating film 16 made of silicon oxide is newly formed. Subsequently, a part of the insulating film 16 is removed by a normal photolithography technique and an etching technique to form openings 16a and 16b. Thereafter, for example, phosphorus (P) is diffused (introduced) through the openings 16a and 16b, thereby extending n from the first main surface of the p ⁺ type semiconductor region 2 and the n ⁺ type semiconductor region 5 to a desired depth. ^{The ++} type semiconductor regions 3 and 4 are selectively formed. The surface concentration of the n ⁺⁺ type semiconductor regions 3 and 4 is, for example, 1 × 10 ²⁰ / cm ³ per unit volume.

Next, in FIG. 3C, light element ions such as helium (He) ions or protons (H), which are lifetime killer, are used, for example, 5 by using lead or tungsten processed into a predetermined shape as a mask. Irradiation is performed at an irradiation energy of 1 × 10 ¹⁰ to 1 × 10 ¹³ / cm ² per unit area with an acceleration energy of ˜50 MeV. This forms a lifetime control region 13 over the inter-n ⁺⁺ type semiconductor regions 3 and 4 and its adjacent, to a wide range of p ⁺ -type semiconductor region 2 between the n ⁺⁺ type semiconductor region 1. In the lifetime control region 13, for example, a heavy metal such as gold (Au) or platinum (Pt) is deposited on the first main surface of the p ⁺ -type semiconductor region 2, and is predetermined at a temperature of 600 to 990 ° C., for example. It can also be formed by performing a time heat treatment (thermal diffusion treatment). Normally, when lifetime control is not performed, the lifetime of the p ⁺ -type semiconductor region 2 is 1 to 10 μs, but according to the first embodiment, it can be shortened to 0.1 to 0.5 μs.

  Subsequently, as shown in FIG. 3D, the insulating film 16 formed in the above process is removed, a new oxide film is formed by a thermal oxidation method or a CVD method, and a phosphor glass (PSG) film is further formed. Is deposited to form the first passivation film 11. Thereafter, the openings 11a to 11c shown in FIG. 1 are formed in a part of the first passivation film 11 by photolithography technique and etching technique, and then aluminum or silicon-containing aluminum is vapor-deposited on the surface. The first electrode 8 and the second electrode 9 are formed by patterning using a lithography technique and an etching technique. Thereafter, a plasma silicon nitride film which is the second passivation film 12 is formed on the first main surface of the semiconductor wafer, and is patterned by a normal photolithography technique and an etching technique, so that one of the first electrode 8 and the second electrode 9 is obtained. Expose the part.

  Thereafter, as shown in FIG. 3E, the third electrode 10 is formed by depositing, for example, gold or gold-antimony alloy on the second main surface of the semiconductor wafer and then performing heat treatment at, for example, 300 to 450 ° C. To do.

Next, FIG. 4 is a partially broken sectional view showing a package structure in which the bidirectional planar diode of the first embodiment is sealed with a mold resin. The semiconductor chip SC on which the bidirectional planar diode is formed has a third electrode 10 on the back surface (second main surface) electrically connected to the lead electrode 21a through the solder 20 on the lead electrode 21a. Has been implemented. Further, the first electrode 8 on the first main surface of the semiconductor chip SC is electrically connected to the lead electrode 21b through the wire 22. The entire semiconductor chip SC and wire 22 and part of the lead electrodes 21 a and 21 b are sealed with a mold resin 23. Part of the lead electrodes 21a and 21b is exposed from the same surface of the mold resin 23, and a diode DP having a surface mount type package configuration is formed. According to the first embodiment as described above, since the diode can be incorporated into a small package having a volume of 1 mm ³ or less, for example, the size and weight of the component can be reduced.

  Next, FIG. 5 is a diagram showing the characteristics of the bidirectional planar diode of the first embodiment. In this figure, the symbol W0 indicates the breakdown characteristic of the bidirectional planar diode that does not use the technique of the first embodiment, and the symbol W1 indicates the breakdown characteristic when the lifetime killer of the first embodiment is introduced. Yes. As shown in this figure, when the voltage is indicated by W0, the voltage is about 6.5V, and when a current of about 1 mA flows, a phenomenon of snapback is observed due to transistor operation. However, a lifetime control region 13 is provided. Therefore, as shown by the symbol W1, even when the current flowed 100 mA, the transistor operation did not appear, and the breakdown voltage was as high as 7V.

(Embodiment 2)
In the second embodiment, a modified example of the connection configuration between the second electrode on the first main surface of the semiconductor chip and the third electrode on the second main surface of the semiconductor chip will be described.

  6 is a plan view seen from the top surface of a semiconductor chip having a bidirectional planar diode according to another embodiment of the present invention, and FIG. 7 is a BB line of the semiconductor chip having the bidirectional planar diode of FIG. FIG. 8 is a cross-sectional view taken along the line CC of the semiconductor chip having the bidirectional planar diode of FIG. In the plan view of FIG. 6, a part is hatched to make the drawing easy to see.

The second embodiment is different from the first embodiment in that the method of taking out the electrodes is simplified. That is, in the first embodiment, as a means for connecting the second electrode 9 and the third electrode 10 to the same potential, the connecting portion 9b of the second electrode 9 is extended to the corner of the semiconductor chip SC, and there is an opening 11c. A method of connecting to the n ⁺ -type semiconductor region 5 through is shown. On the other hand, in the second embodiment, when the n ⁺ type semiconductor region 5 is diffused, a part of the n ⁺ type semiconductor region 4 is included and selectively from the first main surface of the p ⁺ type semiconductor region 2. It is formed by diffusing. That is, in the second embodiment, in the vicinity of one corner of the semiconductor chip SC, the n ⁺ type semiconductor region 5 extends in the direction of the center of the semiconductor chip SC, and is substantially the same as the n ^{+ +} type semiconductor region 4 having a substantially triangular shape in plan view. In the right-angled portion, it overlaps both in plan and in cross section, and is electrically connected directly to the n ⁺⁺ type semiconductor region 4. Reference numeral 25 denotes an overlapping portion of the n ⁺⁺ type semiconductor region 4 and the n ⁺ type semiconductor region 5. By providing such an overlapping portion 25 of the diffusion layer, the n ⁺⁺ type semiconductor region 4 is electrically connected to the n ⁺ type semiconductor region 5 and further electrically connected to the n ⁺⁺ type semiconductor region 1. Yes. Thus, the second electrode 9 on the first main surface of the semiconductor chip SC and the third electrode 10 on the second main surface of the semiconductor chip SC are designed to be electrically connected to have the same potential.

By adopting such a configuration, the opening 11c shown in FIG. 1 of the first embodiment is unnecessary, and the connection region between the second electrode 9 and the n ⁺⁺ type semiconductor region 5 in the first embodiment is used. Can be eliminated. Accordingly, in the case of the second embodiment, the plane area of the n ⁺⁺ type semiconductor regions 3 and 4 can be made larger than in the case of the first embodiment, so that the current path area through which the main current flows is increased. Can do. For this reason, since current capacity can be increased, usable power can be increased. In addition, the manufacturing process of the bidirectional planar diode can be simplified.

(Embodiment 3)
In the third embodiment, a case where the lifetime control region described in the first embodiment is provided in the configuration of the second embodiment will be described.

  FIG. 9 is a plan view seen from the top surface of a semiconductor chip having a bidirectional planar diode according to another embodiment of the present invention, and FIG. 10 is a BB line of the semiconductor chip having the bidirectional planar diode of FIG. FIG. 11 is a cross-sectional view taken along the line CC of the semiconductor chip having the bidirectional planar diode of FIG. In addition, in the plan view of FIG. 9, a part is hatched to make the drawing easy to see.

In the third embodiment, the lifetime control region 13 is formed in the p ⁺ type semiconductor region 2 in the configuration of the second embodiment. The lifetime control region 13 is formed in the same manner as in the first embodiment, but is formed so as not to overlap the n ⁺ type semiconductor region 5. In other words, the lifetime control region 13 is formed in the p ⁺ type semiconductor region 2 away from the n ⁺ type semiconductor region 5. This is because the flow resistance is increased current at the n ⁺ -type semiconductor region 5 lifetime control region 13 to the n ⁺ -type semiconductor region 5 is formed is hindered. The other formation methods and operational effects of the lifetime region 13 are the same as those in the first embodiment.

(Embodiment 4)
12 is a plan view seen from the top surface of a semiconductor chip having a bidirectional planar diode according to another embodiment of the present invention, and FIG. 13 is a DD line of the semiconductor chip having the bidirectional planar diode of FIG. FIG. In the plan view of FIG. 12, hatching is given to a part in order to make the drawing easy to see.

The bidirectional planar diode of the fourth embodiment is different from that of the third embodiment in that the p ⁺⁺ type semiconductor region (fifth semiconductor region) surrounds the n ⁺⁺ type semiconductor region 3 in the p ⁺ type semiconductor region 2. 28 is formed. The p ⁺⁺ type semiconductor region 28 is formed, for example, by selectively diffusing boron (B) as an impurity from the first main surface of the p ⁺ type semiconductor region 2. The impurity concentration of the p ⁺⁺ type semiconductor region 28 is higher than the impurity concentration of the p ⁺ type semiconductor region 2. Further, the junction depth of the p ⁺⁺ type semiconductor region 28 is the same as or slightly deeper than the junction depth of the n ⁺⁺ type semiconductor regions 3 and 4. The p ⁺⁺ type semiconductor region 28 is formed outside the outer periphery of the first electrode 8 when viewed in plan.

By providing such a p ⁺⁺ type semiconductor region 28, the reliability of the bidirectional planar diode can be improved. That is, when a voltage is applied between the first electrode 8 and the third electrode 10 such that the first electrode 8 is positive and the third electrode 10 is negative, the n ⁺⁺ type semiconductor region 3 and the p ⁺ type semiconductor are applied. A pn junction composed of the region 2 is reverse-biased, and a depletion layer extending from the pn junction extends to the p ⁺ type semiconductor region 2. Here, when a planar diode is operated in a normal operation, a depletion layer is formed on the semiconductor surface (first main surface) due to the potential in the passivation film or on the passivation film, and the depletion layer spreads from the inside to the surface. May grow. When the p base surface formed of the npn transistor structure including the n ⁺⁺ type semiconductor region 3, the p ⁺ type semiconductor region 2, and the n ⁺⁺ type semiconductor region 4 is changed to a depletion layer, the surface of the p ⁺ type semiconductor region 2 serving as a p base is obtained. The neutral region becomes narrow, minority carriers injected from the n ⁺⁺ type semiconductor 4 operating as an emitter are likely to reach the depletion layer, and there is a concern that the breakdown voltage is lowered due to transistor operation.

In contrast, by providing the ^{p ++} type semiconductor region 28 as in the present embodiment 4, the depletion layer extending from the pn junction, it is possible to stop at this ^{p ++} type semiconductor region ^{28, p ++} type semiconductor The first main surface of the p ⁺ type semiconductor 2 in the neutral region between the region 28 and the n ^{+ +} type semiconductor region 4 can be maintained as the neutral region. Therefore, since the transistor operation on the first main surface of the p ⁺ type semiconductor 2 can be prevented, a highly reliable bidirectional planar diode can be obtained. Therefore, the effects described in the second and third embodiments can be achieved with high reliability.

(Embodiment 5)
14 is a plan view seen from the top surface of a semiconductor chip having a bidirectional planar diode according to another embodiment of the present invention, and FIG. 15 is an EE line of the semiconductor chip having the bidirectional planar diode of FIG. FIG. In addition, in the plan view of FIG. 14, hatching is given to a part in order to make the drawing easy to see.

The bidirectional planar diode of the fifth embodiment is different from that of the third embodiment in that the p ⁺ type semiconductor region 2 and the n ⁺⁺ type semiconductor region 3 or the n ⁺⁺ type semiconductor region 4 (here, n ⁺⁺ type semiconductor). An n ⁺ type semiconductor region (sixth semiconductor region) 30 is formed at the terminal portion (outer peripheral portion) of the pn junction including both of the regions 3 and 4, and p on the first main surface of the p ⁺ type semiconductor region 2 The p ⁺ / n ⁺⁺ junction formed by the + type semiconductor region 2 and the n ⁺⁺ type semiconductor region 3 or the n ⁺⁺ type semiconductor region 4 is changed to a p ⁺ / n ⁺ / n ⁺⁺ junction, and the n ⁺⁺ type semiconductor This is because a curvature portion by the n ⁺ type semiconductor region 30 is formed at the junction end point (outer peripheral portion) of the region 3 or the n ^{+ +} type semiconductor region 4.

The n ⁺ type semiconductor region 30 is formed by selectively diffusing phosphorus (P) or arsenic (As) from the first main surface of the p ⁺ type semiconductor region 2, for example. The impurity concentration of the n ⁺ type semiconductor region 30 is lower than the impurity concentration of the n ^{+ +} type semiconductor regions 3 and 4. Further, the junction depth of the n ⁺ type semiconductor region 30 is deeper than the junction depth of the n ^{+ +} type semiconductor regions 3 and 4.

By providing such an n ⁺ -type semiconductor region 30, for example, the n ⁺ -type semiconductor region 30 from the breakdown voltage of a pn junction made up of the n ⁺ -type semiconductor region 3 or the n ⁺ -type semiconductor region 4 and the p ⁺ -type semiconductor region 2. And the p ⁺ type semiconductor region 2 can increase the breakdown voltage of the pn junction. Therefore, when the breakdown voltage of the pn junction composed of the n ^{+ +} type semiconductor region 3 or the n ^{+ +} type semiconductor region 4 and the p ⁺ type semiconductor region 2 is used bidirectionally, the fluctuation of the breakdown voltage due to the shape effect of the pn junction is prevented. Therefore, an effect that a predetermined breakdown voltage is easily obtained can be obtained.

(Embodiment 6)
16 incorporates a passive component such as a capacitor CP, a resistor RP, and an inductance LP having the same package configuration as that of FIG. 4 in addition to the bidirectional planar diode DP having the package configuration illustrated in FIG. 4 as one diode module DM. Here is an example. FIG. 17 shows a cross section of the main part of the diode module DP shown in FIG.

  Reference numeral 33 denotes a lead electrode when used as a module. The lead electrode 33 is electrically connected to the lead electrodes 21a and 21b of the bidirectional planar diode DP shown in FIG. 4 via solder, for example. Similarly, other passive components such as the capacitor CP, the resistor RP, and the inductance LP are electrically connected to each lead electrode and the lead electrode 33 of the diode module DM by soldering or the like. Such a bidirectional planar diode DP, capacitor CP, resistor RP and inductance LP, and part of the lead electrode 33 are covered with mold resins 34a and 34b. Thereby, the diode module DM is formed.

  All of these passive components are being modularized with the recent spread of mobile devices. As described above, the bidirectional planar diode DP according to the present embodiment is suitable for miniaturization, and constitutes a diode module DM incorporating a resistor RP, an inductance LP, and a capacitor CP, which are passive components. Suitable for

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment, the case where the present invention is applied to a bidirectional planar type diode having a surface mount type package configuration has been described. However, the present invention is not limited to this, and for example, the bidirectional lead diode having an axial lead type package configuration is also applicable. Applicable.

  The present invention can be applied to the diode manufacturing industry.

It is the top view seen from the upper surface of the semiconductor chip which has a bidirectional | two-way planar type diode which is one embodiment of this invention. It is sectional drawing of the AA line of the semiconductor chip which has the bidirectional | two-way planar type diode of FIG. (A)-(e) is sectional drawing after the main manufacturing processes of the bidirectional | two-way planar type diode shown in FIG.1 and FIG.2. It is a partially broken sectional view which shows the mode of the package structure which sealed the bidirectional | two-way planar type diode of FIG. 1 with mold resin. It is a characteristic view which shows the characteristic of the bidirectional | two-way planar type diode of FIG. It is the top view seen from the upper surface of the semiconductor chip which has the bidirectional | two-way planar type diode which is other embodiment of this invention. It is sectional drawing of the BB line of the semiconductor chip which has a bidirectional | two-way planar type diode of FIG. FIG. 7 is a cross-sectional view taken along line CC of a semiconductor chip having the bidirectional planar diode of FIG. It is the top view seen from the upper surface of the semiconductor chip which has the bidirectional | two-way planar type diode which is other embodiment of this invention. It is sectional drawing of the BB line of the semiconductor chip which has a bidirectional | two-way planar type | mold diode of FIG. FIG. 10 is a cross-sectional view of the semiconductor chip having the bidirectional planar diode of FIG. 9 taken along the line CC. It is the top view seen from the upper surface of the semiconductor chip which has the bidirectional | two-way planar type diode which is other embodiment of this invention. It is sectional drawing of the DD line | wire of the semiconductor chip which has a bidirectional | two-way planar type diode of FIG. It is the top view seen from the upper surface of the semiconductor chip which has the bidirectional | two-way planar type diode which is other embodiment of this invention. It is sectional drawing of the EE line | wire of the semiconductor chip which has a bidirectional | two-way planar type diode of FIG. FIG. 5 is a partially cutaway plan view of a diode module including a bidirectional planar diode having the package configuration described in FIG. 4 and other passive components. It is principal part sectional drawing of the diode module shown in FIG.

Explanation of symbols

1 n ⁺⁺ type semiconductor region (first semiconductor region)
2 p ⁺ type semiconductor region (second semiconductor region)
3 n ⁺⁺ type semiconductor region (third semiconductor region)
4 n ⁺⁺ type semiconductor region (third semiconductor region)
5 n ⁺ type semiconductor region (fourth semiconductor region)
8 1st electrode 9 2nd electrode 9a Main part 9b Connection part 10 3rd electrode 11 1st passivation film 11a, 11b, 11c Opening part 12 2nd passivation film 13 Lifetime control area | region 15 Insulating film 15a Opening part 16 Insulating film 16a , 16b Opening 20 Solder 21a, 21b Lead electrode 22 Wire 23 Mold resin 25 Overlapping portion 28 p ⁺⁺ type semiconductor region (fifth semiconductor region)
30 n ⁺ type semiconductor region (sixth semiconductor region)
33 Lead electrodes 34a, 34b Mold resin SC Semiconductor chip DP Diode DM Diode module CP Capacitor RP Resistance LP Inductance

Claims (5)

A semiconductor chip having a first main surface and a second main surface located opposite to each other along the thickness direction;
The semiconductor chip is
A first conductivity type first semiconductor region having the second main surface;
A second semiconductor region formed on the first semiconductor region and having a second conductivity type opposite to the first conductivity type and having the first main surface;
Two first-conductivity-type third semiconductor regions provided on the first main surface of the second semiconductor region so as to be separated from each other;
The second semiconductor region is provided apart from each of the first semiconductor regions of the first conductivity type, penetrates the second semiconductor region from the first main surface of the second semiconductor region, and further contacts the first semiconductor region. A fourth semiconductor region of the first conductivity type provided in
A first electrode ohmically connected to one third semiconductor region of the two first conductivity type third semiconductor regions;
A second electrode ohmically connected to the other third semiconductor region of the two first conductive type third semiconductor regions and the fourth semiconductor region;
A third electrode ohmically connected to the second main surface of the first semiconductor region,
A bidirectional planar diode characterized in that a lifetime killer is introduced into the second semiconductor region between the one third semiconductor region ohmic-connected to the first electrode and the first semiconductor region. . A semiconductor chip having a first main surface and a second main surface located opposite to each other along the thickness direction;
The semiconductor chip is
A first conductivity type first semiconductor region having the second main surface;
A second semiconductor region formed on the first semiconductor region and having a second conductivity type opposite to the first conductivity type and having the first main surface;
Two first-conductivity-type third semiconductor regions provided on the first main surface of the second semiconductor region so as to be separated from each other;
A first electrode ohmically connected to one third semiconductor region of the two first conductivity type third semiconductor regions;
The second semiconductor region is provided so as to overlap a part of the other third semiconductor region of the two first conductivity type third semiconductor regions, and penetrates the second semiconductor region from the first main surface of the second semiconductor region. And a fourth semiconductor region of a first conductivity type provided so as to be in contact with the first semiconductor region;
A second electrode ohmically connected to the other third semiconductor region of the two first conductive type third semiconductor regions and the fourth semiconductor region;
A third electrode ohmically connected to the second main surface of the first semiconductor region,
A bidirectional planar diode characterized in that a lifetime killer is introduced into the second semiconductor region between the one third semiconductor region ohmic-connected to the first electrode and the first semiconductor region. . 3. The bidirectional planar diode according to claim 1, wherein an impurity higher than the second semiconductor region is provided at a position surrounding the one third semiconductor region ohmic-connected to the first electrode. 5. A bidirectional planar diode comprising a second conductive type fifth semiconductor region having a concentration at a desired depth from the first main surface of the second semiconductor region. In the bidirectional planar diode according to any one of claims 1, 2 or 3, wherein each of the surrounding position of the two third semiconductor region of the first conductivity type, said third lower than the semiconductor region impurity A sixth conductive region having a first conductivity type having a concentration is provided so as to be in contact with each of the third semiconductor regions and at a desired depth from the first main surface of the second semiconductor region. Bidirectional planar diode. 5. The bidirectional planar diode according to claim 1, wherein the bidirectional planar diode is sealed with a molding resin. 6.

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