JPH0226079A - Trigger diode - Google Patents

Trigger diode

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Publication number
JPH0226079A
JPH0226079A JP17661388A JP17661388A JPH0226079A JP H0226079 A JPH0226079 A JP H0226079A JP 17661388 A JP17661388 A JP 17661388A JP 17661388 A JP17661388 A JP 17661388A JP H0226079 A JPH0226079 A JP H0226079A
Authority
JP
Japan
Prior art keywords
trigger diode
layer
junction
conductivity type
negative resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17661388A
Other languages
Japanese (ja)
Inventor
Yasuhiko Ochiai
落合 康彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17661388A priority Critical patent/JPH0226079A/en
Publication of JPH0226079A publication Critical patent/JPH0226079A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a trigger diode of favorable negative resistance characteristics and a high yield by making a p-n junction having a negative resistance between a base region and a high density layer. CONSTITUTION:A p<+> channel stopper 2 and a scribe layer 4 are formed at the same time on an n-type silicon substrate 1, forming a p-type base diffusion region 3 and an n<+> type diffusion layer 5. With a positive voltage applied to a plated electrode 13 and a negative one to an deposited electrode 12, a p-n<+> junction part 9 is reversely biased while a p-n junction part 8 biased forward. In this manner, an opposite conductivity type diffusion layer is deposited on one principal face of the one conductivity type semiconductor substrate 1 and the high density diffusion layer 5 is deposited on the conductivity type semiconductor substrate 1, to make a trigger diode having negative resistance characteristics in one direction. By this method, the reduction of a breakover current IBO and the increase of an yield can be achieved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はトリガダイオードに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to trigger diodes.

〔従来の技術〕[Conventional technology]

サイリスタ応用の普及に伴い、トリガ回路の簡易化及び
経済設計が要望されてきた。
With the spread of thyristor applications, there has been a demand for simpler and more economical designs for trigger circuits.

ダイアック(DIAC)は、本来は双方向三端子サイリ
スタのトリガダイオードとして設計されたが、上述の要
望に近いので従来から電子ジャー等の家庭電化製品に使
用する逆阻止三端子サイリスタにも活用されてきた。
DIAC was originally designed as a trigger diode for bidirectional three-terminal thyristors, but since it meets the above requirements, it has also been used for reverse-blocking three-terminal thyristors used in home appliances such as electronic jars. Ta.

例えば、サイリスタ・エレクトロニクス編集委員命綱、
サイリスクエレクトロニクス5、サイリスタの応用、下
巻、第310頁、丸善(昭和49年5月)に応用回路と
動作が記載されている。
For example, Thyristor Electronics Editorial Committee Lifeline,
Application circuits and operations are described in Thyrisk Electronics 5, Thyristor Applications, Volume 2, page 310, Maruzen (May 1971).

第4図は従来のトリガダイオードの一例の断面図である
FIG. 4 is a cross-sectional view of an example of a conventional trigger diode.

次に、ダブルヒートシンク(DHD)型のトリガダイオ
ードの製造方法を説明する。
Next, a method for manufacturing a double heat sink (DHD) type trigger diode will be described.

先ず、厚さ200μmのp型シリコン基板15の両主面
よりp+型チャネルストッパ16.。
First, p+ type channel stoppers 16. .

16bを形成する。16b.

これは、p型シリコン基板15が低濃度なため、ガラス
パッケージに封入する際にガラスからのアルカリイオン
の汚染によってp型シリコン基板15の表面がn型に反
転し、チャネルリーク不良となるのを防止するためであ
る。
This is because the p-type silicon substrate 15 has a low concentration, so when it is sealed in a glass package, the surface of the p-type silicon substrate 15 is inverted to n-type due to contamination with alkali ions from the glass, resulting in channel leakage defects. This is to prevent this.

次に、ダイシング時の目合せ用にp型シリコン基板15
の両生面か6n+型拡散層17.。
Next, a p-type silicon substrate 15 is used for alignment during dicing.
6n+ type diffusion layer 17. .

17b及びスクライブ層18a、18bを同時に形成す
る。
17b and scribe layers 18a and 18b are formed at the same time.

更に蒸着電極21−.21b及び銀のメツキ電極22−
.22bを両生面に形成する。
Furthermore, the vapor deposition electrode 21-. 21b and silver plating electrode 22-
.. 22b is formed on both sides.

第5図は第4図のトリガダイオードの電圧−電流特性図
である。
FIG. 5 is a voltage-current characteristic diagram of the trigger diode shown in FIG. 4.

例えばメツキ電極22.及び22bに正及び負の電位を
与えると、負性抵抗曲線N1はpn+接合部19.が逆
バイアス状態のブレークダウン電圧VB01のときに、
順バイアス状態にある反対側のpn+接合部19bから
p型シリコン基板15に注入された少数キャリアeが効
率良く増幅されて接合部19.に達することで得られる
For example, plating electrode 22. When positive and negative potentials are applied to pn+ junction 19. When is the breakdown voltage VB01 in reverse bias state,
Minority carriers e injected into the p-type silicon substrate 15 from the pn+ junction 19b on the opposite side, which is in a forward bias state, are efficiently amplified and transferred to the junction 19. Obtained by reaching .

また、トリガダイオードは両生面とも同じ構造を有して
いるために、負性抵抗特性N、及びN2は両方向に得ら
れている。
Further, since the trigger diode has the same structure on both sides, negative resistance characteristics N and N2 are obtained in both directions.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のトリガダイオードは、厚いp型シリコン
基板を使用しているためpn+接合部から注入された少
数キャリアが約厚さ200μmの対向するp n +接
合部に到達する前に再結合される確率が高く、この再結
合電流であるブレークオーバ電流IBOが大きいので、
負性抵抗特性すなわちトリガ特性が悪いという欠点があ
った。
Since the conventional trigger diode described above uses a thick p-type silicon substrate, the minority carriers injected from the pn+ junction are recombined before reaching the opposing pn+ junction, which is approximately 200 μm thick. Since the probability is high and the breakover current IBO, which is this recombination current, is large,
It had the disadvantage of poor negative resistance characteristics, that is, poor trigger characteristics.

またダイアックは、p型シリコン基板の両生面に接合部
があるためホトレジストによる拡散パターンの形成、蒸
着電極及びメツキ電極の形成工程を二度行なう必要があ
り、製造工程が長く、更に、ダイシングの際どちらか一
方の主面を粘着テープに貼り付けるが、銀のメツキ電極
があるため粘着テープとウェーハの接着性が悪く、その
面のペレットカケ不良が多発し歩留低下の大きな原因と
なっていた。
In addition, since DIAC has bonding parts on both sides of the p-type silicon substrate, it is necessary to perform the steps of forming a diffusion pattern using photoresist and forming vapor-deposited electrodes and plating electrodes twice, resulting in a long manufacturing process. Adhesive tape is attached to one of the main surfaces, but because of the silver plating electrode, adhesion between the adhesive tape and the wafer is poor, resulting in frequent pellet chipping defects on that surface, which is a major cause of decreased yield.

この様に、製造工程が長くかつ品質問題があった。As described above, the manufacturing process was long and there were quality problems.

本発明の目的は、負性抵抗特性が良くかつ歩留の良いト
リガダイオードを提供する;とにある。
An object of the present invention is to provide a trigger diode with good negative resistance characteristics and high yield.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のトリガダイオードは、−導電型の半導体基板の
一主面に拡散により形成された逆導電型のベース領域と
、該ベース領域内の上層に形成された一導電型の高濃度
層とを有し、かつ前記ベース領域と前記高濃度層とのp
n接合部が負性抵抗を有して構成されている。
The trigger diode of the present invention includes a base region of an opposite conductivity type formed by diffusion on one principal surface of a semiconductor substrate of a -conductivity type, and a high concentration layer of one conductivity type formed in an upper layer within the base region. and p between the base region and the high concentration layer.
The n-junction is configured to have negative resistance.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例の断面図、第2図は第1
図のトリガダイオードの電圧−電極特性図である。
FIG. 1 is a sectional view of the first embodiment of the present invention, and FIG. 2 is a sectional view of the first embodiment of the present invention.
FIG. 3 is a voltage-electrode characteristic diagram of the trigger diode shown in the figure.

第1図に示すように、まず不純物濃度が5×1015c
m−3程度のn型シリコン基板1に表面濃度が5X10
19C11−3のp++チャネルストッパ2とスクライ
ブ層4を同時に形成する。
As shown in Figure 1, first, the impurity concentration is 5×1015c.
The surface concentration is 5X10 on an n-type silicon substrate 1 of about m-3.
19C11-3 p++ channel stopper 2 and scribe layer 4 are formed at the same time.

p1型チャネルストッパ2は、ガラスパッケージに封止
する際に、ガラスからのアルカリイオンの汚染により後
に形成するn型拡散層3の表面がn型に反転しない様に
するために設けである。
The p1 type channel stopper 2 is provided to prevent the surface of the n-type diffusion layer 3 to be formed later from being inverted to n-type due to contamination of alkali ions from the glass when sealing in a glass package.

スクライブ層4のp+はチャネルストッパとしての効果
はないが、ダイシング時の目合せがし易い様に設けてお
く。
Although the p+ layer of the scribe layer 4 has no effect as a channel stopper, it is provided to facilitate alignment during dicing.

次にp型のベース拡散領域3を、p++チャネルストッ
パ2の表面から深さ約15μmで低濃度の3×1016
cm−3程度に形成する。
Next, a p-type base diffusion region 3 is formed at a depth of about 15 μm from the surface of the p++ channel stopper 2 with a low concentration of 3×10 16
Form to about cm-3.

その後、ベース拡散領域3の上層に深さ10μm2表面
濃度が2×1020CI11−3のn+型型数散層5形
成する。
Thereafter, an n+ type scattering layer 5 having a depth of 10 μm2 and a surface concentration of 2×10 20 CI11−3 is formed on the base diffusion region 3 .

従ってベース拡散領域3の深さdは約5μmとなる。Therefore, the depth d of the base diffusion region 3 is approximately 5 μm.

この時、n型シリコン基板1のもう一方の主面にも同時
に裏面のn型拡散層6を形成する。
At this time, the back n-type diffusion layer 6 is also formed on the other main surface of the n-type silicon substrate 1 at the same time.

これは、後に形成する蒸着電極12とのオーミック性を
良くするためである。
This is to improve the ohmic properties with the vapor deposition electrode 12 that will be formed later.

更に、n++散層らの表面に蒸着電極11゜12及びメ
ツキ電極13を形成する。
Furthermore, vapor deposition electrodes 11 and 12 and plating electrodes 13 are formed on the surface of the n++ diffused layer.

最後にガラスケースに入れ、DHDリードで挟んで封止
する。
Finally, place it in a glass case and seal it by sandwiching it between DHD leads.

次に本実施例のトリガダイオードの動作について説明す
る。
Next, the operation of the trigger diode of this embodiment will be explained.

第2図に示すように負性抵抗特性曲線Nが得られるのは
、メツキ電極13に正及び蒸着電極1°2に負電圧を印
加したときで、pn+接合部9は逆方向、pn接合部8
は順方向にバイアスされている。
As shown in FIG. 2, the negative resistance characteristic curve N is obtained when a positive voltage is applied to the plating electrode 13 and a negative voltage is applied to the vapor deposited electrode 1°2, the pn+ junction 9 is in the opposite direction, and the pn junction is in the opposite direction. 8
is forward biased.

ここでn型シリコン基板1から注入される少数キャリア
は、p + n接合部7よりもpn接合部8の方が注入
効率が高いので、主としてpn接合部8から注入される
Here, the minority carriers injected from the n-type silicon substrate 1 are mainly injected from the pn junction 8 because the injection efficiency is higher in the pn junction 8 than in the p + n junction 7.

ベース拡散層3に注入された少数キャリアは、約30v
のブレークオーバ電圧VB□で動作しているpn接合部
8へ到達する途中で、ある確率で再結合され再結合電流
のブレークオーバ電流IBOとなる。
The minority carriers injected into the base diffusion layer 3 are approximately 30V
On the way to the pn junction 8 which is operating at the breakover voltage VB□, it is recombined with a certain probability and becomes the breakover current IBO of the recombination current.

I 80は応用上小さい程良く、本発明によりトリガダ
イオードでは、ベース拡散領域3の厚さdが約5μmな
ので第4図の従来のn型シリコン基板15の約200μ
mの厚さDよりも小さいため再結合する確率が低く、従
ってIBOがI BOII 802よりも小さくできる
利点がある。
The smaller the I80, the better. In the trigger diode according to the present invention, the thickness d of the base diffusion region 3 is approximately 5 μm, so it is approximately 200 μm thick than that of the conventional n-type silicon substrate 15 shown in FIG.
Since the thickness D is smaller than the thickness D of m, the probability of recombination is low, so there is an advantage that the IBO can be smaller than the IBOII 802.

上述と逆方向、すなわちメツキ電極13に負。In the opposite direction to the above, that is, negative to the plating electrode 13.

蒸着電極12に正電圧を印加した場合は、p+ n接合
部7で決まり約80vの耐圧VflOの定電圧ダイオー
ド特性曲線Zを有する。
When a positive voltage is applied to the vapor deposition electrode 12, the p+n junction 7 has a constant voltage diode characteristic curve Z with a withstand voltage VflO of about 80V.

この場合、従来のダイアック応用回路で使用していた逆
阻止用ダイオードがあれば省略できる。
In this case, the reverse blocking diode used in conventional diac application circuits can be omitted.

本実施例によりトリガダイオードは、n型シリコン基板
1の一重部片側にのみpn接合部を形成するので、第4
図の従来のトリガダイオードに比べ以下の利点も得られ
る。
According to this embodiment, the trigger diode forms a pn junction only on one side of the single part of the n-type silicon substrate 1, so the fourth
The following advantages are also obtained compared to the conventional trigger diode shown in the figure.

(1)ホトレジストによる拡散パターンの形成及びメツ
キ電極の形成が一重部のみで良いため製造工程が短かく
なる。
(1) The manufacturing process is shortened because the formation of the diffusion pattern using photoresist and the formation of the plating electrode only need to be done in one part.

(2)メツキ電極は片側だけで良いためダイシングの際
使用する粘着テープと蒸着電極との密着性が良く、ダイ
シング時の欠は不良の発生が少なく、選別工数も少なく
て済むといった利点がある。
(2) Since only one side of the plating electrode is required, there is good adhesion between the adhesive tape used during dicing and the vapor-deposited electrode, and there are advantages in that defects during dicing are less likely to occur and the number of steps for sorting can be reduced.

第3図は本発明の第2の実施例の断面図である。FIG. 3 is a sectional view of a second embodiment of the invention.

トリガダイオードは、蒸着電極11.が第1図のメツキ
電極13及び蒸着電極11と異る点以外は第1の実施例
のトリガダイオードと同一である。
The trigger diode is connected to the vapor deposition electrode 11. is the same as the trigger diode of the first embodiment except that it is different from the plating electrode 13 and the vapor deposited electrode 11 in FIG.

従って、効果も同一である。Therefore, the effect is also the same.

さらに、銀のメツキ電極がAffの蒸着電極に代られた
ので、リードフレーム上にもマウントすることが出来る
Furthermore, since the silver plated electrode was replaced with an Aff evaporated electrode, it can also be mounted on a lead frame.

例えばこのトリガダイオードを小型樹脂封止半導体用パ
ッケージに封止することで、表面実装対応が可能となり
、高密度実装化の動きに十分対応することができるとい
った新たな効果もある。
For example, by sealing this trigger diode in a small resin-sealed semiconductor package, it becomes possible to support surface mounting, which has new effects such as being able to fully respond to the trend toward high-density packaging.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は、−導電型を有する半導体基
板の一主面側より逆導電型の拡散層を形成し、更に導電
型を有しかつ半導体基板より高濃度の拡散層を形成して
、一方向に負性抵抗特性を有するトリガダイオードを構
成するので、ブレークオード電流I BOが小さく、歩
留が高く経済的なトリガダイオードが得られる効果があ
る。
As explained above, the present invention forms a diffusion layer of an opposite conductivity type from one main surface side of a semiconductor substrate having a -conductivity type, and further forms a diffusion layer having a conductivity type and having a higher concentration than the semiconductor substrate. As a result, a trigger diode having a negative resistance characteristic in one direction is constructed, so that an economical trigger diode with a small break-off current IBO and a high yield can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例の断面図、第2図は第1
図のトリガダイオードの電圧−電流特性図、第3図は本
発明の第2の実施例の断面図、第4図は従来のトリガダ
イオードの一例の断面図、第5図は第4図のトリガダイ
オードの電圧−電流特性図である。 1・・・n型シリコン基板、3・・・ベース拡散領域、
5・・・n型拡散層、9・・・p+ n接合部、N・・
・負性抵抗曲線。
FIG. 1 is a sectional view of the first embodiment of the present invention, and FIG. 2 is a sectional view of the first embodiment of the present invention.
Figure 3 is a sectional view of the second embodiment of the present invention, Figure 4 is a sectional view of an example of a conventional trigger diode, and Figure 5 is the trigger diode shown in Figure 4. It is a voltage-current characteristic diagram of a diode. 1... N-type silicon substrate, 3... Base diffusion region,
5...n-type diffusion layer, 9...p+n junction, N...
・Negative resistance curve.

Claims (1)

【特許請求の範囲】[Claims] 一導電型の半導体基板の一主面に拡散により形成された
逆導電型のベース領域と、該ベース領域内の上層に形成
された一導電型の高濃度層とを有し、かつ前記ベース領
域と前記高濃度層とのpn接合部が負性抵抗を有するこ
とを特徴とするトリガダイオード。
a base region of an opposite conductivity type formed by diffusion on one main surface of a semiconductor substrate of one conductivity type, and a high concentration layer of one conductivity type formed in an upper layer within the base region, and the base region A trigger diode characterized in that a pn junction between the high concentration layer and the high concentration layer has negative resistance.
JP17661388A 1988-07-14 1988-07-14 Trigger diode Pending JPH0226079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17661388A JPH0226079A (en) 1988-07-14 1988-07-14 Trigger diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17661388A JPH0226079A (en) 1988-07-14 1988-07-14 Trigger diode

Publications (1)

Publication Number Publication Date
JPH0226079A true JPH0226079A (en) 1990-01-29

Family

ID=16016630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17661388A Pending JPH0226079A (en) 1988-07-14 1988-07-14 Trigger diode

Country Status (1)

Country Link
JP (1) JPH0226079A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06336256A (en) * 1993-05-28 1994-12-06 Yunikomu:Kk Fitting cap having side peripheral face
JP2004335758A (en) * 2003-05-08 2004-11-25 Sanken Electric Co Ltd Diode element and its manufacturing method
JP2007150085A (en) * 2005-11-29 2007-06-14 Renesas Technology Corp Bidirectional planer diode
JPWO2006022287A1 (en) * 2004-08-27 2008-05-08 松下電器産業株式会社 Surge protection semiconductor device
JP2020017766A (en) * 2019-10-31 2020-01-30 ローム株式会社 Semiconductor device
US11075263B2 (en) 2012-03-12 2021-07-27 Rohm Co, , Ltd. Semiconductor device, and method for manufacturing semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06336256A (en) * 1993-05-28 1994-12-06 Yunikomu:Kk Fitting cap having side peripheral face
JP2004335758A (en) * 2003-05-08 2004-11-25 Sanken Electric Co Ltd Diode element and its manufacturing method
JPWO2006022287A1 (en) * 2004-08-27 2008-05-08 松下電器産業株式会社 Surge protection semiconductor device
JP4642767B2 (en) * 2004-08-27 2011-03-02 パナソニック株式会社 Surge protection semiconductor device
JP2007150085A (en) * 2005-11-29 2007-06-14 Renesas Technology Corp Bidirectional planer diode
US11075263B2 (en) 2012-03-12 2021-07-27 Rohm Co, , Ltd. Semiconductor device, and method for manufacturing semiconductor device
US11862672B2 (en) 2012-03-12 2024-01-02 Rohm Co., Ltd. Semiconductor device, and method for manufacturing semiconductor device
JP2020017766A (en) * 2019-10-31 2020-01-30 ローム株式会社 Semiconductor device

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