JPH07120631B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device in a semiconductor silicon wafer, and in particular, the semiconductor device is an integrated circuit device, and circuit elements constituting an integrated circuit are separated by joining. A method suitable for forming in each of the semiconductor regions formed.

[Conventional technology]

As is well known, a large number of semiconductor devices are formed in a silicon wafer and then cut into chips. When the semiconductor device is an integrated circuit device, each chip has a larger number of semiconductor regions bonded and separated from each other. The circuit elements constituting the integrated circuit are divided and formed in the respective semiconductor regions and then connected to each other. As is well known, FIG. 6 is a partially enlarged view showing how one chip is divided into these semiconductor regions.

In the cross section of FIG. 6A, a semiconductor substrate 1 made of silicon
Is usually a p-type, and the n-type buried layer 2 having a high impurity concentration is diffused in a range corresponding to each semiconductor region on the surface of the substrate 1 and then the epitaxial layer 3 is a predetermined n-type. Grow to thickness. Then, by diffusing the p-type separation layer 4 having a high impurity concentration deeply from the surface of the epitaxial layer 3 until reaching the substrate 1 as shown in FIG. The epitaxial layer 3 is divided into a plurality of semiconductor regions. Circuit elements such as bipolar transistors and field effect transistors are formed in the semiconductor region 3, and a positive power supply voltage is applied to the n-type semiconductor region 3 during its operation, and the p-type substrate 1 is normally connected to the ground potential. To be done.

Therefore, a positive power supply voltage is applied in the reverse bias direction to the pn junction between the n-type semiconductor region 3 and the p-type substrate 1 and the isolation layer 4, which causes the potential of each semiconductor region 3 from the substrate 1. The semiconductor regions 3 and the semiconductor regions 3 are similarly separated from each other. The pattern of each semiconductor region 3 is usually a square as can be seen from FIG. 6 (b), but the area and the vertical and horizontal dimensional ratios are selected according to the type and number of circuit elements to be built therein. The layout of these semiconductor regions 3 in the chip is automatically assigned using a computer as is well known.

[Problems to be Solved by the Invention]

Since the p-type isolation layer 4 for junction isolation of the above-mentioned semiconductor region 3 needs to diffuse deeply with a high impurity concentration as described above, boron having a large diffusion coefficient is generally used as an impurity for that purpose. However, for example, when the thickness of the epitaxial layer to be divided into the semiconductor regions 3 is large, the dividing layer 4
When the go increasingly introducing boron amount for deep diffusion, becomes a semiconductor device particularly easily out characteristic defects in the integrated circuit device when the surface impurity concentration exceeds 5x10 ¹⁸ atoms / cm ^3, further surface impurity concentration of 5x10 ¹⁹ atoms If it exceeds / cm ³ , there is a problem that the non-defective rate decreases rapidly.

In pursuit of this cause, the impurity concentration and the diffusion depth of the semiconductor layers constituting the semiconductor device, particularly the n-type semiconductor layer, do not reach the predetermined values, and the cause is that the semiconductor layers are separated during thermal diffusion at high temperature. From layer 4, it was found that boron was mixed in the atmosphere and was an obstacle to diffusion. Previous 6th
This state is illustrated in FIG.

As shown, for example, the p-type layer 5 is diffused in the central semiconductor region 3, and the n-type layer 6 is diffused therein with a high impurity concentration. At the time of thermal diffusion of the n-type layer 6, the surface of the separation layer 4 which is a high boron concentration layer is covered with a so-called process oxide film 20 as shown in FIG. For example, phosphorus is diffused as an impurity for the shaping layer 6, but boron, which is a p-type impurity, is mixed from the separation layer 4 through the oxide film 20 into the diffusion atmosphere to hinder the diffusion of the n-type impurity. . Therefore, at this time, the oxide film 20 on the separation layer 4 is, so to speak, a boron supply source.

The fact that the oxide film in contact with a silicon semiconductor has a large so-called segregation coefficient for boron is described, for example, in Takao Abe, Masahiko Ogiri, Kenji Taniguchi, "Silicon Crystals and Doping," published by Maruzen, pp. 153-154. It has been conventionally known that p-type impurities, particularly boron, on the surface of a semiconductor which is in contact with the oxide film are easily absorbed by the oxide film due to segregation. FIG. 5 shows the result of measuring the segregation state of boron by the IMA (ion microanalyzer) method.
However, this figure shows that about 0.5 μm oxide film 2 is formed on the surface of the separation layer 4.
This is the result of measuring the distribution of the boron concentration c with respect to the depth d when a so-called phosphorus glass film (phosphorus silicate glass film) 22 having a thickness of 0 and 0.1 μm is attached. Can be considered to be equivalent to a single oxide film having a thickness of 0.6 μm. As can be seen from the figure, the boron concentration c increases from the separation layer 4 to the oxide film 20 at the interface between them by about one digit due to segregation, and further increases toward the surface of the oxide film. It is considered that the harmful boron is released from the surface of the oxide film having a very high impurity concentration.

Due to the influence of boron, the characteristics of the transistor are not sufficiently obtained, and the leakage current tends to increase the consumption current and cause current leakage between transistors in the integrated circuit device.
Judging from the leakage phenomenon, it can be seen that even the surface of the semiconductor region where the semiconductor layer is not formed is easily contaminated by the emitted boron. The problem of contamination of the semiconductor surface is particularly likely to occur when high concentration boron diffusion for a separation layer is performed by a solid diffusion method using boron nitride or a gas diffusion method using diborane, but the ion implantation method is used. When introducing boron, there is not much difference,
It confirms that the problem lies in the oxide film above it.

In order to solve such a problem, it is possible to remove the oxide film on it after performing high-concentration boron diffusion for the separation layer and attach it to a clean oxide film. Boron is sucked into the oxide film from the high boron concentration layer in each process in a relatively short time and becomes a pollution source, so it cannot be said that it is a very effective measure, and it is very difficult to reattach the oxide film in each high temperature heating process. This is troublesome and costly, and the boron diffused at regular intervals is sucked out one after another to lower the surface impurity concentration.

The present invention solves such a problem, and even if boron is accumulated in the silicon oxide film or the like on the high boron concentration layer such as the separation layer due to segregation, the reduction of the non-defective rate due to the re-diffusion thereof is effectively prevented. It is an object of the present invention to obtain a practical manufacturing method of a semiconductor device, especially an integrated circuit device, which can be manufactured.

[Means for Solving the Problems]

The present invention provides the maximum width of a diffusion pattern of a high boron concentration layer in which boron is diffused at a high surface impurity concentration like the above-mentioned separation layer and the surface is covered with a film containing silicon oxide during a high temperature heating process of a wafer. By unifying the size on the diffusion photomask to 20 μm or less, the above-mentioned object was successfully achieved.

The above method is useful when applied to a high boron concentration layer having a boron surface impurity concentration of 5 × 10 ¹⁸ atoms / cm ³ or more. Further, the limit value of the maximum width of the diffusion pattern of the high boron concentration layer in the above structure is preferably 20 μm in terms of the size on the photomask in the case of an integrated circuit device. Furthermore, in an integrated circuit device, the high boron concentration layer usually occupies 25% of the wafer.
%, But if this ratio is higher than this, after limiting the maximum width of the high boron concentration layer as described above,
Furthermore, the total area must be limited to at most 40% of the area of the wafer, preferably less than 35%.

[Action]

The present invention focuses on the fact that the range affected by the re-diffusion of boron from the silicon oxide film or the like on the high boron concentration layer is limited to a relatively small area in the vicinity of the high boron concentration layer. By significantly limiting the above configuration, the amount of boron contamination source in the silicon oxide film, etc. on it is reduced and the adverse effect of re-diffused boron on the periphery is reduced, and the reduction in the yield rate of semiconductor devices is substantially reduced. It has been successfully and effectively prevented. Therefore, according to the method of the present invention,
There is no need for extra work such as replacing the silicon oxide film as in the conventional case, and the problem can be solved without additional steps.

〔Example〕

Hereinafter, some embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment in which the method of the present invention is applied to a separation layer for a semiconductor region of an integrated circuit device. The same parts as those in FIG. The overlapping part will be omitted. FIG. 1 (a) is an XX cross section of the wafer 10 shown in the plan view of FIG. 1 (b), showing a state immediately after the p-type separation layer 4 as a high boron concentration layer is diffused. . A photomask 30 for diffusion of the separation layer 4 is shown in FIG.

The p-type separation layer 4 which is a high boron concentration layer in this embodiment
Is diffused to a boron concentration of, for example, about 10 ¹⁹ atoms / cm ^{3 by} a solid diffusion method, a gas diffusion method, or an ion implantation method as the case may be, and the silicon oxide film 20 formed thereon is a normal steam oxide film or a process oxide film. The thickness of the film is usually about 1 μm, and the bonro for the separation layer 4 is diffused through the window opened therein.

The diffusion pattern of the isolation layer 4 is hatched in the drawing corresponding to each semiconductor region 3 so that the maximum width Wm is 20 μm or less in this example as shown in the photomask 30 of FIG. Placement and area of 31 are decided. In the figure, the width of the separation layer pattern 32, which is a white background, shown by W1 to W3 is of course narrower than the maximum width Wm, and the minimum width W1 is usually 2 to 8 μm depending on the accuracy of the photo process and the thickness of the epitaxial layer. Is set between. FIG. 1 (b) corresponds to FIG. 6 (b), and as can be seen by comparing the two, in order to suppress the maximum width of the separation layer diffusion pattern 32 to 20 μm or less, for example, Semiconductor region 3 of FIG.
Pattern R2 is moved closer to pattern R1, and pattern R3
The area of has been expanded. Such pattern arrangement and size change can be easily performed by adding a maximum width constraint function to the pattern allocation software of the computer. When the maximum width cannot be restricted only by such a change, a pattern for a semiconductor region which is not actually used may be added as appropriate.

When the isolation layer 4 is formed by using the photomask 30 shown in FIG. 1C, boron is laterally diffused under the silicon oxide film 20 as shown in FIG. Layer 4
Is much wider than the width of the pattern 32 of the photomask 30, as shown in FIG. Since the lateral diffusion of boron depends on the diffusion depth of the separation layer 4 and can be almost the same as the thickness of the epitaxial layer, for example, when the thickness of the epitaxial layer is 10 μm, the actual maximum width of the separation layer 4 is 40 μm. Can be close.

FIG. 1D shows a state when the p-type layer 5 is formed in the semiconductor region 3, and the isolation layer 4 is a silicon oxide film as shown in the figure.
Window opened in silicon oxide film 20 while covered by 20
The p-type layer 5 is diffused through 21. At this time, the boron concentration of the silicon oxide film 20 on the separation layer 4 can reach about 10 ²⁰ atoms / cm ³ , but in the present invention, the process proceeds without changing it.

FIG. 2 shows an embodiment in which the method of the present invention is applied to the location of a scribe line for separating each chip for a semiconductor device from a wafer. The scribe line C is shown on the wafer 10 in FIG.
A bipolar transistor T1 and a field effect transistor T2 having a shaping layer 5 and an n-type layer 6 are built in. Wafer 10
Is divided into chips 11 and 12 along the scribe line C as shown in FIG. 7B. In order to prevent current leakage from the transistors T1 and T2 on these chips to the separation plane, It is necessary to interpose the separation layer 4 between the separation layer and the separation surface. Therefore, conventionally, the scribe line C is usually provided in the separation layer 4.

However, in order to separate the wafer into chips in the separation layer 4,
For the sake of the scribing work, the width of the separation layer 4 should be set to a wide range, usually 60 to 100 μm, and the amount of contaminating boron from the silicon oxide film 20 on the separation layer 4 cannot be neglected. The semiconductor region 3 is provided between the isolation layers 4 provided so as to respectively surround the periphery of
The scribe line C is set therein to limit the width of the separation layer 4 on both sides of the scribe line C to the maximum width or less. Although the area of each chip is slightly increased by providing the semiconductor region 3 for the scribe line C, the total area occupied by the separation layer 4 as a high boron concentration layer in the wafer is reduced and the chip in the integrated circuit device is reduced. This is very advantageous in reducing the rate of occurrence of characteristic defects of circuit elements that are likely to occur in the peripheral portion.

There is a high boron concentration layer other than the separation layer in the wafer, and there are monitor patterns of circuit elements and mask alignment marks of the wafer, which are easily overlooked, and an example in which the present invention is applied to these is shown in FIG. And shown in FIG. The monitor pattern 40 shown in FIG. 3 has a size of several mm square, which is similar to a chip including about ten semiconductor regions 41 of several tens of μm square in which circuit elements for monitoring process conditions such as transistors are formed. It is distributed in an appropriate place in the wafer and is usually provided at several places. Monitor pattern to which the present invention is applied
In 40, a mark layer 42 in the shape of a rectangular frame for identifying the location and a separation layer 43 individually surrounding each semiconductor region 41 are used for diffusion of the separation layer 4 and a high boron concentration layer at the same time. Built in. The width of the mark layer 42 is set to, for example, the above-described maximum width Wm so that the mark layer 42 is conspicuous, and the width of the separation layer 43 is set to the above-described minimum width W1.

As the mask alignment mark 50 shown in FIG. 4, there are, for example, a cross-shaped mark 51 and a hook-shaped mark 52 as shown in the drawing. These also use the high boron concentration layer at the same time when the separation layer 4 is diffused. The width of the high boron concentration layer for them is always the above-mentioned maximum width Wm or less according to the present invention.

In addition to the embodiments described above, the present invention can be implemented in various modes. For example, as one application of the present invention, the total area of the high boron concentration layer in the wafer can be controlled. That is, since the influence of re-diffusion boron from the silicon oxide film on the high boron concentration layer is relatively local,
A sufficient effect is usually obtained only by controlling the maximum width, but if the total area of the high boron concentration layer is too large, the adverse effect of re-diffused boron on the entire surface of the wafer cannot be avoided. Therefore, by limiting the maximum width of the high boron concentration layer as described above, and further limiting the total area to 40% at most of the area of the wafer, preferably 35% or less, It is possible to reduce the effect of re-diffused boron to the degree that there is no practical problem.

〔The invention's effect〕

As is apparent from the above description, in the present invention, when a semiconductor device is built in a semiconductor silicon wafer,
For example, the maximum width of the diffusion pattern of a high boron concentration layer such as a separation layer in which boron is diffused at a high surface impurity concentration of 5 × 10 ¹⁸ atoms / cm ³ or more and the surface is covered with a film containing silicon oxide during the high temperature heating process of the wafer, Since the size on the diffusion photomask is unified to a predetermined limit value of 20 μm or less, even if boron is sucked out and accumulated at a high concentration due to segregation on the silicon oxide film or the like on the high boron concentration layer. The contamination of the surface of the peripheral semiconductor region and the adverse effect on the diffusion of the semiconductor layer due to the re-diffusion can be suppressed to the minimum and the reduction in the yield rate of the semiconductor layer can be effectively prevented.

As a result of carrying out the present invention, it was possible to improve the semiconductor device manufacturing yield of 30% or less to at least 60%, and to 90% under good conditions. Further, even in the case of a semiconductor device, particularly an integrated circuit device, in which the leakage current to the ground potential or the leakage current between the circuit elements is large, even if it does not lead to a characteristic failure, there is an effect that the level of the leakage current can be reduced by about one digit. Was obtained.

In carrying out the present invention, it suffices to simply change the pattern of the photomask for the high boron concentration layer, and it is not necessary to add any new steps. The present invention provides a method for manufacturing a semiconductor device, which has a practical effect of increasing the manufacturing yield of the integrated circuit device and improving its performance or reliability.

[Brief description of drawings]

1 to 5 relate to the present invention. FIG. 1 shows a wafer and a photomask showing an embodiment in which the method for manufacturing a semiconductor device according to the present invention is applied to a separation layer for junction separation in a semiconductor region of an integrated circuit device. Partially enlarged plan view and sectional view, second
FIG. 3 is a partially enlarged sectional view of a wafer in which the method of the present invention is applied to a scribe line portion for dividing an integrated circuit device chip from the wafer, and FIG. 3 is applied to a monitor pattern in which the method of the present invention is formed in the wafer. FIG. 4 is a plan view of an embodiment in which the method of the present invention is applied to a mask alignment mark formed in a wafer, and FIG. 5 shows an experimental result regarding segregation of boron into a silicon oxide film. It is a boron concentration distribution diagram. FIG. 6 is a plan view and a sectional view of a wafer illustrating a conventional technique. In the figure, 1: semiconductor silicon substrate, 2: buried layer, 3: semiconductor region or epitaxial layer, 4: junction isolation layer, 5: semiconductor device p
Shaped layer, 6: n-type layer of semiconductor device, 10: wafer, 11, 12: semiconductor device chip, 20: silicon oxide film, 21: window, 22: phosphorus glass film, 30: photomask, 31: semiconductor region Pattern for
32: Separation layer pattern, 40: Monitor pattern, 41: Monitor circuit element semiconductor region, 42: Mark layer, 43: Separation layer, 50:
Marks for mask alignment, 51, 52: sign, C: scribe line, R1 to R3: diffusion pattern of semiconductor region, T1: bipolar transistor, T2: field effect transistor, W1 to W3: width of separation layer, Wm: separation layer Is the maximum width of.

Claims (1)

[Claims] 1. A diffusion pattern of a high boron concentration layer in which boron is diffused at a high surface impurity concentration when a semiconductor device is formed in a semiconductor silicon wafer and the surface is covered with a film containing silicon oxide during a high temperature heating process of the wafer. The method for manufacturing a semiconductor device is characterized in that the maximum width of the device is unified to 20 μm or less in the dimension on the photomask for diffusion.