JPS6222451A - P-n junction isolation method of semiconductor substrate - Google Patents

Abstract

PURPOSE:To shorten the time required from an isolation diffusion, and to limit the increase of the width and area of an isolation region to smaller values by forming a groove in a diffusion region in the surface of a semiconductor substrate through mesa etching, etc. CONSTITUTION:An silicon semiconductor substrate 1 is kept in a substance such as an oxidizing substance at a high temperature, thus shaping an oxide film (SiO2) 2 on the surface. Only a region to be diffused in the oxide film (SiO2) 2 is removed partially through photoetching and SiO2 etching, thus acquiring the silicon semiconductor substrate 1, to the oxide film 2 therein a hole is bored. A groove 3 is shaped to the section through mesa etching, etc. When the silicon semiconductor substrate 1 treated in this manner is isolation-diffused, an impurity is diffused, thus forming an isolation region 4.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a PN junction isolation method in a semiconductor substrate.

<Summary of the Invention> The present invention provides isolation in a process of electrically isolating elements in a semiconductor substrate by forming a PN junction by diffusing impurities from one or both sides of the semiconductor substrate. Reduce the time required for diffusion,
In addition, in order to better limit the width and area of the isolation region, a groove is formed in the area where diffusion is to be performed on the surface of the semiconductor substrate, and the required impurity is diffused through this groove to form a PN.
It forms a bond.

<Prior Art> Generally, in a semiconductor integrated circuit, each element constituting the semiconductor integrated circuit needs to be electrically isolated from other elements.

Conventionally, this electrical isolation between elements has been achieved using a PN junction formed by diffusing P-type (or N-type) impurities into an N-type (or P-type) semiconductor substrate.

Figures 2 (al to (C)) show the conventional PN junction isolation process in an N-type silicon semiconductor substrate. First, by keeping the N-type silicon semiconductor substrate l in an oxidizing substance at high temperature, As shown in figure (al), an oxide film (Si02) 2 is formed on the surface. Next, an oxide film (5i02) is formed on the surface.
) 2, only the region to be diffused is partially removed by photoetching and Si02 etching to obtain a silicon semiconductor substrate 1 with holes in the oxide film (S+0□) 2 as shown in the same figure (bl). When the well-known isolation diffusion using P-type impurities is performed on the silicon semiconductor substrate 1 treated in the above manner, an isolation region 4' extending over both sides of the substrate I is formed as shown in FIG. 3(C).

<Problems to be Solved by the Invention> However, in the conventional PN junction isolator method, since the PN junction is formed by simply performing isolation diffusion from the surface of the semiconductor substrate 1, the thickness of the semiconductor substrate 1 When the resistance is large or when the specific resistance is small, there is a drawback that the time required for isolation diffusion is long and the width and area of the isolation region 4 becomes large.

<Means for Solving the Problems> The present invention has been made to solve the above problems.
In a method for PN junction isolation in a semiconductor substrate, a groove is formed on the surface of a semiconductor substrate l by mesa etching or the like, and isolator diffusion is performed from this groove.

<Operation> In the present invention, before performing isolation diffusion, a groove is formed in the impurity diffusion region of the silicon semiconductor substrate by mesa etching or the like. Therefore, the distance required for diffusion can be shortened by the depth of the groove formed by mesa etching or the like compared to the conventional method, so the time required for isolation diffusion can be shortened.

<Example> Hereinafter, a method for PN junction isolation of a semiconductor substrate according to the present invention will be explained in detail.

FIGS. 1A to 1D show the steps of PN junction isolation in a silicon semiconductor substrate according to the present invention.

First, for example, by keeping a silicon semiconductor substrate I in an oxidizing substance at a high temperature, an oxide film (Si02) 2 is formed on the surface as shown in FIG. 1(a). Next, this oxide film (5i
02) Only the region to be diffused in 2 is partially removed by photoetching and 5i02 etching to obtain a silicon semiconductor substrate 1 with holes in the oxide film 2 as shown in FIG. 2(b). Then, a groove 3 as shown in FIG. 3C is formed in this portion by mesa etching or the like. When isolation diffusion is performed on the silicon semiconductor substrate l treated in this way, the impurity is diffused to form an isolation region 4 as shown in the figure (dl).

In the PN junction isolation method, for example, when using a silicon semiconductor substrate I with a diameter of 3 inches and a wafer thickness of 300 μm to form a PN junction by simply performing isolation diffusion on this substrate I from both sides, the isolation The time required for diffusion is approximately 500 hours. However, according to the PN junction isolation method of the present invention, grooves are formed on both sides of the silicon semiconductor substrate 1 by mesa etching, etc. If grooves of approximately I 00 /1 m are formed from both sides, the time required for isolation diffusion is approximately 60 hours, which can significantly shorten the diffusion time.In addition, the time required for isolation diffusion is reduced compared to the conventional method. As a result, the width and area of the isolator region 4 can be further restricted.

<Effects of the Invention> As described above, according to the present invention, by forming a groove in the diffusion region on the surface of a semiconductor substrate by mesa etching or the like, the time required for isolation diffusion can be shortened.
Furthermore, the width and area of the isolation region can be further restricted. This method is particularly effective for PN junction isolation of thick semiconductor substrates.

[Brief explanation of drawings]

Figure 1 (al~(dl) shows the process of PN junction isolation of a silicon semiconductor substrate according to the present invention, Figure 2 (al~ (C1 shows the process of conventional PN junction isolation of a silicon semiconductor) 1: Silicon semiconductor substrate, 2- Oxide film (S i 02
), 3: Groove, 4: Isolation area.

Claims (1)

[Claims] 1. A method of electrically isolating elements in a semiconductor substrate using a PN junction, in which a groove is formed on one or both sides of the semiconductor substrate, and a required impurity is diffused into the groove to form a PN junction. A PN junction isolation method for a semiconductor substrate, characterized in that: