JPS63249370A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce a useless junction capacitance, and make the high speed operation of an element possible, by making the central parts of an emitter and a collector insulative respectively. CONSTITUTION:A part exposed from the side surface of an aperture C in a first insulating film 6 is selectively subjected to etching. By introducing impurity from an N-type epitaxial layer exposed by' the etching, an emitter is formed on the side surface of a trench 8a, and a collector is formed on the side surface of a trench 8b. A horizontal type PNP transistor is operated by the following constitution, an emitter 11 formed on the side surface of an insulating region 9a for emitter, a collector 12 formed on the side surface of an insulating region 9b for collector, and a base to which an N-type epitaxial layer region 3 between the emitter 11 and the collector 12 is applied. Thereby, a junction capacitance between the emitter and the base, and a junction capacitance between the collector and the base are reduced, so that the high speed operation of an element is enabled.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is used for semiconductor integrated circuits, etc.
*Relates to a lateral bipolar transistor and its manufacturing method.

[Conventional technology]

A conventional lateral bipolar transistor is shown in FIG.

This transistor #i is an element formed on a semiconductor substrate 1ON type epitaxial layer 3 having a N+ type buried layer 2, and a P type emitter 11 formed by ion implantation from the top surface of this N type epitaxial layer 3. and 2
It has a collector 12.

Furthermore, a base contact layer 5 is provided at a location separated from the emitter 11 and the collector 12 and is deeply diffused so as to be different from the N+ type buried layer 2. Jl! formed on the upper surface of this substrate 1! ! At the edge [14 contact holes in the base contact layer 5. AI for each emitter 11 and collector 12! Electrodes 15, 15.15 are connected.

[Problem that the invention seeks to solve]

According to conventional lateral transistors, the emitter and collector must be formed to have an area larger than the electrode connection surface (contact hole).

Therefore, the regions that do not contribute to transistor operation, that is, the bottom regions of the emitter and collector are large.

Capacitance between the emitter base and between the collector base is formed in this bottom region, which hinders high-speed operation of the device.

Furthermore, due to this bottom region, emitter injection efficiency decreases, making it difficult to increase the current amplification factor.

The above problems are caused by the structure of the device, and therefore, in order to solve the above problems, a new structure must be constructed.

In manufacturing an element with this new structure, it is necessary to have as few manufacturing steps as possible and to make the process as easy as possible.

[Means and operations for solving the problem] According to the present invention, by insulating the central portions of the emitter and collector, the bottom surfaces of the emitter and the transistor, which do not contribute to the operation of the transistor, are eliminated. Therefore, +17 unnecessary junction capacitance is reduced, and high-speed operation of the device is enabled.

(2) Emitter injection efficiency is improved and a high current amplification factor can be obtained.

Further, a diffusion source is formed on the substrate, and a nitride and a collector are formed by diffusion from this source.

For this reason, (1) The manufacturing process can be simplified.

(2) Since the diffusion source can be used as a contact electrode as it is, emitter and collector electrodes can be easily formed.

Also, conventionally for contact holes for electrodes.

It was structurally impossible to form the emitter and collector smaller than this (if they were made smaller, they would sit). However, in the present invention, an insulating region is formed within the emitter and collector, so the 'electrode' is formed here. Even if a contact hole is provided, no sheeting occurs, and therefore the emitter and collector can be made smaller than the contact hole.

In addition, when forming the emitter and collector, two different
Using two insulating films, the insulating film on the substrate side is selectively etched 2, and a diffusion source is embedded there.

Since the emitter and collector are formed by diffusion from this buried region, PEP (photo-etching process) for emitter and collector diffusion is unnecessary.

Therefore, the manufacturing process can be simplified.

〔Example〕

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the manufacturing process of a lateral PNP transistor, which is the device of this embodiment.

First step: N+W buried layer 2 on P-type silicon substrate l
and an N-type epitaxial layer 3.

In addition? The mold-embedded layer 2 contains antimony or arsenic, etc.
It is formed by introducing about 0 to 10 cR.

Further, the N-type epitaxial M3 has a thickness of 1 to 5 μm.

It is formed to have a specific resistance of about 0.5 to 10Ω·α.

Subsequently, an element isolation layer (not shown) is formed to surround the N+ type buried #2 in the center and form an island region.

Note that this element isolation layer is formed by a method using a PN junction, a method using a trench isolation structure, a method using a buried oxide film, or the like. (1st
Figure (a) Second step In the N-type epitaxial layer 3, an emitter and collector forming region A and a base contact region B are formed.
After forming field oxide films 4, 4.4 to separate the regions, an N+ type base contact layer 5 is formed in the base contact region B with a different n''f17 layer 2t. (Fig. 1(b) )) Third step An oxide film (first insulating film) 6 with a thickness of about 2000 A is formed on the upper surface of the N-type epitaxial layer 3, and then a second insulating film different from this insulating film is formed on the first insulating film H6. A film 1, for example, a silicon nitride film 7, is formed to a thickness of about 2000 Å.(FIG. 1(C)) Fourth step: The first and second lining films 6 and 7 are patterned by PEP (photo-etching process). , the N-type epitaxial layer 3 is partially exposed through the patterned Jung openings C, C, and C. Subsequently, the exposed portion of the N-type epitaxial layer 3 is etched using the first and second insulating films 6.7 as masks. ,
Grooves 8a and 8b having a depth of about 0.5μ are formed here. Note that in a later step, a collector and an emitter are formed on the side surfaces of this groove, respectively. (FIG. 1(d)) Fifth step: Only the portions exposed from the side surfaces of the openings C, C, C of the first insulator M6 are selectively etched.

By introducing impurities from the N-type epitaxial layer produced by this etching, an emitter is formed on the side surface of the groove 8a, and a collector is formed on the side surface of the groove #8b.

Therefore, the performance of the horizontal PNP transistor that is finally formed depends on the amount of etching in this part. In other words, if excessive etching is performed.

Later, the area of the emitter and collector formed in the substrate increases, and the junction capacitance with the paste region increases, which becomes an obstacle to high-speed operation. 111(e)) Sixth step Using the second insulating film 7 as a mask, an insulating material, for example, a silicon film C3iOz) 9 is buried in #18m and 8b by sputtering, and an insulating region for emitter is formed. 9a and a collector insulating region 9b are formed.

(Figure 1 (f))! Step 7: A polycrystalline silicon film 1O is formed on the upper surface of the substrate by the CVD method so as to bury the polycrystalline silicon (impurity diffusion source 1O) in the etched portion of the first insulating film 6 formed in the tg5 step.

In addition, at this time, 〉U2 guess & use 11゜ brutality / 2 (4 co = c;
To,,.

Subsequently, boron, for example, is introduced into this polycrystalline silicon film 10 by ion implantation, and heat treatment is performed at about 1000° C. to diffuse boron into the side surfaces of insulating regions 9a and 9b.

As a result, an emitter 11 is formed on the side surface of the emitter insulating region 9a, and a collector 12 is formed on the side surface of the collector insulating region 9b. Ca2 diagram (g)) 8th step Polycrystalline silicon film lO by etch-back method
A film with a thickness of 3000 mm is etched on the insulating regions 9a and 9b.
Patterns 13a and 13b of approximately A size are formed.

The patterns 13a and 13b become an emitter contact electrode and a collector contact electrode, respectively. Subsequently, the second insulation M7 and the insulation material formed on the insulation film 7 are removed. (Fig. 1 (h)) @9 step After forming the protective film 14 on the upper surface of the substrate, contact holes for the paste, emitter, and collector electrodes are formed in the protective film 14, and the AI electrodes are connected to each of the contact holes. 15, 15. Connect 15. (Figure 1 (
i)) The lateral PIN'P transistor formed in the above steps has an emitter 11. and a collector 12 formed on the side surface of the collector insulating region 9b. and emitter 11 and collector 12
A transistor operation is performed using the N-type epitaxial layer regions 3a, 3a between the two as a pace.

Note that the present invention is not limited to the above-mentioned rush current,
For example, without forming 48a, 8b.

The N-type epitaxial region where the groove is to be formed may be insulated by, for example, implanting oxygen ions. (Figure 1 (h)) [Effects of the Invention] According to the present invention.

(The junction capacitance between the IJ emitter base and between the collector paste is reduced, and the sieving speed operation of the element becomes possible.

(2) Emitter injection efficiency is improved and a high current amplification factor can be obtained.

(3) It can be manufactured with a small number of steps.

(4) It can be manufactured through easy steps.

There is an effect.

[Brief explanation of drawings]

Figure 1 (value) to figure (i) are cross-sectional views showing the manufacturing process of an embodiment of the present invention. Figure 2 is a cross-sectional view showing a conventional lateral transistor. 1... Semiconductor substrate 6... First insulating film 7... Second insulating film 9a... Insulating region for emitter 9b... Insulating region for collector lO... Impurity diffusion tube 11...・Emitter 12...Collector 13a
...Emitter contact electrode J3b...Collector contact ta 15...AI electrode (pace electrode, emitter electrode, collector electrode) cb) (C) 1st v! J td> (e) (f) Figure 1 (A) ゛ Figure 1

Claims (2)

[Claims] (1) A semiconductor substrate, an emitter insulating region and a collector insulating region formed on one main surface of the substrate, an emitter formed on a side surface of the emitter insulating region, and an emitter formed on a side surface of the collector insulating region. a collector formed, an emitter contact electrode formed on the emitter insulating region and the emitter, a collector contact electrode formed on the collector insulating region and the collector,
A semiconductor device comprising a base electrode formed on one main surface of the semiconductor substrate and spaced apart from the emitter and collector. (2) forming a first insulating film on one principal surface of the semiconductor substrate; forming a second insulating film different from the first insulating film on the first insulating film; forming at least two or more openings in the second insulating film; forming an emitter insulating region and a collector insulating region in the portions of the substrate exposed from the openings; A step of etching a portion exposed from the side surface of the opening, a step of embedding an impurity diffusion source in this etched portion, and a step of introducing an impurity into the substrate from the impurity diffusion source to form an emitter insulating region and a collector insulating region. 1. A method of manufacturing a semiconductor device, comprising the step of forming an emitter and a collector, respectively, so as to surround the side surfaces.