JPH06326115A - Bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a transistor as small as possible without reducing the size of a diffused emitter layer and to enhance the breakdown strength to the transistor by forming a base layer of a second conductivity type whose surface impurity concentration is at least one order of magnitude lower than that of a first diffused layer and which is composed of a second diffused layer whose depth is a specific value or lower. CONSTITUTION:A diffused active base layer 5 and an n-type diffused collector layer 6 are formed on a surface layer in a region partitioned by a p-type diffused isolation layer 4 for an epitaxial layer 3 provided with an n-type buried diffused layer 2 on a p-type silicon substrate 1. In addition, an n-type diffused emitter layer 7 is formed on the surface layer of the diffused active base layer 5. Then, a diffused inactive base layer 13 whose surface impurity concentration is by one digit or at least one order of magnitude lower than that of the active base diffused layer 5 and whose depth is at 80% or lower is formed. Thereby, the ON characteristic value of a transistor can be kept good without making the area of the n-type diffused emitter layer 7 small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to BipIC and BiCM.
The present invention relates to a bipolar transistor represented by an element element of a semiconductor integrated circuit which is an OSIC, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Among electric devices and systems composed of ICs and other electronic parts, BipICs and BiCMOs are used.
SIC, especially the power supply breakdown voltage and output terminal breakdown voltage of the IC itself,
For example, it is used in the field where a relatively large value of 30V or more is required. Specifically, it is a vending machine control IC, a motor drive I
C, automobile control ICs, thermal head drive ICs, flat panel drive ICs such as plasma displays, and the like. Conventional BipIC and BiCMOS
The breakdown voltage of an npn transistor typified by an IC element is a step-like planar junction 21, a cylindrical junction 22 and a spherical junction 23 formed by diffusion regions as shown in FIG. 2 (a).
It is designed by theoretical value data depending on the impurity concentration N _B shown in FIG. 2 (b) with the radius of curvature r _j of the depletion layer of the breakdown voltage V _B of FIG. As shown in FIG. 2 (b), the larger the r _j , the larger the breakdown voltage.

The most basic npn transistor has a structure as shown in FIG. 3, and is divided by a p-type isolation diffusion layer 4 of an n-type epitaxial layer 3 having an n-type buried diffusion layer 2 at the interface on a p-type silicon substrate. The p-type base diffusion layer 5 and the n-type collector diffusion layer 6 are formed on the surface layer of the formed region, and the n-type emitter diffusion layer 7 is formed on the surface layer of the base diffusion layer 5, so that the heat on the surface is formed. In the opening of the oxide film 82, the emitter electrode layer 9 has the emitter electrode wiring 9, the base diffusion layer 7 has the base electrode wiring 10, and the collector diffusion layer 6 has the collector electrode wiring 11.
Are in contact with each other.

FIGS. 5A to 5J show a manufacturing process of a BipIC having such an npn transistor. That is, a window is provided in the oxide film 81 formed on the surface of the p ^- silicon substrate 1 [(a) in the figure] by using the first photomask.
(b)], Sb is diffused to form the n ⁺ buried diffusion layer 2 (FIG. 7 (c)). Then, the oxide film 81 on the surface is removed, the n layer 3 is deposited by epitaxial growth, and a window is opened again on the oxide film 82 formed on the surface by using a second photomask [FIG.
(d)] and B are diffused to form the p ⁺ separation diffusion layer 4 [(e) in the same figure]. Next, a window is opened in the oxide film 82 using the third photomask [(f) in the figure], the p base diffusion layer 5 is formed by implantation of B ⁺ ions and drive-in, and the fourth photomask is used. The oxide film 82 formed up to that time has an emitter,
Open the collector diffusion window [Fig. (G)]. Then, the n ⁺ emitter diffusion layer 7 and the n ⁺ collector / contact layer 6 are formed by phosphorus diffusion [FIG. 6 (h)]. further,
Using the fifth photomask, windows as contact holes for the base, the emitter and the collector are opened in the oxide film 82 [(i) in the figure]. After that, the emitter electrode wiring 9, the base electrode wiring 10, and the collector electrode wiring 11 are formed by Al vapor deposition and patterning using a sixth photomask [(j) of the same figure].

[0005] Such BipIC has been required to improve the characteristic values of element elements due to expansion of application fields, and various element structures have been improved. In particular, as a method for improving the power supply breakdown voltage and output terminal breakdown voltage of the IC itself, the basic element n
In order to increase the radius of curvature of the pn junction between the collector and the base of the structure of the pn transistor, as shown in FIG.
The structure is such that the periphery of the base diffusion layer 5 is surrounded by the p-type inactive base diffusion layer 12 having a large diffusion depth.

[0006]

In the conventional withstand voltage improving method for the npn transistor which is the basic element of BipIC,
Two photomasks are required to form the inactive base diffusion layer 12 and the active base diffusion layer 5, and the diffusion depth of the inactive base diffusion layer 12 is increased, but when it overlaps with the emitter diffusion layer 7. Since the current amplification factor decreases, there is a problem that the size of the emitter diffusion layer 7 needs to be reduced or the size of the entire device needs to be increased.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to improve the breakdown voltage by reducing the size of the entire device as much as possible without reducing the size of the emitter diffusion layer. It is an object of the present invention to provide a bipolar transistor and a manufacturing method capable of forming the active and inactive base diffusion layers with a single photomask.

[0008]

To achieve the above object, a bipolar transistor of the present invention comprises a first diffusion layer in which a first conductivity type collector layer is surrounded by a surface layer of a first conductivity type emitter layer. And at the surface surrounds the first diffusion layer,
It is assumed that the second-conductivity-type base layer including the second diffusion layer having a surface impurity concentration lower than that of the first diffusion layer by one digit or more and a depth of 80% or less is provided. It is effective that the bipolar transistor is an npn transistor and is an element element of the semiconductor integrated circuit device. Further, in this method for manufacturing a bipolar transistor, a mask is formed on the surface of an oxide film deposited on the surface of a semiconductor layer of the first conductivity type, and the first diffusion layer is formed through the oxide film from the opening of the mask. Then, the oxide film exposed in the opening is removed by etching through the opening of the mask, and a part of the oxide film under the mask is removed by side etching to remove the remaining oxide film. Ion implantation for the second diffusion layer is performed as a mask.

[0009]

In addition to the first diffusion layer which is the active base layer of the second conductivity type surrounding the emitter layer of the first conductivity type of the surface layer of the collector layer of the first conductivity type, the first diffusion layer is surrounded on the surface. ,
By providing a second diffusion layer which is a second conductivity type inactive base layer having a surface impurity concentration lower by one digit or more and a depth of 80% or less, a pn junction between the collector layer and the active base layer is formed. The large curvature of the outer peripheral portion is eliminated by connecting the pn junction with the inactive base layer, and the curvature of the pn junction becomes small in the outer peripheral portion of the shallow inactive base layer.
Since the radius of curvature of the outer edge of the depletion layer generated when a reverse voltage is applied to the n-junction also increases accordingly, the electric field applied to the pn junction is relaxed and the breakdown voltage improves.

[0010]

1 (a) and 1 (b) show a Bip of an embodiment of the present invention.
A cross-sectional view and a plan view of an npn transistor integrated in an IC are shown, and the same parts as those in FIGS. 3 and 4 are denoted by the same reference numerals. In this case, instead of the inactive base diffusion layer 12 deeper than the p-type active base diffusion layer 5 in FIG. 4, the inactive base diffusion layer having a lower surface concentration and a shallower depth than the diffusion layer 5 is formed.
13 are provided. The manufacturing process of this bipolar transistor is shown in FIG. 6 in which the same parts as those in FIG.
The explanation will be given by citing (a) to (e).

At the time when the separation and diffusion shown in FIG. 5 (e) is completed, the oxide film 82 on the surface is removed and a new thermal oxide film 8 is formed on the n layer 3.
To a thickness of 100-200 nm, and a resist film on it.
14 is applied to the entire surface to a thickness of about 1 μm [FIG. 6 (a)]. Next, exposure is performed using a photomask, the resist film 14 is removed by a resist developing solution to form a mask having an opening 15, and B ¹¹ is used as the implanted ions 16 for the active base layer 5 by an ion implantation device. 50 to 50 depending on the thickness of the oxide film 8
A dose amount required by the acceleration voltage of 70 keV, for example, 5 × 10
Implant at a dose of ¹⁴ / cm ² [Fig. 6 (b)]. Boron 17
Is injected into the surface layer of the n layer 3 immediately below the opening 15. Immediately after this ion implantation, the thermal oxide film 8 is selectively etched with a hydrofluoric acid chemical solution of about 5 to 20%. Since many defects exist in the oxide film 8 below the opening 15 due to the effect of ion implantation, the thermal oxide film 8 in that part is quickly etched. When the etching is further advanced, the thermal oxide film 8 immediately below the resist film 14 is gradually etched in the lateral direction, so-called side etching phenomenon occurs (FIG. 6 (c)). When the required side etch amount w is secured, the etching is finished. In this etching process, if the adhesiveness between the oxide film 8 and the resist film 14 is not sufficient, the hydrofluoric acid solution will soak into the vicinity of the interface and the oxide film etching shape will be exposed. It is necessary to take precautions such as performing processing that reduces the sex. Then, the resist film 8 is entirely removed and ion implantation of B ¹¹ 16 for the inert base layer is performed at 10 to 20 ke.
Due to V and the low acceleration voltage, the dose is smaller than the active base layer by about one digit or more [FIG. 6 (d)]. After that, base drive oxidation is performed to diffuse each implanted boron 17 into the silicon and simultaneously grow an oxide film in the opening 15 of the oxide film 8 [FIG. 6 (e)]. Furthermore, the process is shown in Fig. 5 (g).
Finally, the structure shown in FIG. 1 is obtained by connecting after the fourth photomask using step. As a method of obtaining the structure of the base diffusion layers 5 and 13 of FIG. 6, it is not limited to one mask and the use of two masks is included in the concept of the present invention. Further, the present invention is not limited to the npn transistor of the above-mentioned embodiment, and can be applied to a pnp transistor.

[0012]

According to the present invention, the base layer is composed of an active base diffusion layer close to the emitter layer and a shallow inactive base diffusion layer outside the active base diffusion layer having a low surface impurity concentration. An electric field was relaxed in the vicinity of the surface of the pn junction between the bases, and a bipolar transistor having an improved breakdown voltage was obtained. Moreover, since the area of the emitter layer does not have to be reduced, the ON characteristic value of the transistor can be kept good. Further, by utilizing the side etching phenomenon of the thermal oxide film, one photomask can be formed as an active / inactive bi-base diffusion layer, so that the increase in the number of steps can be minimized. Further, since the active base layer and the inactive base layer can be formed by the self-alignment method, variations in withstand voltage characteristic values can be reduced, and the alignment margin design can be made zero.

[Brief description of drawings]

FIG. 1 shows an npn transistor according to an embodiment of the present invention, (a) is a sectional view and (b) is a plan view.

2A and 2B show a breakdown voltage of a staircase junction pn junction, FIG. 2A is a perspective view showing types of junctions, and FIG. 2B is a relationship diagram of breakdown voltage and impurity concentration of various pn junctions.

FIG. 3 is a sectional view of a conventional npn transistor.

FIG. 4 is a cross-sectional view of a conventional npn transistor with improved breakdown voltage.

FIG. 5 is a cross-sectional view showing the manufacturing process of the npn transistor of FIG. 2 in the order of (a) to (j).

FIG. 6 shows a main part of a manufacturing process of the npn transistor of FIG.
Sectional views conceptually shown in order from (a) to (e)

[Explanation of symbols]

1 p-type silicon substrate 2 n-type epitaxial layer 5 p-type active base diffusion layer 6 n-type collector diffusion layer 7 n-type emitter diffusion layer 8 thermal oxide film 9 emitter electrode 10 base electrode 11 collector electrode 13 p-type inactive base diffusion layer 14 resist film 15 mask opening 16 B ¹¹ 17 boron

Claims (3)

[Claims] 1. A surface layer of a collector layer of the first conductivity type surrounds an emitter layer of the first conductivity type to surround a first diffusion layer and a first diffusion layer on the surface, and a surface impurity concentration higher than that of the first diffusion layer. A bipolar transistor having a second conductivity type base layer comprising a second diffusion layer having a depth of one digit or more and a depth of 80% or less. 2. The bipolar transistor according to claim 1, which is an npn transistor and is an element element of a semiconductor integrated circuit device. 3. A mask is formed on the surface of an oxide film deposited on the surface of the semiconductor layer of the first conductivity type, and ion implantation for the first diffusion layer is performed from the opening of the mask through the oxide film. Then, the oxide film exposed in the opening is removed by etching through the opening of the mask, and part of the oxide film under the mask is removed by side etching, and the remaining oxide film is used as a mask for the second diffusion layer. 3. The method for manufacturing a bipolar transistor according to claim 1, wherein the ion implantation for the purpose is performed.