JPH04243159A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide the manufacture of a semiconductor device which is high in the base-collector breakdown voltage of a bipolar transistor and small in the parasitic capacitance of MOSFET and further can raise the reverse voltage of the parasitic MOSFET. CONSTITUTION:P well 2 and N well 3 are formed in a semiconductor substrate 1 and diffused deeply by the thermal process at a high temperature and for hours so that a silicon oxide film 4 is formed. Then, the silicon oxide film 4 in the region forming a bipolar transistor is removed selectively and the semiconductor substrate 1 is etched by the use of the silicon oxide film as a mask so that a recess 5 is formed. Subsequently, after a silicon oxide film formed in the side wall 6 of the recess 5 and said silicon oxide film 4 are used as masks and an intense N-type diffused layer 7 is formed by ion implantation, an epitaxial layer 8 is formed selectively in said recess. Then, a collector-leading layer 9, field oxide film 10, gate oxide film 11, gate electrode 12 and base region 13 are formed to complete Bi-CMOS semiconductor device.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a Bi-CMOS semiconductor device comprising an optimized bipolar transistor and a CMOSFET.

0002

[Prior Art] Conventionally, bipolar transistors and CMO
Various proposals have been made regarding Bi-CMOS devices mixed with SFET. Bi-CMO with high-speed CMOSFET and high-voltage bipolar transistor, especially for application to analog-digital hybrid circuits.
As an example of a method for forming an element region of an S device, the following method is disclosed in Japanese Patent Laid-Open No. 61-245563. That is, as shown in FIG.
After forming the type buried layer 103, an N-type epitaxial layer 104 is formed. Next, as shown in FIG. 8, a P well 105, an N well 106, and a collector lead-out layer 107 are formed, and a field oxide film 108 is further formed by the LOCOS method. Next, as shown in FIG. 9, a gate oxide film 109, a gate electrode 110, and a base region 111 are sequentially formed. After this, an emitter region, source/drain regions, etc. are formed, and an interlayer insulating film and a wiring region are formed to complete the Bi-CMOS semiconductor device.

According to this method, MOSFETs can be formed in the relatively highly doped well regions 105 and 106, and the relatively lightly doped epitaxial layer 104 can be used as the collector region of the bipolar transistor.
Bi-
CMOS semiconductor devices can be manufactured. Furthermore, according to this method, the well region 105, which is diffused from above,
106 and the heavily doped buried layers 102 and 103 are electrically connected, a substantially deep well region is formed and high latch-up resistance can be obtained.

0004

[Problems to be Solved by the Invention] However, in the above conventional manufacturing method, the N-type high concentration buried layer 102
Collector of bipolar transistor due to upward diffusion of
In order to prevent a decrease in the base-to-base breakdown voltage, the thermal process for diffusion of the well regions 105, 106 forming the MOSFET is limited, so that the thermal process for electrically connecting the well regions 105, 106 and the buried layers 102, 103 is limited. To achieve this, the surface concentration of the well must be higher than necessary to achieve the required punch-through resistance, and the diffusion must be deep with a limited thermal step. For this reason, MOSFE
The parasitic capacitance of the source/drain region of T increases, and the MOS
There is a problem that the operating speed of the FET decreases.

Furthermore, in the above manufacturing method, the P-type well region 1
05 is formed on the N-type epitaxial layer 104, and the concentration of this epitaxial layer 104 is usually set to about 1E16/cm2 in order to suppress the punch-through and Kirk effect of the bipolar transistor. Therefore, in the process of forming the field oxide film, the surface concentration in the field region of the P-type well region decreases due to the pile-up of phosphorus in the epitaxial layer on the surface of the field region. There was also the problem that the reversal voltage decreased.

The present invention has been made to solve the above-mentioned problems in the conventional method of manufacturing Bi-CMOS semiconductor devices, and has a high base-collector breakdown voltage of a bipolar transistor, a small parasitic capacitance of a MOSFET, and a low parasitic capacitance. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can increase the inversion voltage of a MOSFET.

[0007]

[Means for Solving the Problems] In order to solve the above problems, the present invention forms a low concentration well region of one conductivity type in a first region of a semiconductor substrate, and a well region of another conductivity type in a second region. forming a low concentration well region, and then selectively forming a high concentration buried layer of one conductivity type and an epitaxial layer of one conductivity type in the third region; A semiconductor device is manufactured by forming a conductive type MOSFET, forming a single conductive type MOSFET in a second region, and forming a bipolar transistor in a third region.

[0008]

[Operation] According to the manufacturing method of the present invention, in order to form a low concentration well region for forming a MOSFET prior to forming a high concentration buried layer and an epitaxial layer, a relatively low concentration well region is formed deeply. This makes it possible to obtain a MOSFET with small parasitic capacitance and high latch-up resistance.Furthermore, since the MOSFET is not formed on an epitaxial layer, by using a low-concentration substrate, the field region in the field oxide film formation process can be reduced. Due to phosphorus pile-up on the surface,
Parasitic MO using the field oxide film as the gate insulating film due to the decrease in surface concentration in the field region of the P-type well region
It is possible to prevent the inversion voltage of the SFET from decreasing.

[0009]

[Example] Next, an example will be explained. 1 to 6 are manufacturing process diagrams for explaining embodiments of a semiconductor device according to the present invention. First, as shown in FIG.
A P-well 2 and an N-well 3 are formed, and the silicon oxide film 4 is diffused deeply by a high-temperature and long-term thermal process, and then a first silicon oxide film 4 is formed. Next, as shown in FIG. 2, a first silicon oxide film 4 is formed in a region where a bipolar transistor is to be formed.
is selectively removed, and the semiconductor substrate 1 is etched using the remaining silicon oxide film 4 as a mask to form a recess 5 in the bipolar transistor formation region. Next, as shown in FIG. 3, a second silicon oxide film that is thinner than the first silicon oxide film 4 is formed by CVD, and by etching back, leaving a portion of the side wall 6 of the recess 5 and a second silicon oxide film of the other portion. The first silicon oxide film 4 is removed, and the first silicon oxide film 4 is removed.
Using the sidewalls 6 as a mask, arsenic ions are implanted to form a highly concentrated N-type diffusion layer 7. Next, as shown in FIG. 4, the silicon oxide film on the side wall 6 is removed using a solution such as hydrofluoric acid. At this time, a portion of the first silicon oxide film 4 existing in the region other than the recessed portion 5 is made to remain. Subsequently, an N-type epitaxial layer 8 is formed in the recess 5 by selective epitaxial growth. Next, as shown in FIG. 5, the first silicon oxide film 4 is removed, a collector lead-out layer 9 is formed on the N-type epitaxial layer 8, and a field oxide film 10 is formed by the LOCOS method. Next, as shown in Figure 6,
Gate oxide film 11, gate electrode 12 and base region 13
are formed sequentially. After this, an emitter region, source/drain regions, etc. are formed, and an interlayer insulating film and a wiring region are formed to complete the Bi-CMOS semiconductor device.

According to this method, the thermal process for forming the well region of the CMOSFET can be set independently of the region in which the bipolar transistor is formed, so that a deep well region can be formed with a relatively low concentration. Therefore, CMOSFETs with high latch-up resistance and low parasitic capacitance
can be formed. Furthermore, since the CMOSFET is not formed in an epitaxial layer, the surface concentration in the field region of the P-type well region does not decrease due to phosphorus pile-up on the surface of the field region during the field oxide film formation process, and the field oxide film is The inversion voltage of the parasitic MOSFET used as the gate insulating film does not decrease.

[0011]

[Effect of the invention] As explained above based on the embodiments,
According to the present invention, a semiconductor device with optimized structures of both a bipolar transistor and a CMOSFET, which maintains a high base-collector breakdown voltage of the bipolar transistor, reduces the parasitic capacitance of the MOSFET, and increases the inversion voltage of the parasitic MOSFET. can be easily manufactured.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a manufacturing process for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a manufacturing process following FIG. 1.

FIG. 3 is a diagram showing a manufacturing process following FIG. 2;

4 is a diagram showing a manufacturing process following FIG. 3. FIG.

5 is a diagram showing a manufacturing process following FIG. 4. FIG.

6 is a diagram showing a manufacturing process following FIG. 5. FIG.

FIG. 7 is a diagram showing a manufacturing process of a conventional semiconductor device.

8 is a diagram showing a manufacturing process following FIG. 7. FIG.

9 is a diagram showing a manufacturing process following FIG. 8. FIG.

[Explanation of symbols]

1 Semiconductor substrate 2 P well 3 N well 4 First silicon oxide film 5 Recess 6 Side wall 7 N-type high concentration buried layer 8 N type epitaxial layer 9 Collector drawer layer 10 Field oxide film 11 Gate oxide film 12 Gate electrode 13 Base area

Claims (1)

[Claims] 1. A step of forming a low concentration well region of one conductivity type in a first region of a semiconductor substrate, forming a low concentration well region of another conductivity type in a second region, and then forming a low concentration well region of a third conductivity type. selectively forming a high concentration buried layer of one conductivity type and an epitaxial layer of one conductivity type, forming a MOSFET of another conductivity type in the first region, and forming a MOSFET of another conductivity type in the second region.
1. A method of manufacturing a semiconductor device, comprising forming a conductive type MOSFET and forming a bipolar transistor in a third region.