JPS63269558A - Semiconductor device - Google Patents

Abstract

PURPOSE:To integrate a MOS transistor and a bipolar transistor by a simple process and to enable them to display their high performance by a method wherein the MOS transistor is made to be of LDD structure and low- concentration source and drain diffusion layers of this transistor, a base layer, a high-concentration diffusion layer and a base contact layer of the bipolar transistor are made to be layers of an identical impurity concentration distribution. CONSTITUTION:High-concentration n<+> buried layers 121, 122 are formed on a p-type Si substrate 11; an n-type well 13 for a p-channel MOS transistor and an n-type collector 14 for a transistor, both having an identical impurity concentration distribution, are formed on the buried layers 121, 122. Low- concentration source and drain diffusion layers, i.e. p<-> type diffusion layers 191, 192 for the p-channel MOS transistor have the same impurity concentration distribution as a p<-> type base layer 20 for the npn transistor while high- concentration source and drain diffusion layers, i.e. p<+> type diffusion layers 241, 242 for the p-channel MOS transistor have the same impurity concentration distribution as a base contact layer 23 for the npn transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device in which a MOS transistor and a bipolar transistor are integrated and formed on the same substrate.

(Prior Art) Many attempts have been made to realize higher functionality with a single chip by fabricating polar transistors in six MO8i integrated circuits. In particular, recent advances in microfabrication technology have made it possible to implement functions that were previously required using multiple chips on a single chip, and various ideas have been proposed to further reduce the number of steps, improve yields, and lower costs. has been done. For example, the collector layer of a bipolar transistor and the well of an 0M08 circuit are made into diffusion layers in the same process, and the emitter layer or base layer of a bipolar transistor and the source of a MOS transistor.

A method has been proposed in which the drain diffusion layer is formed as a diffusion layer in the same process.

However, these conventionally proposed methods cannot individually optimize the impurity concentration distribution of each layer. For example, considering the case where the base layer of a bipolar transistor and the source and drain diffusion layers of a MOS transistor are formed in the same process, it is desirable that the impurity concentration of the source and train diffusion layers be high in order to lower the resistance. In the base layer, if the impurity level is too high, the current amplification factor will decrease, so the respective R values do not necessarily match.

Generally preferred impurity concentrations are approximately 10"/cs3 for the source and drain diffusion layers and 1016/cs3 for the base layer.
The difference is two orders of magnitude. Therefore, although it is possible to reduce the number of steps by forming each of these layers in the same process, there is a problem in that the characteristics of either the bipolar transistor or the MOS transistor must be sacrificed.

(Problems to be Solved by the Invention) As described above, when MoS transistors and bipolar transistors are integrated and formed on the same substrate, it is difficult to fully demonstrate the performance of each when attempting to simplify the process. was there.

The present invention solves these problems and creates MOS with a simple process.
It is an object of the present invention to provide a semiconductor device that makes it possible to integrate an i-transistor and a bipolar transistor, and also allows each to exhibit high performance.

[Structure of the Invention] (Means for Solving Problems) The present invention provides a semiconductor device in which a bipolar transistor and a MOS transistor are integrated, in which a MOS transistor is formed into a low concentration source, a drain diffusion layer and a high concentration source. L D D (L ig
The low concentration source/drain diffusion layer and the base layer of the bipolar transistor are layers with the same impurity concentration distribution, and the high concentration source/drain diffusion layer and the base contact of the bipolar transistor are It is characterized by having the same impurity concentration distribution as the skin. More preferably in the present invention, the second conductive type collector layer of the bipolar transistor formed in the first conductive layer Wlffi and the second conductive type well for forming the MOS transistor are layers with the same impurity concentration distribution.

(Function) In order to prevent a decrease in reliability due to miniaturization of MO8 integrated circuit elements, an LDD structure is often used recently. This LD
The two-stage source and drain diffusion layers of the DH4 structure are applied to the base layer and base layer of the bipolar transistor as described above.
By making them correspond to the contact layer, the characteristics of the bipolar transistor 1 to the transistor and the MOS transistor that are made to coexist can be respectively set optimally. Furthermore, bipolar transistors and MOS transistors having such optimal characteristics can be integrated on the same substrate without significantly changing the manufacturing process of conventional CMO8 integrated circuits.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the main structure of an embodiment in which an npnt transistor and a CMOS transistor are integrated. p-type S1
For example, high concentration 04'' buried layers 121 and 122 with a depth of 2 to 3 μm are formed on the substrate 11, and these buried layers 112
p with the same impurity concentration distribution on 1.122
An n-type well 13 for a channel MOS transistor and an n-type collector layer 14 for the transistor are formed.

The low concentration source and drain expanded rP1 layers of the p-channel MO8I transistor, that is, the p-type diffusion layers 191 and 192 are np.
It has the same impurity concentration distribution as the p- type base layer 20 of the n-transistor, and is a high-concentration source and drain diffusion layer of the p-channel MOS transistor, that is, the p+-type scattered layer 24+2.
42 is the base contact layer 23 of the npn transistor
It has the same impurity concentration distribution as .

A specific manufacturing process for obtaining such a structure will be explained using FIGS. 2(a) to 2(f). For example, antimony is thermally diffused into the p-type Si material plate 11 to form an n1-type buried layer 121,
122 is formed. After that, for example, an n-type epitaxial growth layer is formed, and a p-type layer is deeply diffused in the isolation region of the bipolar transistor and the n-channel MOS transistor formation region, thereby forming an island-shaped n-channel MOS transistor.
An n-type well 13 and an n-type collector layer 14 for the S transistor are formed. Thereafter, an element isolation insulating film 15 is formed by selective oxidation or the like (a). and an n+ type wide diffusion layer 16 that reaches the buried layer 122 for collector contact;
For example, phosphorus is formed by ion implantation at I Xl 0'' /a + 2.50 keV (b).
Gate insulation Il with human-sized thermal oxide film! 17 is formed, and gate electrodes 181 and 182 are formed by a 4000 phosphorus-doped polycrystalline silicon film. After thermally oxidizing the entire surface, a mask with openings in the base region of the transistor and the n-channel MOS transistor region is formed, and boron ions, for example, are implanted at 4×1013/Clm at 2.30 keV to form the low-concentration source and drain of the n-channel MOS transistor. P-type diffusion layers 191 and 192, which are diffusion layers, and a p-type base layer 20 of an npn transistor are formed. Next, the n-channel MOS transistor ff1hl
For example, form a mask with an opening in the
3/cttr2, low lI by ion implantation at 25keV
n-type diffusion layer 21 which is r51 source and drain diffusion layer
1.212 is formed (C).

After this, for example, a silicon oxide film is applied by CVD to the entire surface.
500 layers are deposited, and the entire surface is etched by reactive ion etching to selectively leave the oxide film 22 on the side walls of the gate electrodes 181 and 182. After thermally oxidizing the entire surface, a mask having openings in the base contact region and the n-channel MOS transistor region is formed, and boron fluoride, for example, is ion-implanted at 5×10”/crs2.40keVr to increase the high fAr of the n-channel MOS transistor. !i source.

A p+ type scattering layer 241242 which is a drain diffusion layer and a p++ base contact layer 23 are formed. Furthermore n
A mask with an opening is formed in the channel MOS transistor region, and arsenic, for example, is deposited at 5x10"/ctx2,40
High concentration source of n channel MOS transistor by ion implantation at keV.

An n+ type scattering layer 251252, which is a drain diffusion layer, is formed (d>). After this, a CvD insulator 111J26 is deposited on the entire surface, and only the emitter region is etched to deposit, for example, an arsenic-doped polycrystalline silicon film, followed by heat treatment. Then, arsenic is diffused to form an n+ type emitter layer 28. This polycrystalline silicon group is patterned to form an emitter contact electrode 27 (e). After this, CVD insulation!! 29 is deposited on the entire surface, A contact hole is made in this and an Aff wiring 30 is formed to complete a bipolar CMOS transistor (
f).

In the structure of this embodiment, an n-channel MOS of LDD structure is used.
Since the two-stage source and drain diffusion layers of the transistor correspond to the base layer and base contact layer of the npn transistor, each impurity 111
f is set to the optimum state. Moreover, the manufacturing process is LDD
The process for forming a CMOS transistor of II structure can be used with almost no changes.

The present invention is not limited to the above embodiments. For example, in the example,
The emitter layer of a bipolar transistor was formed by thermal diffusion from an arsenic-doped polycrystalline silicon film.
It can also be formed by ion implantation at the same time as the highly doped source and drain diffusion layers of the channel MOS transistor. Further, in the actual example, an npn transistor was formed using a p-type 5illi, but the present invention is also effective when forming a pnp transistor using an n-type substrate. In that case, the same relationship as in the above embodiment may be provided between the source and drain diffusion layers of the n-channel MOS transistor and the base layer and base contact layer of the pnp transistor.

In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, an LDD structure MOS
By associating the source and drain expansion rIIFj4 of the transistor with the base layer and base contact layer of the bipolar transistor, the impurity concentration of each layer can be optimized and the MOS transistor and bipolar transistor can be integrated in a state where each can achieve high performance. can do. Furthermore, the structure of the present invention can be realized without major changes to the conventional manufacturing process of CMOS transistors, and can minimize the decrease in yield and increase in cost due to the integration of MOS transistors and bipolar transistors. , an integrated circuit with excellent performance and reliability can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the structure of an embodiment of the present invention, and FIG. 2 (a
) to (f) are diagrams showing the manufacturing process. i i p-type St substrate, 12t, 122-n++
Buried layer, 13... n-type well, 14... n-type collector layer, 15... element isolation insulating film, 16... n++
Collector contact layer, 17... gate insulating film, 1
81.182...Gate electrode, 191,192...
p-type diffusion layer (low concentration source, drain expansion r'l1 layer)
, 20...p-type base layer, 211, 212...n
- type diffusion layer, 22... Oxide film, 23... P++ base contact layer, 241.242... P" type diffusion layer (high concentration source, drain diffusion layer>, 25t, 252
...n+ type scattering layer 26...CVD insulating film, 27.
...Arsenic-doped polycrystalline silicon layer, 28...n+ type emitter layer, two...CVD insulating film, 30...AQ wiring. Applicant's agent Patent attorney Takehiko Suzue (C) Figure 2

Claims (2)

[Claims] (1) A bipolar transistor having a collector layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and a well of a second conductivity type is provided in the same substrate, and a source,
A MOS transistor is formed whose drain diffusion layer includes a low concentration diffusion layer and a high concentration diffusion layer, and the low concentration source and drain diffusion layers of the MOS transistor and the base diffusion layer of the bipolar transistor have the same impurity concentration distribution,
A semiconductor device characterized in that the high concentration source and drain diffusion layers of the MOS transistor and the base contact layer of the bipolar transistor have the same impurity concentration distribution. (2) The semiconductor device according to claim 1, wherein the well and the collector layer of the bipolar transistor have the same impurity concentration distribution.