JP2616809B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a mixed bipolar / moss semiconductor device.

(Prior art) With the demand for high integration, high speed, and low power consumption of semiconductor integrated circuits (LSIs), the high speed and high drive performance of bipolar LSIs and complementary MOS LSIs (CMOS-LSIs) The development of a bipolar / complementary MOS mixed-type LSI (hereinafter abbreviated as Bi-CMOS LSI), which has both features of high integration and low power consumption, is underway.

For example, Japanese Patent Application Laid-Open No. 59-94861 proposes a Bi-CMOS type semiconductor device capable of performing good isolation.

FIG. 3 shows a cross-sectional structure of a conventional Bi-CMOS semiconductor device. In the figure, an N ⁺ -type buried layer 22 is formed on a part of the surface of a P ⁻ -type semiconductor substrate 21 by selective diffusion,
Further, a P ⁺ type buried layer is formed on other portions of the surface of the P ⁻ type semiconductor substrate 21.
After forming 23, an N ⁻ -type epitaxial layer 24 is formed. Then, the P ⁺ type buried layer 23 is added to the N ⁻ type epitaxial layer 24.
A P-type diffusion layer 25 is formed so as to be connected to. The vertical NPN transistor is formed on the N ⁺ type buried layer 22 and has a collector N ^−.
P ⁺ -type base layer 26 formed by selective diffusion from the surface of the p-type epitaxial layer 24, and N ⁺ formed in the P ⁺ -type base layer 26.
It is composed of a mold emitter layer 27. The NMOS transistor is formed on the P ⁺ -type buried layer 23 and has an N ⁺ -type source / drain region 29 and a P-well region
Gate oxide film 30 provided on the surface of 28, and gate electrode 31
It is composed of PMOS transistor, N is an N-well region ^- -type epitaxial layer P ⁺ type source and drain regions 32 in the 24, N ^- gate oxide film 30 provided on the surface of the type epitaxial layer 24, and is constituted by a gate electrode 31 ing.

More in the conventional Bi-CMOS semiconductor device having such a structure, N ^- -type epitaxial layer 24 under the N ⁺ -type buried layer 22
Is provided to reduce the collector series resistance of the NPN transistor. Further, by providing the P ⁺ type buried layer 23 also under the P well region 28, the well resistance value is reduced, so that a latch map phenomenon peculiar to CMOS can be prevented.

(Problem to be Solved by the Invention) The above-described conventional configuration has the following disadvantages.

(1) Since the N ⁺ -type buried layer and the P ⁺ -type buried layer are formed by selective diffusion, a photolithography step for forming a diffusion window is required, and the number of LSI manufacturing steps increases. I do.

(2) Since the collector N ⁻ type semiconductor layer of the NPN transistor is formed by epitaxial growth, the throughput in the manufacturing process is low, and the operating cost of the epitaxial growth apparatus is high, so that the manufacturing cost of the LSI increases.

An object of the present invention is to solve the conventional drawbacks, reduce the number of manufacturing steps with a simple configuration, and reduce the manufacturing cost.
An object of the present invention is to provide a CMOS semiconductor device.

(Means for Solving the Problems) The semiconductor device of the present invention comprises a semiconductor substrate of one conductivity type,
A second conductivity type well region provided in a predetermined region on one main surface of the semiconductor substrate; and a second conductivity type second region provided in the semiconductor substrate in the entire region of the semiconductor substrate and connected to the bottom surface of the well region. A buried layer, a first buried layer of one conductivity type provided in the semiconductor substrate outside the well region and shallower than the second buried layer, and a semiconductor substrate connected to an upper surface of the first buried layer And a bipolar transistor having the surface region as a collector and a bipolar transistor having the surface region as a collector are provided with a one conductivity type MIS transistor in a well region.

(Operation) According to the present invention, each active element is separated from the second buried layer and the well region by the above structure, and the NPN transistor is formed using the surface region of the N-type semiconductor substrate as the collector region. A bipolar transistor can be realized without using a semiconductor layer formed by epitaxial growth, and the LSI manufacturing process can be shortened.

(Embodiment) An embodiment of the present invention will be described with reference to FIG. 1 and FIG.

FIG. 1 shows a sectional structure of a Bi-CMOS type semiconductor device of the present invention. In the figure, an N ^- type semiconductor substrate (here, a single crystal silicon substrate, hereinafter abbreviated as a Si substrate) 1
Then, a first N ⁺ type buried layer 2 and a second P ⁺ type buried layer 3 deeper than this are formed. Here, since the first and second buried layers 2 and 3 are formed by ion implantation with high acceleration energy (here, about several MeV), the impurity concentration on the surface of the Si substrate 1 is low, and the impurity distribution is low. Is deep, it can be formed at a predetermined depth position. Therefore, the N-type surface regions 1a and 1b remain on the Si substrate 1. Then, a P-type well region 4 connected to the second buried layer 3 is formed on the N ⁻ -type Si substrate 1 outside the region of the first buried layer 2. Therefore, a well structure having a buried layer can be realized without using epitaxial growth.

After forming the respective buried layers and the well regions, the N ⁺ -type source / drain regions 5 are formed in the P-type well regions 4.
And a gate insulating film (here, a silicon oxide film, hereinafter referred to as a gate oxide film) on the surface of the P-type well region 4.
6 and a gate electrode (here, a polycrystalline silicon film, hereinafter referred to as a Poly-Si gate) 7 are formed to form an NMOS transistor, and a P ⁺ type source
A PMOS transistor is formed by forming a drain region 8 and a gate oxide film 6 and a Poly-Si gate 7 on the surface of the surface region 1a to form a PMOS transistor. The surface region 1b of the Si substrate 1 on the first N-type buried layer 2 is formed. Within the P-type active base layer 9 and the N ⁺ -type collector wall layer 10 connected to the N ⁺ -type buried layer 2, the N ⁺ -type emitter layer 5 'and the P ⁺ -type external The NPN transistor is formed by forming the base layer 8 '.

In FIG. 1, reference numeral 11 denotes an element isolation insulating film (here, a silicon oxide film, hereinafter referred to as an SiO ₂ film), 12 an interlayer insulating film (here, a PSG film), and 13 an aluminum wiring (here, A
The P ⁺ -type buried layer 3 and the P-type well region 4 under the element isolation SiO ₂ film 11 are element isolation regions.

According to the present embodiment configured as described above, the second P ⁺
Since the mold buried layer 3 is formed in the entire region of the Si substrate 1, a photolithography step is required, and therefore, the number of LSI manufacturing steps can be reduced. And the NPN transistor is Si
Since the surface region 1b of the substrate 1 is formed as a collector, since epitaxial growth is not used, the throughput of the manufacturing process is high, and the manufacturing cost of the LSI can be reduced.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described. 2 (A) to 2 (C) show the Bi-CM shown in FIG.
FIG. 4 is a process sectional view illustrating the method for manufacturing the OS-type semiconductor device.

(A) After forming the SiO ₂ film 14 on the surface of the Si substrate 1, a photoresist film 15 is formed with a thickness of about 3 μm. after that,
After the photoresist film 15 in the PMOS transistor and NPN transistor formation region is opened using the photolithography technique, phosphorus (P) is used as a mask with high acceleration energy, for example, 1 to 2 MeV (5 to 20) × 10 ^13. Ions are implanted. In this case, a depth of about 1 to 2 μm is driven into the peak P.

(B) Next, after removing the photoresist film, a heat treatment for crystallinity recovery is performed on the SiO substrate 1 at, for example, 1000 to 1050C. As a result, a first N ⁺ type buried layer 2 is formed in a predetermined region. Thereafter, boron (B) is applied to the entire region of the Si substrate 1 with high acceleration energy, for example, at 1 to 2 MeV (1 to 5) × 10
¹³ ions are implanted. By doing so, B is implanted at a depth of about 2 to 3 μm as a peak. Thereafter, when heat treatment for recovering crystallinity is performed on the Si substrate 1, a second P ⁺ -type buried layer 3 deeper than the first buried layer 2 is formed.

(C) Next, a P-type well region 4 is formed in the NMOS transistor formation region and the element isolation region outside the formation region of the first embedded layer 2 by using selective diffusion. Then, the Si substrate 1
On the first N ⁺ -type buried layer 2, there are provided N-type surface regions 1 a and 1 b separated by a second P ⁺ -type buried layer 3 and a P-type well region 4.
Remains.

Hereinafter, an element isolation SiO ₂ film 11 is formed by using a well-known technique, and a P-type transistor constituting an NPN transistor is formed in the N-type surface region 1b.
An active base layer 9, an N ⁺ -type emitter layer 5 ', an N ⁺ -type collector wall layer 10, and an external base layer 8' are formed, and a P ⁺ -type source / source for forming a PMOS transistor is formed in an N-type surface region 1a. Drain region 8, gate oxide film 6, and Poly-Si gate 7
Are formed, and an N ⁺ type source / drain region 5, a gate oxide film 6 and a Po
The ly-Si gate 7 is formed, the PSG film 12 for the interlayer is formed,
After opening the contact window, the Al wiring 13 is formed, whereby the Bi-CMOS semiconductor device shown in FIG. 1 can be formed.

In this embodiment, the first N ⁺ type buried layer is formed using phosphorus (P), but may be formed using arsenic (As) or antimony (Sb). Further, since the photoresist film is used as an implantation mask, another deposited film or a coated film may be used.

(Effects of the Invention) According to the present invention, the number of manufacturing steps of a semiconductor device can be reduced with a simple configuration, and therefore, a Bi-CMOS type semiconductor device whose manufacturing cost can be reduced can be realized. The effect is extremely large.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a main part of the manufacturing method, and FIG. 3 is a sectional view of a conventional semiconductor device. 1 ...... N ^- -type semiconductor substrate, 2 ...... first N ⁺ -type buried layer, 3 second P ⁺ type buried layer, 4 ...... P-type well region, 5 ...... N ⁺ -type source and drain Region, 5 '... N-type ⁺ emitter layer, 6 ...
... gate insulating film, 7 ... gate electrode, 8 ... P ⁺ type source / drain region, 8 '... P ^{+ type} external base layer, 9 ... P
Active base layer, 10 ... N ⁺ type collector wall layer, 11 ...
... Element isolation insulating film, 12 ... Interlayer insulating film, 13 ... Aluminum wiring, 14 ... SiO ₂ film, 15 ... Photoresist film.

Claims (3)

(57) [Claims] A semiconductor substrate of one conductivity type; a well region of the other conductivity type provided in a predetermined region on one main surface of the semiconductor substrate; and a semiconductor substrate provided in the semiconductor substrate over the entire region of the semiconductor substrate. A second buried layer of the other conductivity type connected to the bottom surface of the well region; and a first buried layer of one conductivity type provided in the semiconductor substrate outside the well region and shallower than the second buried layer.
A buried layer, and active elements respectively formed in a surface region and the well region of the semiconductor substrate connected to an upper surface of the first buried layer. 2. An active element formed in a surface region of a semiconductor substrate is a MIS transistor of the other conductivity type and a bipolar transistor having this surface region as a collector, and an active element formed in a well region is a MIS transistor of one conductivity type. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the first and second buried layers are formed by ion implantation with high acceleration energy (here, about several MeV).