JP2940557B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an npn, pnp transistor and an n-channel, p-channel transistor.
The present invention relates to a method for manufacturing a semiconductor device having a channel MOS transistor on the same semiconductor substrate.

[Conventional technology]

Fig. 2 shows the International Electron Devlces Mee (IEDM).
ting) Vertical npn, pnp shown in Tech. Dig. 1988, p760-763.
FIG. 2 is a cross-sectional view of a mixed-type LSI including a transistor and a CMOS transistor.

In the figure, 1 is p ^- type semiconductor substrate, 2 and 3 are n-type and the n ⁺ -type buried layer, the p ⁺ -type buried layer 4, 5 is n-type epitaxial layer, 6 is the element isolation insulating film, 7 Is a p ⁺ -type channel cut layer, 8 is a p-type diffusion layer, 9 is a p-type base diffusion layer, and 10 is n
Type base diffusion layer, 11 and 12 are channel doped regions, 13 is p
Base electrode, 14 is an n-type base electrode, 15 is an n-type source
Drain electrode, 16 is a p-type source / drain electrode, 17 is n
Type collector lead-out electrode, 18 is a p-type collector lead-out electrode, 19 is a passivation insulating film, 20 is an n-type emitter electrode, 21 is a p-type emitter electrode, 22 is an n-type gate electrode, 23 is a p-type gate electrode, and 24 is n 25 is a p-type emitter diffusion layer, and 26 is a wiring layer.

Here, npn and pnp represent regions for forming npn and pnp transistors, respectively, and nMOS and pMOS represent n channel and pMOS, respectively.
Represents a region for forming a channel MOS transistor.

Next, the manufacturing process will be described with reference to FIGS. 3A to 3C.

First, an n-type buried layer 2 is formed on the surface of the pnp region of the substrate 1, and as shown in FIG. 3A, an n ⁺ -type buried layer 3 is formed on the surface of the npn and pMOS regions, and Surface of embedded layer 2 and nMOS
A p ⁺ -type buried layer 4 is formed on the surface of the region, and then an n-type epitaxial layer 5 is formed.

Then, after the channel cut layer 7 is formed, an element isolation insulating film 6 is formed in a predetermined region to perform element isolation.
In order to reach the p ⁺ type buried layer 4 of the nMOS region,
After forming the diffusion layer 8, a thin nitride film 100 is formed on the entire upper surface.
Is formed, and an n ⁺ buried layer 3 is formed in the collector lead portion of the npn and pnp regions.
And a groove 101 reaching the p ⁺ buried layer 4 is formed.
A polycrystalline silicon layer 102 is formed inside and on the nitride film 100.

Next, as shown in FIG. 3B, the regions other than the predetermined region of the polycrystalline silicon layer 102 in the npn and nMOS regions are selectively oxidized, and the collector electrode layer 102a, the base electrode layer 102b, and the source Forming a drain electrode layer 102c, forming a passivation insulating film 19 in the selectively oxidized region,
Similarly, the collector, base, source / drain electrode layers are formed for the pnp and pMOS regions.

Thereafter, using a mask having a predetermined pattern, boron (B) is implanted into the base electrode layer 102b in the npn region, the collector electrode layer in the pnp region (not shown in FIG. 3B), and the source / drain region in the pMOS region. The base electrode 13, the p-type collector lead-out electrode 18, and the p-type source / drain electrode 16 are formed, and a mask having another predetermined pattern is used to form a collector electrode layer 102 a in the npn region and a source / drain electrode layer 102 c in the nMOS region. And phosphorus (P) is implanted into a base electrode layer of a pnp region not shown in FIG. 3B to form an n-type collector lead-out electrode 17, an n-type source / drain electrode 15, and an n-type base electrode.
Form 14.

Further, as shown in FIG. 3C, the insulating film 19 in the region to be the emitter and the gate is removed, the surface of each electrode is oxidized, and the nitride film 100 at the bottom of the region where the insulating film 19 is removed and the nitride film 100 are removed. After removing the thin oxide film immediately below, and simultaneously etching in the lateral direction, a thin layer of polycrystalline silicon is again deposited on the entire surface, and this polycrystalline silicon forms a base electrode 13.
And the n-type epitaxial layer 5 and the source / drain electrode 15 and the p-type diffusion layer 8, then oxidize the emitter and gate regions to form an insulating film 19 also in the emitter and gate regions. The same process is performed for the pnp and pMOS regions.

Then, as shown in FIG. 2, the base regions of the npn and pnp regions and the channel dope regions of the nMOS and pMOS regions
Each of the diffusion regions 9, 10 and the channel dope regions 11, 12 are formed by injecting predetermined impurities, and an opening for the emitter is formed in the emitter region of the npn, pnp region. Arsenic (As) is introduced using a mask of another judgment pattern, an n-type emitter electrode 20 is formed in the npn region, and an n-type gate electrode 22 is formed in the nMOS region. Then, B is introduced using a mask having a different predetermined pattern. Then, a p-type emitter electrode 21 is formed in the pnp region, a p-type gate electrode 23 is formed in the pMOS region, and an n-type emitter diffusion layer 24 and a p-type emitter diffusion layer 25 are formed by thermal diffusion when these impurities are introduced. Then, a contact hole is opened at a predetermined position to form a wiring layer 26, and a desired wiring is performed.

[Problems to be solved by the invention]

In the conventional method for manufacturing a semiconductor device, the n-type base electrode 14
And an n-type source / drain electrode 15 and a p-type base electrode 13
Since the implantation type is different from that of the p-type source / drain electrodes 16, a mask alignment step of a photoresist or the like for impurity implantation during the formation of the n-type electrodes 14 and 15 and the p-type electrodes 13 and 1 are performed.
Many mask alignment steps are required for impurity implantation at the time of forming 6, and the mask alignment step is required twice.

Further, an n-type emitter electrode 20 and an n-type gate electrode 22,
Since the p-type emitter electrode 21 and the p-type gate electrode 23 also have different implantation species, a mask alignment step for forming the n-type electrodes 20 and 22 and a p-type electrode 21 and 23 A mask alignment step is required.

As described above, there is a problem that a large number of mask alignment steps are required for the impurity implantation at the time of forming the electrodes 13 to 16 and 20 to 23.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-described problems, and has as its object to reduce the number of mask alignment steps for impurity implantation at the time of forming each electrode.

[Means for solving the problem]

According to the method of manufacturing a semiconductor device of the present invention, a first region for forming a bipolar transistor having a first conductivity type base layer and a bipolar transistor having a second conductivity type base layer are formed on the same semiconductor substrate. Comprising a second region for forming a MOS transistor having a channel region of the second conductivity type, and a fourth region for forming a MOS transistor having a channel region of the first conductivity type. In a method of manufacturing a semiconductor device for manufacturing a device,
Selectively forming an oxide film only above the substrate in the third region, sequentially depositing a first polycrystalline silicon film and a first insulating film, and forming a first polycrystalline silicon film on the first polycrystalline silicon film. 1
Introducing a conductivity type impurity, and processing the first polycrystalline silicon film into a predetermined shape together with the first insulating film;
Forming a base electrode in the first region, an emitter electrode and a collector electrode in the second region, a gate electrode in the third region, and a source / drain electrode in the fourth region; Forming an insulating film on side surfaces of the crystalline silicon film and the first insulating film;
Selectively forming an oxide film only on the region above the substrate; depositing a second polycrystalline silicon film and introducing a second conductivity type impurity into the second polycrystalline silicon film; A second polycrystalline silicon film is processed into a predetermined shape, an emitter electrode and a collector electrode in the first region, a base electrode in the second region, a source / drain electrode in the third region,
Forming respective gate electrodes in the fourth region;
An emitter diffusion layer and an external base diffusion layer are formed in the first and second regions by heat treatment, and a source region is formed in the third and fourth regions.
Forming a drain diffusion layer.

[Action]

In the present invention, after the first polycrystalline silicon film is formed, impurities of the first conductivity type are introduced, and processed into a predetermined shape to form each electrode of the first conductivity type, thereby forming the second polysilicon film. In order to form a crystalline silicon film, introduce a second conductivity type impurity, and process it into a predetermined shape to form each second conductivity type electrode. Unlike the related art, a mask alignment step for impurity implantation at the time of forming each electrode is not required, and the number of steps can be reduced as a whole.

〔Example〕

1A to 1F are cross-sectional views of one embodiment of a method for manufacturing a semiconductor device according to the present invention, and each step will be described below.

However, in these figures, npn, pnp, nMOS, pMOS
Are npn transistors corresponding to the first, second, third, and fourth regions,
pnp transistor, n-channel MOS transistor, p-channel
Each represents a region for forming a MOS transistor.

First, as shown in FIG. 1A, an n ⁺ type buried layer 28 is formed on the surface of a p ⁻ type silicon substrate 27, and ap ⁺ type buried layer 29 is formed on the surface of the buried layer 28 in the pnp and pMOS regions. After formation, an n ⁻ -type epitaxial layer 30 is deposited on the entire surface, and a p-type channel cut layer 31 is formed on the bottom surface.
An element isolation insulating film 32 is formed so that pnp, nM
The p ^- type diffusion layers 33 and 3 are respectively formed on the epitaxial layer 30 in the OS region.
4 and an n ⁺ -type collector lead-out layer 35 and a p ⁺ -type collector lead-out layer 36 are formed in the npn and pnp regions, respectively.

Thereafter, n becomes a base region of the npn regions ^- -type epitaxial layer 30 with p-type impurity ions B ⁺ and the like are injected, p becomes a base region of the pnp region ^- n type such as P ⁺ in type diffusion layer 33 Impurity ions are implanted into the p ^- type diffusion layer 34 in the nMOS region.
Channel doping ion implantation for controlling the threshold voltage is performed on the surface of the n ⁻ -type epitaxial layer 30 in the pMOS region.

Then, as shown in FIG. 1B, after oxidizing the entire surface to form an oxide film, the oxide film is etched so that the oxide film 37 remains only on the surface of the p ⁻ type diffusion layer 34 in the nMOS region, and the surface is etched. A first polycrystalline silicon film 38 and a CVD oxide film 39 as a first insulating film are sequentially deposited on the entire surface, and then a p-type impurity is doped into the polycrystalline silicon film 38 through the CVD oxide film 39.
At this time, by heat treatment at the time of forming the CVD oxide film 39, np
A p-type base layer 40 and an n-type base layer 41 are formed in the n and pnp regions, respectively, and a channel dope layer 4 is formed in the nMOS and pMOS regions.
2,43 are formed.

Further, as shown in FIG. 1C, the p-type polycrystalline silicon film 38 and the oxide film 39 are processed into a predetermined pattern, and the p-type base electrode 44 is formed in the npn region, the p-type collector electrode 45 and the p-type collector electrode 45 are formed in the pnp region.
A p-type gate electrode 47 is formed in the n-MOS region, and a p-type source / drain electrode 48 is formed in the pMOS region.

At this time, an opening 49 is formed in the emitter region of the npn region and an opening 50 is formed in the gate region of the pMOS region by patterning the polycrystalline silicon film 38 and the oxide film 39.

Next, as shown in FIG. 1D, a sidewall 51 made of an insulating film is formed on the side surface of each of the electrodes 44 to 48 formed by patterning and the oxide film 39 thereon, and then the oxide film is formed thin again. The oxide film 52 only in the opening 50 of the pMOS region.
The oxide film is etched so as to remain.

Then, as shown in FIG. 1E, a second polycrystalline silicon film is deposited and formed on the entire surface, and n is added to this polycrystalline silicon film.
After implanting the type impurity, this is patterned and npn
The opening 49 of the region has an n-type emitter electrode 53 and an n-type collector electrode 54 on the collector extraction layer 35, an n-type base electrode 55 on the base layer 41 in the pnp region, and an n-type base electrode 55 on the p ^- type diffusion layer 34 in the nMOS region. An n-type gate electrode 57 is formed on the p-type source / drain electrodes 56 and the pMOS region n ⁻ -type epitaxial layer 30, respectively.

Further, as shown in FIG.
An n ⁺ -type emitter diffusion layer 58 and a p ⁺ -type external base diffusion layer 59 are formed below the emitter electrode 53 and the base electrode 44 in the p-type base layer 40 in the p-type region, respectively. p ⁺ -type emitter diffusion layer 60 and n ⁺ type outer base diffusion layer 61 are respectively formed in the lower part of the emitter electrode 46 and base electrode 55, p in the nMOS region ^- diffusion layer
An n ⁺ -type source / drain diffusion layer 62 is formed below the source / drain electrode 56 of the N-type semiconductor layer 34, and a p ⁺ -type source / drain diffusion layer 63 is formed below the source / drain electrode 48 of the n ⁻ -type epitaxial layer 30 in the pMOS region. Is formed, a passivation insulating film 64 is formed on the entire surface, a contact hole is formed at a predetermined position, and a wiring layer 65 is formed.
A semiconductor device in which transistors, nMOS, and nMOS transistors are mixed is completed.

In the above embodiment, the p-type base electrode 44 in the npn region,
The p-type collector electrode 45 and the p-type emitter electrode 46 in the pnp region,
The p-type gate electrode 47 in the nMOS region and the p-type source in the pMOS region
After forming the drain region 48, the n-type emitter electrode 53 and the n-type collector electrode 54 in the npn region, the n-type base electrode 55 in the pnp region, the n-type source / drain electrode 56 in the nMOS region, and the n-type gate electrode in the pMOS region Although 57 is formed, the order of forming these electrodes may be changed.

〔The invention's effect〕

As described above, according to the method of manufacturing a semiconductor device of the present invention, after forming a first polycrystalline silicon film, an impurity of a first conductivity type is introduced and processed into a predetermined shape to form a first conductive film. Forming a second polycrystalline silicon film, introducing a second conductivity type impurity, and processing it into a predetermined shape to form a second conductivity type electrode. As described above, the mask alignment step for impurity implantation at the time of forming each electrode becomes unnecessary, and the total number of steps can be reduced.

[Brief description of the drawings]

1A to 1F are cross-sectional views of respective steps of an embodiment of a method of manufacturing a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of a conventional semiconductor device, and FIGS. 3A to 3C are FIG. FIG. 14 is a cross-sectional view of the manufacturing process for the semiconductor device shown in FIG. In the figure, 27 is a silicon substrate, 37 and 52 are oxide films, 38 is a first polycrystalline silicon film, 39 is a CVD oxide film, 40 is a p-type base layer, 41 is an n-type base layer, and 44 is a p-type base layer. Electrode, 45 is a p-type collector electrode, 46 is a p-type emitter electrode, 47 is a p-type gate electrode, 48 is a p-type source / drain electrode, 51 is a sidewall, 53 is an n-type emitter electrode, 54 is an n-type collector electrode 55, an n-type base electrode, 56, an n-type source / drain electrode, 57, an n-type gate electrode, 58, 60, an emitter diffusion layer, 59,
61 is an external base diffusion layer, and 62 and 63 are source / drain diffusion layers. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A first region for forming a bipolar transistor having a base layer of a first conductivity type and a second region for forming a bipolar transistor having a base layer of a second conductivity type on the same semiconductor substrate. A third region for forming a MOS transistor having a channel region of the second conductivity type;
In a method of manufacturing a semiconductor device having a fourth region for forming a MOS transistor having a channel region of a conductivity type, a method for manufacturing a semiconductor device, wherein an oxide film is selectively formed only above the substrate in the third region. A step of sequentially depositing a first polysilicon film and a first insulating film, and then introducing a first conductivity type impurity into the first polysilicon film; The film is processed into a predetermined shape together with the first insulating film, and a base electrode is provided in the first region, an emitter electrode and a collector electrode is provided in the second region, a gate electrode is provided in the third region, and a source / drain is provided in the fourth region. Forming an electrode, forming side surfaces of the processed first polycrystalline silicon film and the first insulating film, and selectively forming an oxide film only on the substrate in the fourth region. Work Depositing a second polysilicon film and introducing a second conductivity type impurity into the second polysilicon film; processing the second polysilicon film into a predetermined shape; Forming an emitter electrode and a collector electrode in one region, a base electrode in the second region, a source / drain electrode in the third region, and a gate electrode in the fourth region, respectively; An emitter diffusion layer and an external base diffusion layer are formed in the third and fourth regions.
Forming a drain diffusion layer. A method for manufacturing a semiconductor device, comprising: