JPH0418752A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To dispense with a mask alignment process through which impurities are implanted at the formation of electrodes so as to lessen processes in number by a method wherein first conductivity type and second conductivity type electrodes are provided to a semiconductor device where an NPN, a PNP, an N channel, and a P channel MOS transistor are provided to the same substrate. CONSTITUTION:An N<+>-type buried layer 28, a P<+>-type buried layer 29, and an N<->-type epitaxial layer 30 are deposited on the surface of a P<->-type silicon substrate 27, a P-type channel cut layer 31 and an element isolation insulating film 32 are formed, P<->-type diffusion layers 33 and 34, an N<+>-type collector lead-out layer 35, and a P<+>-type collector lead-out layer 36 are deposited. A first polycrystalline silicon film and an insulating film are provided to the whole surface, and a P-type and an N-type base layer and a channel doped layer are provided through a thermal treatment. Furthermore, electrodes 44-48 are built, a second polycrystalline silicon film is deposited on all the surface, electrodes 53-57 are built, diffusion layers 58-63 are formed through a heat treatment, a passivation insulating film 64 is provided to the whole surface, and a wiring layer 65 is formed at a prescribed position.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to np+1. The present invention relates to a method of manufacturing a semiconductor device having a pnpl transistor and n-channel and p-channel MOS transistors on the same 't' conductor substrate.

[Conventional technology]

Figure 2 shows I E D M (Internal Nonal
Electron I)evlccs Moetin
g) Tech, Dig, 1988. Vertical r1pn, pnp transistor and CM shown on p780-763
FIG. 2 is a cross-sectional view of a mixed type LSI including OS transistors.

In the figure, 1 is a p-type semiconductor substrate, 2 and 3 are n-type and n+ type buried layers, 4 is a p+ type buried layer, 5 is an n-type epitaxial layer, 6 is an element isolation insulating film, and 7 is a p+ type 8 is a p-type diffusion layer, 9 is a p-type base diffusion layer,
10 is an n-type base diffusion layer; 1, 1. , , 1. ,2
is a channel doped region, 13 is an n-type base electrode, 14 is an n-type base electrode, 15 is an n-type sos/drain electrode, 16
are p-type source/drain electrodes, 17 is an n-type collector extraction electrode, 18 is a p-type collector extraction 7 electrode, ]9 is a passivation insulating film, 20 is an n-type emitter electrode, 21
- is an n-type emitter electrode, 22 is an n-type gate electrode, 23 is a p-type gate electrode, 24 is an n-type emitter diffusion layer, 25 is a p-type
26 is a wiring layer.

Here, npn and pnp are npn and pn p, respectively.
l □ Represents the area for forming transistors l~, n M Os
, pMos are lo channel and p channel MO3I, respectively.
- represents the area for the formation of transistors;

Next, the manufacturing process will be explained with reference to FIGS. 3A to 3C.

First, an n-type buried layer 2 is formed on the surface of the pnp region of the substrate 1, and an n+-type buried layer 3 is formed on the surface of the rlpn, pMO3 region, as shown in FIG. 3A. layer 2
A p-type buried layer 4 is formed on the surface of the substrate and the surface of the nMOS region, and then an n-type epitaaxial layer 5 is formed.

After forming the channel cut layer 7, an element isolation insulating film 6 is formed in a predetermined region to perform element isolation.
After forming the p-type diffusion layer 8 of the p+-type buried layer 4 in the p, nMO3 region, a thin nitride film]00 is formed on the − metal surface,
Grooves 101 reaching the n+ buried layer 3 and p+ buried layer 4 are formed in the collector lead-out portions of the npn and pHp regions, and a polycrystalline silicon layer 1.0 is formed in these grooves 101 and on the nitride film 1001.
form 2.

Next, as shown in FIG. 3B, the polycrystalline silicon layer 102 in the npn, nMO8 region is patterned into a predetermined shape, and a collector electrode layer 1.02a and a base electrode layer 102b are formed.
Then, a source/drain electrode layer 102c is formed, and one new PAD conductor insulating film is formed in a predetermined portion where the polycrystalline silicon layer 102 has been removed by patterning.
p, pM.

For the S region, collector, base, sos, and drain electrode layers are formed in the same manner.

Thereafter, using a mask with a predetermined pattern, the base electrode layer 102b in the npn region is
The collector electrode layer in the np region and the source layer in the 9MO8 region.
Boron (B) is implanted into the drain region 2, and an n-type base electrode 13. P-type collector exposed electrode 18. p-type source
While forming the drain electrode 16, a collector electrode layer 102a in the npn region is formed using a mask with another predetermined pattern.
, phosphorus (P) is implanted into the source/drain electrode layer 102c in the nMO3 region and the base electrode layer in the pnp region (not shown in FIG. 3B) to form the n-type collector extraction electrode 17.
．． n-type source/drain electrode 15 and n-type base electrode 1
form 4.

Furthermore, as shown in FIG. 3C, one insulating film in the region that will become the emitter and gate is removed, and the surface of each electrode is oxidized.
The nitride film 100 at the bottom of the region where the insulating film] 9 has been removed and the thin oxide film immediately below the nitride film 100 are etched laterally at the same time as they are removed, and polycrystalline silicon is deposited thinly over the entire surface again. After connecting the base electrode 13 and the n-type epitaxial layer 5 and connecting the source/drain electrode 15 and the p-type diffusion layer 8 using crystalline silicon, the emitter and gate regions are oxidized to form an emitter,
An insulating film 19 is also formed in the gate region, pnp, pMO3
The same process is performed for the area O and then, as shown in Figure 2, npn■) n
Predetermined impurities are implanted into the base region of the p region and the channel doped regions of the nMO8 and pMO8 regions to form respective diffusion regions 9 and 10 and channel dove regions 11 and 12, and into the emitter regions of the npn and pnp regions. After forming the emitter hole, polycrystalline silicon is deposited again, and arsenic (As) is introduced using another predetermined pattern mask.
[1 type emitter electrode 20. After forming a T]-type electrode 22 in the nMO8 region, B is introduced using a mask with a different predetermined pattern, and a p-type emitter electrode 21 is formed in the pnp region. P-type gate electrode 23 in pMO8 region
is formed, and by thermal diffusion when introducing these impurities, I
l-type emitter diffusion layer 24. After forming the p-type emitter diffusion layer 25, a contact pole is opened at a predetermined position to form a wiring layer 26, and desired wiring is performed.

[Problem to be solved by the invention]

In conventional semiconductor device manufacturing methods, n-type base electrode]4
Since the type of implantation is different between the n-type source/drain electrode 15 and the p-type base electrode 13 and p-type source/drain electrode 16, the・A mask alignment process for resist, etc., and another mask alignment process for impurity implantation when forming p-type electrodes 1B and 16 are required;
times are required.

In addition, since the n-type emitter electrode 20 and n-type gate electrode 22 and the p-type emitter electrode 21 and p-type gate electrode 23 are also different in injection type, a mask for forming the n-type electrode 20 and 22 is used. A matching process and a mask matching process for forming the p-type electrodes 21 and 23 are required.

As described above, there is a problem in that a large number of mask alignment steps are required to implant impurities when forming each of the electrodes 13-16 and 20-23.

The present invention has been made to solve the problem of "duplication" and aims to reduce the number of mask alignments required for impurity implantation when forming each electrode.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention includes
a first region for forming a bipolar transistor having a base layer of a first conductivity type;
A MOS having a second region for forming a bipolar transistor having a base layer of 'rTX type, a third region for forming a MO3+- transistor having a channel region of the second conductivity type, and a channel region of the first conductivity type. A semiconductor device manufacturing method for manufacturing a semiconductor device including a fourth region for forming a transistor, the step of slowly and selectively forming an oxide film above the substrate in the third region; 1
a step of sequentially depositing a first polycrystalline silicon film into which conductivity type impurities are introduced and a first insulating film, and processing the first polycrystalline silicon film together with the first insulating film into a predetermined shape. , forming a base electrode in the first region, an emitter electrode and a collector electrode in the second region, a gate electrode in the third region, and a source/drain electrode in the fourth region; a step of forming an insulating film on the side surfaces of the first polycrystalline silicon film and the first insulating film; a step of selectively forming an oxide film only above the substrate in the fourth region; and a step of forming an oxide film on the entire surface. The process of depositing a second polycrystalline silicon film into which two conductivity type impurities are introduced, and
A polycrystalline silicon film is processed into a predetermined shape, and an emitter electrode and a collector electrode are formed in the first region.

Forming a base electrode in the second region, a source/drain electrode in the third region, and a gate electrode in the fourth region, and forming an emitter diffusion layer and an external base diffusion layer in the first and second regions by heat treatment. and the third. The method is characterized in that it includes an upper step of forming a source/drain diffusion layer in the fourth region.

[Effect]

In this invention, a first polycrystalline silicon film doped with impurities of a first conductivity type is formed, processed into a predetermined shape to form each electrode of the first conductivity type, and impurities of a second conductivity type are introduced. In order to form each electrode of the second conductivity type by forming the introduced second polycrystalline silicon film and shaping it into a predetermined shape,
This eliminates the need for mask alignment for impurity implantation during the formation of each electrode, which is required in the past, and the overall number of steps can be reduced.

〔Example〕

FIGS. 1A to 1F are cross-sectional views of an embodiment of the method for manufacturing a semiconductor device of the present invention, and each step L will be explained below.

However, 2. In these figures, npn, pnpnMO
3, pMO8 is the first. Second. Third. NPN transistor + pnp transistor corresponding to the fourth region, n-channel MO8 transistor, p-channel MO3
The regions for forming +- transistors are shown respectively.

First, as shown in FIG. 1A, a p-type silicon substrate 27
An n+ type buried layer 28 is formed on the surface of the pnp, pMO3
After forming a p+ type buried layer 29 on the surface of the buried layer 28 in the region, an n- type epitaxial layer 30 is deposited on the entire surface, and element isolation insulation is performed so that a p type channel cut layer 31 is formed on the bottom surface. A film 32 is formed, and p-type diffusion layers 33 and 34 are formed in the epitaxial S normal layer 30 in the pnp and nMO5 regions, respectively.
At the same time, n+ is formed in the npn and pnp regions, respectively.
A type collector extraction layer 35 and a p+ type collector extraction layer 36 are formed.

Thereafter, p-type impurity ions such as B+ are implanted into the n-type epitaxial layer 30, which will become the base region of the npn region, and the p-type diffusion layer 3, which will become the base region of the pnp region.
3, n-type impurity ions such as P+ are implanted into n M O
Channel doping ions are implanted into the surfaces of the p type diffusion layer 34 in the S region and the n type epitaxial layer 30 in the pMO8 region for threshold voltage control.

Then, as shown in FIG. 1B, after oxidizing the entire surface to form an oxide film, the oxide film is etched so that the oxide film 37 remains only on the surface of the p-type diffusion layer 34 in the nMOS region. , a first polycrystalline silicon film 38 is formed on the entire surface.
Then, three CVD oxide films as a first insulating film are sequentially deposited, and then p-type impurities are doped into the polycrystalline silicon film 38 through the three CVD oxide films. At this time, by heat treatment during formation of the CVD oxide film 39, p-type base layers 40 are formed in the npn and pnp regions, respectively. An n-type base layer 41 is formed, and channel doped layers 42 and 43 are formed in the nMO8 and pMO3 regions.

Furthermore, as shown in FIG. 1C, the p-type polycrystalline silicon film 38 and the oxide film 39 are processed into a predetermined pattern, and the npn
A p-type base electrode 44. An n-type collector electrode 45 and a p-type emitter electrode 46. A p-type gate electrode 47 is formed in the nMO8 region, and an n-type source/drain electrode 48 is formed in the pMO3 region.

At this time, by patterning the polycrystalline silicon film 38 and the oxide film 39, an opening 4 is formed in the emitter region of the npn region.
At the same time, an opening 50 is formed in the gate region of the pMO5 region.

Next, as shown in FIG. 1D, side walls 51 made of an insulating film are formed on the side surfaces of each of the electrodes 44 to 48 formed by patterning and the oxide film 39 thereon, and then a thin oxide film is formed again. The oxide film is etched so that the oxide film 52 remains only in the opening 50 in the p-IQs region.

Then, as shown in FIG. 1E, a second polycrystalline silicon film is deposited over the entire surface, and this polycrystalline silicon film is
After implanting type impurities, this is patterned to form an np
An n-type emitter electrode 53 is formed in the opening 49 in the n-region, and an n-type collector electrode 54 is formed on the collector lead-out layer 35. An n-type base electrode 55. is formed on the base layer 41 in the pnp region. An n-type source/drain electrode 56 is formed on the p-type diffusion layer 34 in the nMO3 region, and an n-type gate electrode 57 is formed on the n-type epitaxial layer '30' in the pMO3 region.

Furthermore, as shown in FIG. 1F, by heat treatment, np
Emitter electrode 53 in n-type base layer 40 in n region
and an n+ type emitter diffusion layer 58 under the base electrode 44.
and a p+ type external base diffusion layer 59, respectively, and a p+ type emitter diffusion layer 60 and an n+ type external base diffusion layer 61 are respectively formed under the emitter electrode 46 and the base electrode 55 in the n type base layer 41 in the pnp region. An n+ type source/drain diffusion layer 62 is formed under the source/drain electrode 56 of the p diffusion layer 34 in the nMOS region, and an n+ type source/drain diffusion layer 62 is formed under the source/drain electrode 48 of the r] type epitaxial layer 3o in the pMO3 region. After forming a p+ type source/drain diffusion layer 6'3, a passivation insulating film 64 is formed on the entire surface, and contact holes are opened at predetermined positions (7. By forming a wiring layer 65, an npn, pnpl transistor) is formed. and n
A semiconductor device including M OSp M OS transistors is completed.

In addition, in the two-legged embodiment, the p-type base electrode 4 in the npn region
4. A p-type collector electrode 45 and a p-type emitter electrode 46 in the pnp region. p-type gate electrode 47 in nMO8 region. pM
After forming the n-type source/drain regions 48 in the O3 region, the n-type emitter electrode 5'3 and the n-type collector electrode 54 in the npn region, the n-type base electrode 55 in the pnp region. nM
r] type source/drain electrodes 56 in the O3 region. pMO8
Although the r1 type gate electrode 57 in the region is formed, the order in which these electrodes are formed may be reversed.

〔Effect of the invention〕

As described above, according to the method of manufacturing a semiconductor device of the present invention, a first polycrystalline silicon film doped with a first conductivity type impurity is formed, and this is processed into a predetermined shape to form a first conductivity type impurity. Each electrode is formed by forming a second polycrystalline silicon film doped with a second conductivity type impurity, and processing this into a predetermined shape to form each second conductivity type electrode. , the mask alignment process for impurity implantation when forming each electrode is no longer necessary, and the overall number of steps can be reduced.

[Brief explanation of drawings]

1A to 1F are cross-sectional views of each step of an embodiment of a method for manufacturing a conductor device according to the present invention, FIG. 2 is a cross-sectional view of a conventional semiconductor device, and FIGS. 38 to 3C are The figure is the second
This is a sectional view of the manufacturing process of the 6-conductor device shown in the figure. In the figure, 27 is a silicon substrate, 37.52 is an oxide film, 38 is a first polycrystalline silicon film, 39 is a CVD oxide film, and 40 is a 41 is a p-type base layer, 44 is a p-type base layer, and 44 is a p-type base layer.
type base electrode, 45 is p type] 6 collector electrode, 46 is p type gate electrode, 47 is ■) type gate electrode, 48 is n type source/drain electrode, 5] is Zide wall, 53 is n type emitter electrode, 54 is an n-type collector electrode, 55 is an n-type base electrode, and 56 is an n-type source electrode.
57 is an n-type gate electrode, 58.60 is an emitter diffusion layer, 59.6] is an external base diffusion layer, 62.
63 is a source/drain diffusion layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) On the same semiconductor substrate, a first region for forming a bipolar transistor having a base layer of a first conductivity type, a second region for forming a bipolar transistor having a base layer of a second conductivity type, and a second region for forming a bipolar transistor having a base layer of a second conductivity type. Manufacture of a semiconductor device for manufacturing a semiconductor device including a third region for forming a MOS transistor having a channel region of two conductivity types and a fourth region for forming a MOS transistor having a channel region of first conductivity type The method includes: selectively forming an oxide film only above the substrate in the third region; and sequentially forming a first polycrystalline silicon film doped with impurities of a first conductivity type and a first insulating film over the entire surface. processing the first polycrystalline silicon film together with the first insulating film into a predetermined shape, forming a base electrode in the first region, an emitter electrode and a collector electrode in the second region, and depositing a base electrode in the first region, an emitter electrode and a collector electrode in the second region, and a step of depositing the first polycrystalline silicon film together with the first insulating film into a predetermined shape. a step of forming a gate electrode in the region and a source/drain electrode in the fourth region; a step of forming an insulating film on side surfaces of the processed first polycrystalline silicon film and the first insulating film; a step of selectively forming an oxide film only above the substrate in a fourth region; a step of depositing a second polycrystalline silicon film doped with a second conductivity type impurity over the entire surface of the second polycrystalline silicon film; Processing a silicon film into a predetermined shape, forming an emitter electrode and a collector electrode in the first region, a base electrode in the second region, a source/drain electrode in the third region, and a gate electrode in the fourth region. and forming an emitter diffusion layer and an external base diffusion layer in the first and second regions by heat treatment, and forming source/drain diffusion layers in the third and fourth regions. Method of manufacturing the device.