JPS62181458A - Complementary type mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to absorb a current at a position as deep as a well, by providing a groove deeper than source and drain regions in a guard band forming part, diffusing impurities from the groove part, and providing a high concentration impurity region. CONSTITUTION:A part of a thin oxide film 24 on the surface of a substrate 21 is etched away. With oxide films 23 and 24 as masks, anisotropic etching is performed, and a groove part 43 having a width of 0.8mum and a depth of 1.5mum is formed. boron is diffused from polycrystalline silicon 25, in which boron is doped, into the silicon substrate 21 through the side surface and the bottom surface of the groove part 43. A P<+> high concentration impurity region 26 is formed at a deep position of the substrate surrounding the groove part 43. Thereafter, contact holes are provided in source and rain regions 28, 29, 31 and 32, and Al wirings 34 are formed. Thus, a large current, which causes latch-up, is absorbed from the guard band and the high concentration substrate. The abnormal conduction of the current in the semiconductor device can be blocked.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a CMOS semiconductor device having full latch-up resistance and a method for manufacturing the same.

[Prior art]

Conventionally, countermeasures against latch-up have been considered in OMOS (phase complex MOS) semiconductor devices. A conventional example is shown in FIG. In this device, an N-type well region 2 is formed on a P-type semiconductor substrate.
is formed. An element isolation insulating film 3 is selectively provided on the substrate surface.

On the surface of the substrate 1 surrounded by this impurity, an N+ type high concentration impurity region 4. which becomes the drain and source of the transistor.
An N-channel MOS transistor Trl is provided, which includes a gate electrode 6 and a gate electrode 6 with a gate oxide film interposed therebetween. On the other hand, on the surface of the N-well 2, a P-channel MOS transistor Tr2 is provided, which is made up of P-type high-concentration impurity regions 7 and 8, which serve as the source and drain of the transistor, and a gate electrode 9 with a gate oxide film interposed therebetween. This T, 1 and Tr2
In order to prevent latch-up, a guard band -0 containing a P+ type impurity at a high concentration and having a shallow depth similar to that of the high concentration impurity regions 4, 5, and 7.8 is provided between the two.

This guard band -O is connected to the source region 5 of Trl so as to have the same potential Vss.

In a CMOS semiconductor device configured as described above, latch-up occurs when T, 1,
T, 2 sources 5, 7, P type substrate 1 and N well 2, respectively
A PNPN thyristor is formed with and, and when a CMOS semiconductor device with and is operated, there is no damage due to trigger input such as noise.
This is a phenomenon in which parasitic bipolar transistors such as &PNP and NPN occur in various places and form a closed loop, and a large current continuously flows from the power supply VDD to the ground, and continues to flow until the power supply is turned off. The current flowing between the N-well 2 and the joint region 5 is sucked out from the guard band 10, and the potential around the joint region 50 is kept below the voltage at which a large current begins to flow.

[Problem that the invention seeks to solve]

The guard bands of the conventional device are 'I'l, T, and 2.
The depth of the drain region is approximately the same as that of the drain region.

Since the large current that causes latch-up flows deep at the bottom of the well, which is very shallow compared to the well region, a conventional shallow guard band cannot sufficiently improve latch-up resistance.

The present invention aims to form a guard band that can draw out current even at a position as deep as the well.

[Means to solve the problem]

In the present invention, a highly doped guard band of the same type as the substrate is formed between the P-channel and N-channel MOS transistors (1'% CMOS Si transistors) deep in their source/drain regions by the method described below. By forming this, the problems of the conventional method were solved.

The first method is to use the guard band forming part K/-S.
A groove was provided slightly deeper than the drain region, and impurities were diffused from this groove to provide a high concentration impurity region.

In the second method, ion implantation with varying acceleration voltages was carried out in multiple stages into the guard band formation region, and a highly concentrated impurity region was formed even deeper than the thin drain region by thermal diffusion.

[For production]

In the CMOS semiconductor device configured as described above, even if a large current flows from the well to the high concentration impurity region of the MOS transistor formed on the substrate surface, the flow is deeper than the high concentration impurity region of the MOS transistor.

The guard band, which is of the same type as the substrate and has a high concentration, absorbs this large current, and the voltage near the high concentration impurity region of the MOS transistor does not reach the level where latch-up occurs.

〔Example〕

Embodiment vi of the present invention - All of the manufacturing methods shown in FIGS. 1a-g are shown together.

Thermal oxidation 11 on P-type silicon substrate 21! l form resist h
After T coating, patterning is performed, impurities such as phosphorus are introduced by ion implantation, etc., and after the resist is removed, thermal diffusion is performed to form the N well 22. (Illustrated in FIG. 1a) Next, an oxide film 41° with a film thickness of 500A and a nitride film 42 with a film thickness of 2500A
All portions other than the element region are selectively removed by sequential CVD method. (Illustrated in Figure 1) Next, the first
As shown in Figure C, the nitride film 4 is thermally oxidized at 1000°C.
2t - The element isolation oxide film 23 is made to a thickness of 7 by using an oxidation-resistant mask.
000A, and the oxide film 41 and nitride film 42 are completely etched away. Subsequently, thermal oxidation is performed again at 1000°C to form an oxide film 24 of 000^, and a thin oxide IL@24 is formed on the surface of the substrate 21 where the groove 43 is to be formed.
A part of the oxide film was removed by etching, and anisotropic etching (IE) was performed as a 23°24t oxide film with a width of 0.8
A groove 43t having a depth of 1.5 μm and a depth of 1.5 μm is formed. (@1
(Illustrated in FIG. d) Subsequently, 600 OA of polycrystalline silicon 44 containing poron is deposited to a thickness of 600 OA, and is sufficiently deposited inside the S portion 43. (Illustrated in FIG. 1 e) Next, as shown in FIG.
Etching is performed using the E method, and heat treatment is performed for 10 minutes in a N2 atmosphere at 1000°C. Boron is diffused into the silicon substrate 21 from this polycrystalline silicon 25 fully doped with boron through the side and bottom surfaces of the trench 43 to form a P+ high concentration impurity region 26 at a deep position in the substrate surrounding the trench 43. Next, a polycrystalline silicon layer is deposited on the entire surface, and a silicate gate electrode 27 is entirely formed by selective etching. Using this gate electrode 27 as a mask, ions of impurities such as arsenic are implanted, and a high concentration drain source region is formed. 28,291-formation.

A gate electrode 30t made of polycrystalline silicon is similarly formed on the quintic N well 22 forming the transistor Tr1 (N-type MOS) transistor Tr1, and impurities such as boron are ion-implanted to form a door-shaped heavily doped source/drain region. 31 and 32 are formed, and a P-type MOS) transistor Tr2 is formed. (Illustrated in FIG. 1g) Next, a 1.1 μm thick CVD silicon oxide film containing BPSGt was deposited on the entire surface, and the guard bands 24, 2
5. Gate electrode 27.30. Contact holes are provided in the source Φ drain regions 28, 29, 31, and 32 of Trl and Tr2, and are formed in At interconnections a34'. (Illustrated in the first diagram) The CMOS semiconductor device manufactured through the above steps is
A girt band 24.25 deeper than each source drain/region 28, 29° 31.32 is obtained and the well 22
Even the current flowing from the bottom of the guard band 24
．． 25, which improves latch-up resistance. Further, the groove portion 43 is formed by anisotropic etching and can be etched deeply with a narrow width, so that it does not greatly affect the improvement in the degree of integration. In this manufacturing method, the trench 43 is formed after the element isolation oxide film 23t is formed.
3. This is to prevent stress from being applied to the surrounding area, which can cause defects. However, in cases where the influence of stress is small, or when element isolation is performed using the 5EPOX method, which has little effect on the silicon substrate, or the BOX method, which does not perform any heat treatment.

The groove portion 43 can be formed before element isolation.

Next, other embodiments are shown in FIGS. 2a to 2c. P-type silicon substrate 21, N-type well 22 and element isolation oxide film 231!
-The forming process is the same as in the first embodiment. (See @1 Figures a to C) Subsequently, as shown in Figure 2 a, the oxide film 24 is formed again, and impurities such as boron are added to the guard band forming portion 45 while changing the acceleration voltage to Trl and Tr2. Ion implantation is performed in multiple stages, even to positions deeper than the source/drain regions. Subsequently, high-temperature treatment is performed to fully perform thermal diffusion to obtain a guard ring 45 with a high concentration to a deep position.

(Illustrated in FIG. 2) Next, as in the process of the first embodiment shown in FIG.
MOS transistor Tr2 is formed.

As shown in FIG. 2C, a CMOS semiconductor device having a highly doped guard link 45f deeper than the source/drain regions 28, 29, 31, and 32 of TI and Tr2 to near the bottom is formed.

In addition, as another example, as shown in FIG.
In the embodiment shown in the figure, an epitaxial substrate in which a silicon single crystal 52 with a low concentration (~1015/c!i) is grown on a silicon substrate 51 with a thickness of 10/- or more is used, and the high concentration portion 51 is formed with a guard band 26. They were connected to have the same potential. This allows the large current that causes latch-up to be sucked out from the guard band 26 and the highly concentrated substrate 51, thereby further improving latch-up resistance.

In this embodiment, the case where the guard band is provided on the substrate side has been described, but it can also be provided on the well side. In this case, the conductivity type of the impurity implanted into the guard band is the same as that of the well, but other conditions are the same.

In this example, a %P-type substrate was used, but N
A similar effect can be obtained in the case of a semiconductor device including a P-well region using a molded substrate.

〔Effect of the invention〕

As explained above, according to the present invention, the large current that causes latch-up from the guard band and the high-concentration substrate can be fully extracted.
Abnormal flow of current in the semiconductor device t? Since the latch-up resistance can be significantly improved, the minimum trigger current that causes latch-up can be increased by 10 to 100 times that of the conventional device even when an epitaxial substrate is not used.

[Brief explanation of drawings]

FIG. 1 shows a manufacturing method and the number of grooves in a semiconductor device according to one embodiment of the present invention, and FIGS. 2 and 3 show other embodiments. 23... Oxide film for element isolation 24... Groove polycrystalline silicon 25. 45... Height 1 degree, guard band in the inert region Doujin i Separate coujin j Figure 1? 526 Figure 2 nl 〆55 Ushi 2 Figure 3/U Sono 4I21

Claims (1)

[Claims] 1) A semiconductor substrate of one conductivity type, a semiconductor well region of another conductivity type provided in a part of this semiconductor substrate, and source/drain regions of another conductivity type provided on the surface of the semiconductor substrate. a second MOS transistor provided on the surface of the semiconductor well region and having source/drain regions of one conductivity type; and a second MOS transistor provided between the first MOS transistor and the second MOS transistor, and an impurity region of one conductivity type or the other conductivity type formed deeper and more highly concentrated than the source/drain region of the second MOS transistor and connected to the same potential as the source of the first or second MOS transistor. Complementary MOS transistor. 2) The high concentration impurity region of one conductivity type provided between the first MOS transistor and the second MOS transistor is as deep as the semiconductor well region, and has a doping amount of 1.
2. The complementary MOS transistor according to claim 1, characterized in that it is 0^1^8/cm or more. 3) A step of introducing an impurity of the other conductivity type into a part of the semiconductor substrate of one conductivity type to form a low concentration semiconductor well region of the other conductivity type, and selectively forming an element isolation insulating film on the surface of the substrate,
defining a first element region and a second element region in each of the one conductivity type semiconductor substrate and the other conductivity type semiconductor region; and forming a groove between the first element region and the second element region. , a process of depositing polycrystalline silicon containing a high concentration impurity of one conductivity type or the other conductivity type inside the groove, and diffusion from the groove part by heat treatment to form a high concentration impurity of one conductivity type or the other conductivity type around the groove. and a step of introducing impurities of opposite conductivity type into the first element region and the second element region, respectively, to form a different conductivity channel type MOS transistor and a single conductivity channel type MOS transistor. A method for manufacturing a complementary MOS transistor. 4) A step of introducing an impurity of the other conductivity type into a part of the semiconductor substrate of one conductivity type to form a semiconductor region of the other conductivity type at a low concentration, and selectively forming an element isolation insulating film on the surface of this substrate. a step of defining a first element region and a second element region in each of the conductivity type semiconductor substrate and the other conductivity type semiconductor region; and impurities of one conductivity type or the other conductivity type between the first element region and the second element region. A process of performing ion implantation in multiple stages by changing the acceleration voltage to form a highly concentrated impurity region of one conductivity type or the other conductivity type by thermal diffusion, and implanting an opposite conductivity type in the first element region and the second element region, respectively. By introducing impurities, a multi-conducting channel type MOS transistor and a single-conducting channel type MOS transistor
1. A method for manufacturing a complementary MOS transistor, comprising the steps of forming an OS transistor. 5) The method of manufacturing a complementary MOS transistor according to claims 3 and 4, wherein the one conductivity type substrate is formed by epitaxially growing a low concentration single crystal on a high concentration substrate.