JPH01157565A - Manufacture of bi-mos integrated circuit device - Google Patents

Abstract

PURPOSE:To microstructure an NPN transistor and to enable high speed operation, by forming an emitter region, a collector region, primary and secondary source regions, and primary and secondary drain regions then forming an emitter and a collector by patterning a secondary polycrystalline silicon layer. CONSTITUTION:After a resist 24 is removed, boron is ion-implanted through a pattern oxide film 11 to form a P-type base region 12. The pattern oxide film 11 is selectively etched to form diffusion windows 28a, 29a, 30a. After a polycrystalline silicon layer 13 is grown entirely, arsenic is ion-implanted to dope the whole region with an N-type impurity. Then, after an oxide film 27 is formed on the silicon layer 13, thermal treatment is carried out to form regions 28, 29, 30. The silicon layer 13 is patterned to leave electrode regions 28b, 29b only and the other region is etched and removed. Thereafter, the oxide film 11 is eliminated completely and a pattern oxide film 31 is formed. After a BPSG film 19 is grown, holes are opened on a BPSG film 19 and an oxide film 31, then electrodes 20, 21, 22, 23 are formed by evaporating aluminum. In this way, it is possible to fine elements and reduce parasitic MOS capacity between an emitter and a base.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a silicon gate MO3) B1-MO3 in which a run transistor and a bipolar transistor are formed on the same substrate.
The present invention relates to a method of manufacturing an integrated circuit device.

[Prior Art] In the conventional manufacturing method of a Bi-MO3 integrated circuit device in which an NPN bipolar transistor (hereinafter referred to as an NPN transistor) and an N-channel MOS + Hernan transistor (hereinafter referred to as an NMO3 Rancisister) are formed on the same substrate, In order to shorten the process, generally the emitter region and collector contact region of the NPN transistor and the source/drain region of the NMOS transistor are formed at the same time. In addition, when attempting to operate an NPN transistor at high speed, it is necessary to form the emitter shallowly, so by driving in arsenic with a small diffusion coefficient through the polycrystalline silicon layer, a shallow N++ emitter region is formed. is formed.

FIGS. 3(a) to 3(e) are cross-sectional views showing a conventional manufacturing method of a Bi-MO3 integrated circuit device in the order of steps.

First, as shown in FIG. 3(a), after forming an N+ type buried region 2 in an appropriate region of a P− type silicon substrate 1, a P+ type buried region 3 and a P+ type insulating region 4 are simultaneously formed. . Next, after growing an N- type epitaxial layer 5 over the entire surface of the substrate, a P+ type buried region 3 is formed in the epitaxial layer 5.
A P-type well region 6 is formed so as to connect to the
form. Next, after selectively forming an oxide film 8 for element isolation, a gate oxide film 9 of an NMOS transistor and a gate electrode 10 made of a first polycrystalline silicon layer are patterned on the substrate surface of the P-type well region 6. Form.

Next, as shown in FIG. 3(b), after forming a first pattern oxide film 11 on the entire surface, a P-type base region 12 of an NPN transistor is formed. Next, the first pattern oxide film 11 is selectively etched to form an emitter diffusion window 16a and a collector diffusion window 17a of the NPN transistor, and then a second polycrystalline silicon layer 13 is grown on the entire surface.

Next, as shown in FIG. 3C, the second polycrystalline silicon layer 13 is patterned and removed so as to remain only in the emitter electrode region 16b near the emitter diffusion window 16a and the collector electrode region 17b near the collector diffusion window 17a. do. Next, the exposed first pattern oxide film 11 is completely removed, and a new second pattern oxide film 14 is formed.

Next, as shown in FIG. 3(d), the resist 15 is patterned, and the resist 15 is used as a mask to form, for example,
By thermally diffusing arsenic after ion implantation, the surface concentration is 1020 to 1021 cm-3 and the depth is approximately 0.2 cm.
μm N++ emitter region 16 and N0 type collector contact region 17 and surface concentration between 1020 and 1021
N++ source/drain regions 18 with a depth of about 0.4 μm and a depth of about 0.4 μm are formed.

Next, as shown in FIG. 3(e), a BPSG film (
After forming silicon oxide M) 19 containing B and P,
The BP'SG film 19 and the second pattern oxide film 14 are selectively etched to form holes, and aluminum is deposited in the holes to form the emitter electrode 20, base electrode 21 and collector electrode 22 of the NPN transistor, and the NMO3) transistor. Source/drain electrodes 23 are formed.

[Problems to be Solved by the Invention] However, in the conventional manufacturing method of the Bi-MO3 integrated circuit device described above, in order to form an NPN transistor, a single photolithography process (hereinafter referred to as PR) is first performed. ) to pattern the second polycrystalline silicon layer 13 so that only the emitter electrode region 16b and the collector electrode region 17b remain [FIGS. 3(b) and 3(c)]. Then, a resist 15 is formed by a second PR, and arsenic ions are implanted into the emitter electrode region 16b and the collector electrode region 17b of the second polycrystalline silicon layer 13 using the resist 15 as a mask.

For this reason, in anticipation of mask misalignment in the two PRs, the second polycrystalline silicon layer 13 is patterned in the first PR with the emitter electrode region 16b and collector electrode region 17b remaining slightly wider. This is disadvantageous in terms of miniaturization of each element. Moreover, the parasitic MO3 capacitance between the emitter and base increases by the extra extent of the emitter electrode region 16b and collector electrode region 17b of the second polycrystalline silicon layer 13, which is disadvantageous in terms of speeding up.

In addition, if mask alignment misalignment occurs, arsenic ions cannot be uniformly implanted into the entire area of the emitter electrode region 16b and collector electrode region 17b remaining after patterning, and the emitter electrode region 16b and the collector electrode region 1
In 7b, the concentration locally varies. Therefore, there is a problem that variations occur in the emitter ground current amplification factor (hereinafter referred to as h14) and the emitter resistance.

On the other hand, in order to shorten the process, the source/drain region 18 of the NMOS transistor is replaced by the emitter region 16 and collector contact region 17 of the N P N l-transistor.
formed at the same time. Therefore, if the N+ type emitter region 16 is made shallow to increase the speed of the NPN) transistor,
The N+ type source/drain region 18 also becomes shallower, and at the junction with the P-type well region 6, the concentration gradient of the source/drain region becomes steeper, the electric field strength near the drain increases, and the source/drain breakdown voltage decreases. There is a problem with doing so.

The present invention has been made in view of such problems, and includes:
In addition to being able to miniaturize NPN transistors,
Bi-MO3 makes it possible to obtain an NPN transistor that is capable of high-speed operation and has reduced variations in common emitter current amplification factor and emitter resistance, and also to obtain an NMOS transistor with high source-drain breakdown voltage.
An object of the present invention is to provide a method for manufacturing an integrated circuit device.

[Means for Solving the Problems] A method for manufacturing a B i -MO3 integrated circuit device according to the present invention includes a step of forming a second region of a first conductivity type and a first region of a second conductivity type on a semiconductor substrate. a step of laminating a first oxide film and a first polycrystalline silicon layer locally on the first region; a step of forming a second oxide film over the entire surface;
forming a first source region and a first drain region of a first conductivity type by implanting impurities into the regions in a self-aligned manner using the first polycrystalline silicon layer as a mask;
selectively etching the second oxide film to form an emitter window and a collector window on the second region, a source window on the first source region, and a drain window on the first drain region; , forming a second polycrystalline silicon layer of the first conductivity type on the entire surface; and using the second polycrystalline silicon layer as an impurity source, injecting the first conductivity type into the second region through the emitter window and the collector window, respectively. At the same time, a second source region and a second drain region of a first conductivity type are formed in the first source region and first drain region through the source window and drain window, respectively. a step of forming;
The second source region and the second drain region are formed to be shallower and have a higher concentration than the first source region and the first drain region, respectively.

[Operation] In the present invention, first, a semiconductor substrate is provided with, for example, a first conductivity type second region of a bipolar transistor, and, for example,
A first region of a second conductivity type of a M OS +- transistor is formed. Next, a first oxide film and a first polycrystalline silicon layer are locally stacked on the first region. This allows M.O.
A gate oxide film and gate electrode of the S transistor are formed.

Next, a second oxide film is formed on the entire surface, and impurities are implanted using the first polycrystalline silicon layer as a mask, thereby forming a low concentration and deep first source region of the first conductivity type in the first region. and a first drain region is formed in a self-aligned manner.

Next, the second oxide film is selectively etched to form a source window and a drain window on the first source region and the first drain region, respectively, and an emitter window and a collector window on the second region. Form.

Next, a second polycrystalline silicon layer is grown over the entire surface, and ions of, for example, arsenic are implanted into the entire surface, thereby using the second polycrystalline silicon layer as an impurity source. Then, impurities are introduced into the substrate through each of the windows to form a first conductivity type emitter region, collector contact region, second source region, and second drain region. As a result, a highly doped and shallow second source region and a second drain region of the first conductivity type are formed in the first source region and first drain region, respectively. The first and second parts formed in this way
In the source region and the drain region, since the concentration gradient is relaxed, the source-drain breakdown voltage can be increased. In addition, since impurities are introduced into the entire second polycrystalline silicon layer and then into the substrate through good intentions, variations in the emitter common current amplification factor and emitter resistance of bipolar transistors in the manufacturing process are reduced. can do.

After forming the emitter region, the collector region, the first and second source regions, and the first and second drain regions, the second polycrystalline silicon layer may be patterned to form the emitter and collector.

In this case, there is no resist forming step for implanting arsenic ions in the subsequent steps, so there is no need to perform patterning in anticipation of misalignment. Therefore, in the present invention, it is possible to miniaturize the device, and since the patterned second polycrystalline silicon layer does not have any extra spread to account for misalignment, the parasitic MO3 capacitance between the emitter and the base is In addition, it is possible to reduce the amount of damage caused by the oxidation layer, and furthermore, it is possible to operate at high speed.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIGS. 1(a) to 1(e) are cross-sectional views showing a method for manufacturing a B1-MOS integrated circuit device according to a first embodiment of the present invention in order of steps. In the following description, the first conductivity type is assumed to be N type and the second conductivity type is assumed to be P type, but it goes without saying that the same effects can be obtained even if the polarities are changed.

First, as shown in FIG. 1 (a), by doping, for example, arsenic or antimony into an appropriate region of a P-type silicon substrate 1 with a concentration of 1014 to 1016 CIn-3, the layer resistance is increased to 10 to 50 Ω/. N+ type burial area in the mouth 2
Form. Next, by doping appropriate regions of the substrate 1 with, for example, boron, the layer resistance is increased to 100 to 500Ω.
A P+ type buried region 3 and a P+ type insulating region 4 are formed at the same time. Next, the resistivity becomes 0 over the entire surface layer of the substrate 1.
．． An N-type epitaxial layer 5 of 5 to 2 Ω·cm is grown.

Next, for example, by ion-implanting boron, P
A P-type well region 6 and a P-type insulating region 7, each having a layer resistance of 1 to 3 Ω/hole, are simultaneously formed so as to be connected to the +-type buried region 3 and the P+-type insulating region 4. Next, using the nitride film as a mask, an element isolation oxide film 8 having a thickness of about 1 μm is selectively formed.

Next, a thickness of approximately 400 mm is deposited on the substrate surface of the P-type well region 6.
A gate oxide film 9 of a NMOS (NMOS) transistor and a gate electrode 1o obtained by patterning a first polycrystalline silicon layer having a thickness of about 4,000 are formed.

Next, as shown in Figure 1(b), the entire surface has a thickness of approximately 60 mm.
A first pattern oxide film 11 of 0 people is formed. Next, a resist 24 is patterned, and using this resist 24 as a mask, ions of, for example, phosphorus are implanted into the substrate through the oxide film 11, so that the surface concentration is 1018 to 10.
An N-type collector contact region 25 of an NPN transistor and an N-type source/drain region 26 of an NMO3) transistor having a thickness of 19 cm' and a depth of about 0.6 μm are simultaneously formed in a self-aligned manner.

Next, as shown in FIG. 1C, after removing the resist 24, ions of boron, for example, are implanted through the first pattern oxide film 11 to reduce the layer resistance to 1 to 3 Ω/. A P-type base region 12 of the mouth is formed. Then the first
(NPN) by selectively etching the pattern oxide film 11
The emitter diffusion window 28a and collector diffusion window 29a of the transistor and the source/drain diffusion window 30a of the NMOS transistor are formed. These diffusion windows 28 are then
A thickness of 10 mm is applied to the entire surface, covering a, 29a, and 30a.
After growing the second polycrystalline silicon layer 13 of 00 to 3000 layers, for example, by ion-implanting arsenic,
The entire second polycrystalline silicon layer 13 is doped with N-type impurities. Next, on the second polycrystalline silicon layer 13, for example, a CVD method is used to form an oxide film 27 for injecting arsenic to a thickness of about 3000, and then the oxide film 27 is formed in a nitrogen gas atmosphere at a temperature of about 950°C. By heat treatment for 50 to 150 minutes, the surface concentration is 1020 to 1021 cm-3,
An N+ type emitter region 14=region 28, an N+ type collector contact region 29, and an N+ type source/drain region 30 having a depth of about 0.2 μm are formed.

Next, as shown in FIG. 1(d), the second polycrystalline silicon layer 13 is patterned so that only the emitter electrode region 28b near the emitter diffusion window 28a and the collector electrode region 29b near the collector diffusion window 29a remain. After removing other areas by etching, the exposed first pattern oxide film 11 is completely removed, and the entire surface is further oxidized to form a new second pattern oxide film 31 with a thickness of about 200 wafers. .

Next, as shown in FIG. 1(e), after growing one insulating BPSG film with a thickness of about 1 μm, this BPSG
selectively opening holes in the entire 192 pattern oxide film 31 of the film 19;
By vapor-depositing aluminum, the emitter electrode 20, base electrode 21, and collector electrode 22 of the NPN transistor and the source/drain electrodes 23 of the NM○S I-transistor are formed.

In this way, in order to form the (NPN) transistor region, the PR for arsenic ion implantation, which was conventionally required, is no longer necessary, so when patterning and removing the second polycrystalline silicon layer 3, this PR is used. There is no need to leave a slightly larger amount in consideration of misalignment, and it is possible to miniaturize the NPN transistor. In addition, as the emitter electrode region 28b of the second polycrystalline silicon layer 13 on the emitter region 28 spreads smaller, the emitter electrode region 28b on the emitter region 28, the first pattern oxide film 1, and the P-type base region 12 Since it is possible to reduce the parasitic MO3 capacitance between the emitter and base that is formed, furthermore, high-speed operation is possible. Furthermore, since the impurity arsenic is implanted into the entire surface of the second polycrystalline silicon layer 13, the arsenic concentration becomes uniform, so that variations in hPE and emitter resistance can be reduced. Further, by forming a shallow N+ type collector contact region 29 with a high concentration in the deep N type collector contact region 25 with a low concentration, collector series resistance can be reduced. This makes it possible to reduce the saturation voltage due to large current, and also to improve the characteristics of hPE in the large current region.

On the other hand, by forming the N+ type source/drain region 30, which is highly doped and shallow as in the conventional case, in the lightly doped and deep N type source/drain region 26 of the NMOS transistor region, a double diffusion type drain structure is formed. It can be realized. As a result, the concentration gradient in the source/drain region caused by the junction between the source/drain region and the P-type well region 6 is relaxed compared to the Bi-MO3 integrated circuit device manufactured by the conventional manufacturing method, so that the electric field strength near the drain is reduced. is reduced to about 1/2 to 1/3, making it possible to increase the source/drain breakdown voltage. Note that in order to form the N-type source/drain regions 26, only one PR process or an IPR process for arsenic ion implantation is unnecessary, so the number of PR steps does not actually increase. It is possible to improve the characteristics.

FIG. 2 shows B manufactured by the second embodiment method of the present invention.
FIG. 1 is a cross-sectional view showing a 1-MO3 integrated circuit device. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and their explanation will be omitted. The second example is NPN in the first example)
In addition to transistors and NM○S transistors, an N-type polycrystalline silicon resistor is also formed. That is, in the first embodiment, the emitter electrode region 28b and the collector electrode region 29b in the vicinity of the emitter diffusion window 28a and the collector diffusion window 29a are left, respectively, and the second polycrystalline silicon layer 1 is
When selectively etching 3, a polycrystalline silicon resistance layer 32, which becomes an N-type resistance region, remains as shown in FIG. Next, a second pattern oxide film 3 is formed on the region of the polycrystalline silicon resistance layer 32 through the same steps as in the first embodiment.
1 is grown, and further a BPSG film 19 is grown. Finally, a pair of N-type resistance electrodes 33 are formed.

In the second embodiment, after arsenic is ion-implanted into the entire surface of the second polycrystalline silicon layer 13, the second polycrystalline silicon layer 13 is patterned to form an N-type polycrystalline silicon resistance layer 3.
2, the impurity concentration of the polycrystalline silicon resistance layer 32 becomes uniform.

Therefore, variations in resistance are small and it is possible to form fine patterns.

[Effects of the Invention] As described above, according to the present invention, after forming a low concentration and deep first conductivity type first source region and first drain region through one photolithography process, Second
Impurities are implanted into the entire surface of the polycrystalline silicon layer to form a first conductivity type emitter region, a collector contact region, a second source region, and a second drain region, and a second polycrystalline silicon layer is formed on the emitter and collector. Since the patterning is performed in a single photolithography process so that only the second polycrystalline silicon layer remains, there is no need to account for misalignment when patterning the second polycrystalline silicon layer, so it is possible to miniaturize and speed up the device. Furthermore, since the impurities are uniformly implanted, variations in emitter resistance, emitter grounded current amplification factor, etc. during the manufacturing process can be reduced. Furthermore, since a double diffused drain structure is formed,
Source/drain breakdown voltage can be increased.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are cross-sectional views showing the manufacturing method of a B1-MOS integrated circuit device according to the first embodiment of the present invention in order of steps, and FIG. 2 is a second embodiment of the present invention. Cross-sectional view showing a B1-MOS integrated circuit device manufactured by the method, No. 3
The figures (a) to (e) are cross-sectional views showing a conventional method for manufacturing a B1-MOS integrated circuit device in the order of steps. 1; P− type silicon substrate, 2; N+ type buried region 3; P
+ type buried region, 4; P+ type insulating region, 5: N- type epitaxial layer, 6; P type well region, 7; P type assembly region,
8; oxide film for element isolation, 9; gate oxide film, 10; gate electrode, 11; first pattern oxide film, 12; P-type base region, 13; second polycrystalline silicon layer, 14, 31; second
Patterned oxide film, 15, 24; Resist, 16, 28;
N++ emitter region, 16a, 28a; emitter diffusion window, 16b, 28b; emitter electrode region, 17.29; N
++Collector contact region, 17a, 29a; collector diffusion window, 17b. 29b; Collector electrode region, 18.30; N++ source/drain region, 19. BPSG film, 20; emitter electrode, 21; base electrode, 22; collector electrode, 23; source/drain electrode, 25; N-type collector contact region, 26; N-type source/drain region, 27; oxide film for pushing arsenic, 30a: Source/drain diffusion window, 32; Polycrystalline silicon resistance layer, 33; N-type resistance electrode

Claims (1)

[Claims] forming a second region of a first conductivity type and a first region of a second conductivity type on a semiconductor substrate; and locally forming a first oxide film and a first polycrystalline silicon layer on the first region. forming a second oxide film over the entire surface; and implanting impurities into the first region in a self-aligned manner using the first polycrystalline silicon layer as a mask to form a first source region of a first conductivity type. and forming a first drain region, and selectively etching the second oxide film to form an emitter window and a collector window on the second region, a source window on the first source region, and the first drain region. forming a drain window over the drain region; forming a second polycrystalline silicon layer of the first conductivity type over the entire surface; and forming the emitter window and the collector window using the second polycrystalline silicon layer as an impurity source. An emitter region and a collector contact region of a first conductivity type are respectively formed in the second region through the wafer, and at the same time, a first conductivity type emitter region and a collector contact region of the first conductivity type are respectively formed in the first source region and the first drain region through the source window and the drain window. forming a second source region and a second drain region, the second source region and the second drain region being respectively smaller than the first source region and the first drain region. A method for manufacturing a Bi-MOS integrated circuit device, characterized by forming a Bi-MOS integrated circuit device shallowly and with high concentration.