JP2648808B2 - Method for manufacturing bipolar transistor for BiCMOS - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor, and more particularly, to a BiCMOS (BismuthCompli).
mentary Metalloxide Semico
The present invention relates to a method for manufacturing a high-performance bipolar transistor used for a semiconductor device.

[0002]

2. Description of the Related Art Various types of bipolar transistors (BJTs) are used in BiCMOS, but two types are generally used most frequently. The first type of BJT is a base oxide region (BJT). oxi
de), the emitter region is determined. As shown in FIG. 13, the structure of a bipolar transistor commonly used in this type of BiCMOS is such that the base oxide region 11 of the BJT 1 is formed of a base region 12 and a base contact region 13. The base region 12 and the base contact region 13 are indirectly connected by the base connection region 14 grown by implanting the base connection boron ions. Therefore, the base has a relatively large electric resistance, and the diffusion of boron ions proceeds while the base oxide region 11 is growing. The surface breakdown voltage BV _cbo decreases, while the base connection region 14 also diffuses into the base region 12. However, the current gain of the BJT decreases, which adversely affects performance.

[0003] The structure of a second type of BJT is a conventional BiJT.
As shown in FIG. 14, which is a display diagram of a bipolar transistor structure used in CMOS, the BJT 2 separates a base region 22 and a base contact region 23 by a side wall spacer (Side Wall Spacer) 21. Although the distance between the base region 22 and the base contact region 23 can be shortened to greatly reduce the electric resistance of the base and improve the performance of the BJT, the implantation of high-concentration boron ions on the base contact region 23 significantly reduces the BJT emitter. Since it approaches the base connection surface, a high electric field is generated between the emitter and the substrate, and the destructive lightning pressure BV _{ebo on the} emitter-base connection surface decreases,
Problems easily occur at the interface, such as leakage and reliability. Of course, it is conceivable to increase the thickness of the side wall spacer 21 to reduce this effect, but this will have a great effect on the characteristics of the MOS. .

[0004]

SUMMARY OF THE INVENTION The above conventional BiCMO
In view of the problems in the method for manufacturing a bipolar transistor for S, an object of the present invention is to provide a method for manufacturing a bipolar transistor for BiCMOS that can reduce the base electric resistance of the bipolar transistor and improve its current gain.

[0005]

In order to achieve the above object, a method of manufacturing a BiCMOS device according to the present invention comprises the steps of: (a) forming a BiCMOS device having a bipolar transistor and NMOS and PMOS transistors;
Implanting first and second conductivity type impurities into the substrate to form adjacent first, second and third buried regions; and (b) implanting the first, second and third impurities. (C) depositing an epitaxial layer (37) over the entire substrate after forming the buried region, and (c) one of the NMOS and PMOS transistor wells is a bipolar transistor well and the other of the NMOS and PMOS transistor wells. To form a bipolar transistor well, an NMOS transistor well, and a PMOS transistor well in the region where the first, second and third buried regions are located. Implanting an impurity of the second conductivity type and (d)
(F) growing a silicon dioxide layer (43) on the surface of the bipolar, NMOS and PMOS transistor wells; (e) depositing a silicon nitride layer (45) on the silicon dioxide layer (43); A) a plurality of first isolation regions on each junction of the bipolar, NMOS and PMOS transistor wells;
Etching the silicon nitride layer (45) to expose a second isolation region on the surface of the bipolar transistor well adjacent to one of the isolation regions;
(G) growing a field oxide layer (51) on the first and second isolation regions; and (h) using the silicon nitride layer () to expose adjacent base oxide regions on the surface of the bipolar transistor well. (I) growing a base oxide layer (53) on the base oxide region to define the range of the emitter of the bipolar transistor; and (j) etching the silicon nitride layer (45). ) And the silicon dioxide layer (4)
And (k) a sacrificial oxide layer (55) on the bipolar, NMOS and PMOS transistor wells.
And (l) the second isolation region (51).
A deep collector contact of a bipolar transistor in a bipolar transistor well between the first transistor and an adjacent one of the plurality of first isolation regions.
(M) removing the sacrificial oxide layer (55); and (n) removing the bipolar, NMOS and P
A gate oxide layer (6) is formed on the surface of the MOS transistor well.
1) the process of growing, and (o) the thickness of the opposing portions of the facing base oxide layer (53) exposing the intrinsic base region (63) between the base oxide layers (53) on the bipolar transistor wells. (P) a base portion (65) between the base oxide layers (53), and a portion of the base disposed below an opposing portion of the base oxide layer; Implanting ions into the intrinsic base region to form an intrinsic base of a bipolar transistor having a base link portion (66) connected to the gate oxide layer (61); Depositing a polysilicon layer (67) on the base region (63); and (r) implanting an impurity into the polysilicon layer (67) to form a portion of the intrinsic base (63). Emitter region to the base surface (6
Driving in the impurities in the polysilicon layer (67) by a high-temperature heat treatment that allows the impurities to diffuse from the polysilicon layer (67) to form 9).

After the step (r), (s) N
Etching the polysilicon layer (67) to form the gate electrodes of the MOS and PMOS transistors and the polysilicon emitter (69) of the bipolar transistor; and (t) adding N to the NMOS transistor well.
Performing a LDD ion implantation of a P-type, performing P-type LDD ion implantation into a PMOS transistor well, and simultaneously performing one of the N-type LDD ion implantation and the P-type LDD ion implantation into the bipolar transistor well, and (u )
Depositing an oxide layer (71) on the bipolar, NMOS and PMOS transistor wells after the N-type LDD and P-type LDD ion implantation, and (v) LDD on each side wall of the gate electrode and the polysilicon emitter. Anisotropically etching the oxide layer (71) to form sidewall spacers (73); (w) source and drain (75) of the NMOS transistor, source and drain (77) of the PMOS transistor, Implanting first and second conductivity type impurities into the bipolar, NMOS and PMOS transistor wells to form a bipolar transistor base region (79) around the intrinsic base link portion; The present invention relates to a method for manufacturing a BiCMOS device including:

[0007]

According to the present invention, as described above, since a thinner base oxide layer is first grown before implanting ions into the base connection region, some ions are implanted during base ion implantation. An elongate base connection region can be formed underneath the layer to connect the BJT base to the base contact region, and the base contact region is ion implanted at the end of the manufacturing step, thus reducing manufacturing costs. In the step involving a high temperature in the first half of the step, the high concentration doping of the base contact region does not diffuse into the base region.

[0008] Then, the fourth step is referred to as "and then, after a silica layer is grown on the upper surface thereof, silicon nitride is vapor-deposited, and then the silicon nitride in the field region is etched using a photomask. Remove,
Further, another field oxide layer is grown by performing field ion implantation of boron in the field region of the N-type well using the photomask once again, so that not only the NPN-type BJT but also the PNP-type BJT
It is also a manufacturing step.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a method of manufacturing a BiCMOS bipolar transistor according to the present invention will be described. The present invention is based on the background art that the first type of BJT manufacturing method described above is too complicated and has a base connection. In the second type of BJT manufacturing method, the electric resistance of the region increases, and in the manufacturing process, the base connecting boron ions diffuse to the base region and the current gain decreases. Since a high electric field is generated and the connection surface has problems such as leakage and reliability, the research and development of the manufacturing method of the high performance bipolar transistor of the present invention is performed. A connecting region is formed between the base region and the base contact region, and at the same time, between the base contact region and the emitter-base connecting surface during the manufacturing process. By controlling is to improve the current gain to prevent leakage of the connecting surface.

FIG. 1 is a diagram showing steps of manufacturing a BiCMOS bipolar transistor according to the present invention. Each of the manufacturing steps will be described in order with reference to the drawings; (1) As shown in FIG. First, an N + buried layer (Buried Layer) is formed on the P-type substrate 31 by an ion implantation method.
er) 33 or both buried layers of N + and P buried layers are formed.

(2) Next, as shown in FIG. 2, an N-- epitaxy layer 37 or a P-- epitaxy layer (Epitaxial Layer) is grown on the upper surface.

(3) Further, as shown in FIG. 3, an N-type well (Well) 39 and a P-type well 41 are formed based on a conventional method.

(4) Then, as shown in FIG. 4, after an oxide film (SiO 2) 43 is grown on the upper surface, silicon nitride (Si 3 N 4) 45 is vapor-phase deposited (CVD), and then a photomask is formed. Utilize the field area (Fie1d
The silicon nitride 45 in the region 47 is removed by etching, and another field ion implantation 49 of boron is performed on the field region of the P-type well 41 by using a photomask once again to form a field oxide layer (layer). FieldOxi
de) Growing 51. This is a general LOCOS (L
ocal oxidation On Silico
n) Same as the working method of the insulation technology. The field oxide layer 51 can be formed in the region of the bipolar transistor well to separate the deep collector 59, as shown in FIG. 6, in addition to the boundary region of each well.

(5) Subsequently, as shown in FIG. 5, the silicon nitride is partially removed by etching again using a photomask, and then, a base oxide layer (Base oxide) 53 is formed on the etched portion. Is grown to define the emitter region of the BJT. This base oxide layer 5
The growth of No. 3 is made thicker than the oxide film 43 and is similar to the field oxide layer 51. The only difference is that no field ion implantation is performed.

(6) In this step, as shown in FIG. 6, all the remaining silicon nitride and the oxide film layer 43 thereunder are removed by etching to form a single sacrificial oxide layer (S
An amorphous oxide (55) is grown, and thereafter, a MOSFET (Metal oxide semi) is formed.
conductor field effect tr
The formation of the ionic layer 57 having a critical voltage is performed, and the BJT deep collector is formed.
The collector region 59 is formed by ion implantation to form a collector to reduce the series electrical resistance of the BJT collector.

(7) Next, as shown in FIG. 7, the sacrificial oxide layer 55 is removed by etching, and
1 is grown to an oxide layer for the MOSFET gate, and then the oxide layer on the upper surface of the region intended to be the BJT base region 63 is etched away using a photomask. At this time, portions of the two base oxide films 53 defining the intrinsic base region formed in a relatively thick film on the sides facing each other are also removed. As shown in FIG. 7, the thickness of a part of the base oxide layer 53 on the side of the intrinsic base region decreases. Further, boron ions are implanted as BJT base ions to form a P-type base 65 between the base oxide layers 53 and a base connection region 66 under the partially etched base oxide layer 53.

(8) Then, as shown in FIG. 8, one layer of polysilicon (Poly Si) 67 is vapor-phase deposited to form M
The gate of the OSFET and the emitter of the BJT are used, and then impurity ions of phosphorus (P) or arsenic (As) are implanted to make the polysilicon dope (Dope) N +.
Further, drive-in is performed at a high temperature to diffuse impurities from the polysilicon above the base region 65 in the silicon surface opening to form an N + emitter region 69. Since the thickness of base oxide film 53 serving as an opening is relatively large, emitter region 69 is formed substantially between base oxide films 53.

(9) As shown in FIG. 9, the polysilicon 67 is removed by etching using a photomask, and a MOSFET gate and a BJT emitter 69 are formed in the remaining polysilicon region. N-LDD (Light Doped D)
line) and P-LDD ion implantation, of which NMOS performs N-LDD ion implantation,
In the MOS and BJT portions, P-LDD ion implantation is performed. However, N-LDD ion implantation may be completely performed. (In the figure, since the manufacturing process of the NMOS portion belongs to the prior art, only the BJT portion is used. ), Followed by
A single oxide layer 71 is coated thereon.

(10) As shown in FIG. 10, the covering oxide layer 71 is anisotropically etched to
A side wall spacer (Spacer) 73 is formed.
There is a spacer region on the periphery of the polysilicon gate of the MOSFET and the polysilicon emitter of the BJT. To completely etch the spacer region, overetching must be performed without fail, and the spacer 73 of the polysilicon emitter 69 must be formed. Completely remove the base oxide layer at the outer edge of the substrate.

(11) In the following step, as shown in FIG. 11 including the MOS portion and the BJT portion, this step is the same as in a general MOSFET manufacturing process. First, an N + photomask (n-select mask) is used.
Using the source of the NMOS transistor (Source
e) N + ions are implanted into the drain and drain regions to form MOS source / drain 75. After that, a P + photomask (p-select mas)
Using k), P + ions are implanted into the source and drain regions of the PMOS transistor to form MOS source / drain 77. At this time, P + ions are also applied to the outside of the polysilicon emitter spacer 73, and a P + base contact region 79 is formed.

(12) Subsequently, an oxide layer and a BPSG (Boron Phosphos S) are formed by a conventional method.
and a metal layer is formed by drilling a contact hole to form a connection between the terminals of the BJT and the MOSFET component, and then another passivation film (Passivati) is formed.
On) is added to protect the metal lines, and finally several windows are opened in the protective film to help connect the integrated circuit during packaging. Then, as shown in FIG. 12, when heat treatment is added in these subsequent steps, the BJ
Since the base contact region 79 on the side surface of the T emitter region is laterally diffused and connected to the base connection region 66, the electric resistance of the base is greatly reduced and the performance of the BJT is improved. The above is an NPN-type BJT manufacturing step. However, in the case of a PNP-type BJT, the field ion implantation of boron in the field region of the P-type well is simply changed to the N-type well, and the base connection region is phosphorus or It is sufficient to substitute arsenic ions for implantation and polysilicon doping for boron ions, which is a very simple technique in the manufacturing steps, and will not be discussed here.

[0023]

According to the present invention having the above-described structure, B
The following effects are obtained in the process of manufacturing a bipolar transistor for iCMOS and the product thereof. Furthermore, since it is not necessary to implant another base connection region and the base region and the base contact region are directly connected, the electric resistance of the base can be reduced.

2. Since the connection depth of the base contact region and the base region is shallow, the standard size in the vertical direction can be reduced very easily.

3. Since the emitter-base junction surface is formed between the base oxide films, the distance between the base contact region and the emitter-base junction surface is kept relatively long, so that electric leakage does not occur easily and reliability is increased.

4. Since the base contact region does not diffuse into the base region, a decrease in current gain does not occur.

5. Therefore, the current gain of the manufactured BJT is improved, and the performance of the bipolar transistor used in the BiCMOS is improved.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing step of a BiCMOS bipolar transistor of the present invention.

FIG. 2 is a diagram showing a manufacturing step of a BiCMOS bipolar transistor of the present invention.

FIG. 3 is a view showing a manufacturing step of a BiCMOS bipolar transistor of the present invention.

FIG. 4 is a diagram showing a manufacturing step of a BiCMOS bipolar transistor of the present invention.

FIG. 5 is a diagram showing a manufacturing step of a BiCMOS bipolar transistor of the present invention.

FIG. 6 is a view showing a manufacturing step of the BiCMOS bipolar transistor of the present invention.

FIG. 7 is a diagram showing a manufacturing step of a bipolar transistor for BiCMOS of the present invention.

FIG. 8 is a diagram showing a manufacturing step of the BiCMOS bipolar transistor of the present invention.

FIG. 9 is a view showing a manufacturing step of the BiCMOS bipolar transistor of the present invention.

FIG. 10 is a diagram showing a manufacturing step of the BiCMOS bipolar transistor of the present invention.

FIG. 11 is a view showing a manufacturing step of the BiCMOS bipolar transistor of the present invention.

FIG. 12 is a view showing a manufacturing step of the BiCMOS bipolar transistor of the present invention.

FIG. 13 is a diagram showing a structural example of a conventional BiCMOS bipolar transistor.

FIG. 14 is a diagram showing another structural example of a conventional BiCMOS bipolar transistor.

[Explanation of symbols]

 Reference Signs List 31 base 33 single buried layer 35 double buried layer 37 epitaxy layer 39 N-type well 41 P-type well 43 silicon dioxide 45 silicon nitride 47 field region 49 field oxide layer 51 field oxide layer 53 base oxide layer 55 sacrificial oxide layer 57 ion Layer 61 Oxide layer 63 BJT base region 65 Base connection region 67 Polysilicon 69 Emitter region 71 Oxide layer 73 Polysilicon emitter spacer 75 Drain 79 P + base contact region

 ──────────────────────────────────────────────────続 き The continuation of the front page (72) Inventor Ke Wencheon No.2, Rokuro 2 R & D Center, Science Park, Hsinchu City, Taiwan (56) References JP-A-63-284854 (JP, A) JP-A-2-246148 (JP) JP-A-3-49256 (JP, A) JP-A-58-157157 (JP, A)

Claims (4)

(57) [Claims] 1. A bipolar transistor, an NMOS and a P
A method of manufacturing a BiCMOS device having a MOS transistor, comprising: (a) forming a first, a second, and a third buried region adjacent to each other by adding first and second conductivity type impurities to a substrate; Implanting; (b) depositing an epitaxial layer (37) over the entire substrate after forming the first, second and third buried regions; and (c) of the NMOS and PMOS transistor wells. One of which is a bipolar transistor well and the NMO
A bipolar transistor well, so as to be disposed between the S and the other of the PMOS transistor wells;
Implanting first and second conductivity type impurities into the epitaxial layer in regions where the first, second, and third buried regions are formed to form an NMOS transistor well and a PMOS transistor well; (D) growing a silicon dioxide layer (43) on the surface of the bipolar, NMOS and PMOS transistor wells; and (e) depositing a silicon nitride layer (45) on the silicon dioxide layer (43). (F) a plurality of first isolation regions on each junction of the bipolar, NMOS and PMOS transistor wells, and a second of the surface of the bipolar transistor well adjacent to one of the first isolation regions. Etching said silicon nitride layer (45) to expose said isolation region; and (g) said first and second silicon nitride layers (45). (H) etching the silicon nitride layer (45) to expose adjacent base oxide regions on the surface of the bipolar transistor well; (i) growing a field oxide layer (51) in the isolation region; Growing a base oxide layer (53) on the base oxide region to define the range of the emitter of the bipolar transistor; and (j) removing the silicon nitride layer (45) and the silicon dioxide layer (43). (K) forming a sacrificial oxide layer (55) on the bipolar, NMOS and PMOS transistor wells; and (l) the second isolation region (51) and the plurality of first
Forming a bipolar transistor deep collector contact (59) in a bipolar transistor well between adjacent ones of the isolation regions (51); (m) removing the sacrificial oxide layer (55); (N) growing a gate oxide layer (61) on the surface of the bipolar, NMOS and PMOS transistor wells; and (o) forming an intrinsic base region (63) between the base oxide layers (53) on the bipolar transistor well. Exposed,
Etching to reduce the thickness of opposing portions of the opposing base oxide layer (53); and (p) a base portion (6) between said base oxide layers (53).
5) and a base link portion (66) disposed below an opposing portion of the base oxide layer and connected to a portion of the base to form an intrinsic base of a bipolar transistor. (Q) depositing a polysilicon layer (67) on the gate oxide layer (61) and on the intrinsic base region (63); (r) the polysilicon layer Impurities are implanted into (67), allowing the impurities to diffuse from the polysilicon layer (67) to form an emitter region (69) on the surface of the base that is part of the intrinsic base (63). Driving the impurities in the polysilicon layer (67) by high-temperature heat treatment. 2. The method of manufacturing a BiCMOS device according to claim 1, further comprising, after the step (r), (s) forming a gate electrode of an NMOS and a PMOS transistor and a polysilicon emitter (69) of a bipolar transistor. The polysilicon layer (6
And (t) N-type LDD ion implantation in the NMOS transistor well, P-type LDD ion implantation in the PMOS transistor well, and the N-type LDD and P-type implantation in the bipolar transistor well. And (u) depositing an oxide layer (71) on the bipolar, NMOS and PMOS transistor wells after the N-type LDD and P-type LDD ion implantation. (V) anisotropically etching the oxide layer (71) to form LDD sidewall spacers (73) on each sidewall of the gate electrode and the polysilicon emitter; and (w) the source of the NMOS transistor. And the drain (75), the source and the drain (77) of the PMOS transistor, and The base region around the bipolar transistor of the base link portion of the intrinsic base (7
Implanting first and second conductivity type impurities into said bipolar, NMOS and PMOS transistor wells to form 9). 3. The method of manufacturing a BiCMOS device according to claim 1, further comprising: (f1) a field ion on a surface of one of said NMOS and PMOS transistor wells between steps (f) and (g). Injection area (4
7) a process for etching the silicon nitride layer (45) to expose the silicon nitride layer (45); and (f2) a process for forming a boron implanted region (49) in the field ion implanted region (47). Method. 4. The method of manufacturing a BiCMOS device according to claim 1, further comprising, during steps (k) and (l), adjusting the threshold voltages of NMOS and PMOS transistors to be formed. Implanting an impurity (57) into the oxide layer (55).