JPH06224375A - Preparing bipolar transistor for bicmos - Google Patents

Abstract

PURPOSE: To reduce the base electric resistance of a bipolar transistor (BJT), and to improve the current gain by forming a slim base connecting region, and connecting the base of the BJT and a base contact region. CONSTITUTION: A thin base oxide layer in one layer is grown before ion is injected into a base connecting region 65. Therefore, at the time of base ion injection, one part of ions is allowed to pass through the base oxide layer, the slim base connecting area 65 is formed at the lower part, and a bipolar transistor (BJT) base is connected with a base contact region 79. Also, the ion injection into the base contact region 79 is operated in the final period of a manufacturing step, so that the high concentration doping of the base contact region 79 can be prevented from diffusing and intruding on the base region in a step accompanied by high temperature in the beginning period of the manufacturing step. That is, the base contact region 79 is allowed to diffuse horizontally and mutually connected with the base connecting region 65 so that the electric resistance of the base can be sharply reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor, and more particularly to a BiCMOS (BismuthCompli).
mentally metalloid semico
The present invention relates to a method for manufacturing a high performance bipolar transistor used for a high frequency bipolar transistor.

[0002]

2. Description of the Related Art Bipolar transistors (BJTs) are widely used in BiCMOS, but there are two types that are most commonly used. The first type BJT is a base oxide region (Base). oxi
The emitter area is determined by de), and the structure of a bipolar transistor which is often used in this type of BiCMOS has a base area 12 and a base tangent area 13 which are the base oxidation area 11 of the BJT1 as shown in FIG.
Are grown by implanting base-connecting boron ions that connect to the base. The base region 12 and the base tangential region 13 are indirectly connected by the base-connecting region 14 grown by implanting the base-connecting boron ions. Therefore, the electric resistance of the base is relatively large, and the base oxidation area 11
During the growth of boron, the diffusion of boron ions is enhanced, so that on the one hand the base junction surface becomes considerably deeper and the breakdown voltage BV _cbo between the base and collector junction surface decreases, and on the other hand the base _junction area 14 also. In addition, it diffuses and enters the base area 12, and the current gain of the BJT drops, which adversely affects the performance.

The structure of the second type of BJT is the conventional Bi
As shown in FIG. 14, which is a schematic view of the structure of a bipolar transistor used in CMOS, the BJT 2 separates the base area 22 and the base tangent area 23 by a side wall spacer 21. With this method, the distance between the base area 22 and the base tangential area 23 can be shortened to greatly reduce the electric resistance of the base and improve the performance of the BJT. Pretty B
Since it is close to the emitter-base connection surface of the JT, a high electric field is generated between the emitter and the base, and the breakdown voltage BV _ebo of the emitter-base connection surface is reduced, which easily causes problems such as leakage and reliability at the interface. It is conceivable to increase the thickness of the side wall spacing area 21 to reduce this effect, but this will have a severe effect on the characteristics of the MOS.

[0004]

The above-mentioned conventional BiCMO
In view of the problems in the method for manufacturing an S bipolar transistor, an object of the present invention is to provide a method for manufacturing a BiCMOS bipolar transistor that can reduce the base electric resistance of the bipolar transistor and improve the current gain thereof.

[0005]

In order to achieve the above object, the present invention provides a first step of implanting a single / twin buried layer on a base by an ion implantation method; the single / twin buried layer. A second step of growing an epitaxy layer on the top surface; a third step of making N-type wells and P-type wells by conventional methods; and, after growing a silica layer on the top surface, vapor phase silicic acid nitride. Precipitation, then using a photomask to etch away the silicon nitride in the field area portions, and again using the photomask to perform field ion implantation of boron in the field area of the P-type well. 4th step of growing a field oxide layer of the same; then, using the photomask once again, the partial silicon nitride acid is etched away, and then the base acid is added to the etched away portion. Fifth step of growing the layer to define the emitter area of the BJT; then etching away any remaining silicon nitride nitride and the underlying silica layer to grow a sacrificial oxide layer, Later, MOSF
Ion layer implantation at ET critical voltage and BJT
Sixth step of ion implanting the deep collector to reduce the series resistance of the BJT collector;
The sacrificial oxide layer is etched away, and a single oxide layer is grown to form the MOSFET gate oxide layer, and then the photomask is used to etch away the top oxide layer that will be the BJT base area. Boron ion is B
7th step of implanting as JT base ions; and then vapor-depositing a layer of polysilicon to form MOSFET gates and BJT emitters, followed by implanting polysilicon to dope the polysilicon with phosphorus / arsenic ions, Eighth step of further driving in at high temperature to diffuse over the base area of the silicon surface opening to form the emitter area; then, the polysilicon is etched away by a photomask, and the remaining polysilicon area is covered with MOSFET gate and After configuring the emitter of BJT, general MOS
Ninth step of ion-implanting N-LDD and P-LDD based on the FET manufacturing process, and coating a single oxide layer thereover; non-isotropic etching on the coating oxide layer. Forming an appropriate gap, and at this time, there is a gap area on the periphery of the polysilicon emitter of the BJT, and the tenth step of performing overetching to completely etch the gap area; and MOSFET. Source and drain ion implantation is performed, in which P + ions are also implanted outside the polysilicon emitter spacing to form a P + base tangential region; the eleventh step is followed by an oxide layer and a conventional method. The BPSG layer is coated to insulate and planarize, then contact holes are drilled and metal is implanted to form BJT and MOS.
After connecting and forming terminals of FET parts, another layer of protective film is added again to protect the metal wire, and finally some windows are opened in the protective film to make it useful as a tangent line when packaging the integrated circuit. The steps are sequentially performed.

The fourth step is then followed by "and after growing a silica layer on top of it, vapor-depositing silicon nitride, and then using a photomask, the silicon nitride in the field area portion. It is more preferable to etch away the acid and then once again use the photomask to perform field ion implantation of boron in the field area of the N-type well to grow one more field oxide layer. "

[0007]

As described above, according to the present invention, since a thin base oxide layer is first grown before implanting the ions in the base connecting region, the partial ions pass through the base oxide layer when implanting the base ions. Then, an elongated base connecting area can be formed thereunder to connect the BJT base and the base tangential area, and since the base tangential area is planted at the end of the manufacturing step, the high temperature in the early manufacturing step is involved. In the step, the heavy doping of the base tangential area does not diffuse into the base area.

The fourth step is then followed by "and after growing a silica layer on top of it, vapor-depositing silicon nitride, and then using a photomask to form silicon nitride in the field area. Etching away the elemental acid and again using the photomask to implant boron field ions in the field area of the N-type well to grow one more field oxide layer. "
Not only PN type BJT but also PNP type BJT manufacturing step.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a method for manufacturing a BiCMOS bipolar transistor according to the present invention will be described. In the present invention, the first type BJT manufacturing method described in the above-mentioned "Prior Art" is too complicated, and the base connecting area is too large. The electric resistance of the BJT is increased, and in the manufacturing process, the base connecting boron ions are diffused to the base region to reduce the current gain. Therefore, we have researched and developed the manufacturing method of the high performance bipolar transistor of the present invention because there is a problem of leakage and reliability in the connection surface. By forming a connecting area with the base tangential area and controlling the distance between the base tangential area and the emitter-base connection surface at the same time during the manufacturing process. Is to improve the current gain to prevent leakage of the connecting surface.

FIG. 1 shows the BiCMOS of the present invention.
FIG. 1 is a view showing steps for manufacturing a bipolar transistor for use in the manufacturing process, and each manufacturing step will be described in order with reference to the drawings; (1) First, as shown in FIG. N + buried layer (Buried Layer)
r) Implant 33 or both N + and P buried layers.

(2) Then, as shown in FIG. 2, the N-- epitaxy layer 37 or the P-- epitaxy layer (Epitaxy Layer) grows on the upper surface thereof.

(3) Further, as shown in FIG. 3, an N-type well (Well) 39 and a P-type well 41 are formed by a conventional method.

(4) Then, as shown in FIG. 4, after a silica layer (SiO ₂ ) 43 is grown on the upper surface, silicon nitride (Si ₃ N ₄ ) 45 is vapor-phase precipitated (CVD). ,
Next, using a photomask, the field area (Field
(Region) Silicic acid nitride 45 in the portion 47 is removed by etching, and again using a photomask, P
Field ion implantation 49 of boron is performed on the field area of the well 41 to form a single field oxide layer (FieldOxid).
e) Grow 51. This is a general LOCOS (Lo
cal oxidation on silicon)
It is the same as the working method of insulation technology.

(5) Subsequently, as shown in FIG. 5, the partial silicon nitride acid is removed by etching again using an optical mask, and then, the base oxide layer (Base oxide) 53 is formed on the removed portion by etching. To limit the emitter area of the BJT. The growth of this base oxide layer 53 is similar to that of the field oxide layer 51, the only difference being that field ion implantation is not performed.

(6) This step is as shown in FIG.
All the remaining silicic acid nitride and the underlying silica layer 43 are removed by etching to remove one sacrificial oxide layer (Sac
After growing the rough oxide 55),
MOSFET (Metaloxide semiconductor)
ductor field effect trans
istor) implanting an ion layer 57 of a critical voltage,
And BJT Deep Collector
ctor) forming an ion-implanted collector area 59 to reduce the series electrical resistance of the BJT collector.

(7) Next, as shown in FIG. 7, the sacrificial oxide layer 55 is removed by etching, and a single oxide layer 61 is formed.
To form an oxide layer for the MOSFET gate, and then the photomask is used to etch away the oxide layer on the upper surface of the BJT base area 63, and boron ions are implanted as the BJT base ion to form a P-type oxide layer. A base 65 and a base connecting area 66 are formed.

(8) Then, as shown in FIG. 8, a single layer of polysilicon (Poly Si) 67 is vapor-phase precipitated to form MO.
It is used as the gate of SFET and the emitter of BJT, and then phosphorus (P) or arsenic (As) ions are implanted to make polysilicon dope (Nope) N +, and further, high temperature drive-in (Drive in), The base area 65 of the opening is diffused to form an N + emitter area 69.

(9) As shown in FIG. 9, after the polysilicon 67 is removed by etching with a photomask to form a MOSFET gate and a BJT emitter in the remaining polysilicon area, a general MOSFET manufacturing process is performed. Ion-implantation of N-LDD (Light Doped Drain) and P-LDD was performed, and
The OS implants N-LDD ions, and the PMOS and BJT portions implant P-LDD ions, but N-LDD ion implantation may be performed completely (in the figure, the NMOS portion is manufactured. Since the process belongs to the prior art, only the BJT portion is shown), and subsequently, a single oxide layer 71 is coated thereon.

(10) As shown in FIG. 10, the coating oxide layer 71 is non-isotropically etched to form an LDD space (Spacer). At this time, the polysilicon gate of the MOSFET and the polysilicon of the BJT are formed. Since there is a gap area around the periphery of the silicon emitter and the gap area is completely etched, the overetching (Ove
Etching is performed to completely etch away the base oxide layer at the outer edge of the gap 73 of the polysilicon emitter 69.

(11) The next step is the MOS part and BJ
As shown in FIG. 11 including the T portion, this step is performed by first performing N +
After exposing using an optical mask, the NMOS source (Sou
rce) and Drain 75 are N + ion implanted, and then exposed using a P + photomask, followed by P + ion implantation of the PMOS source and drain 77. At this time, the polysilicon emitter spacing 7
3 P + ions were also hit outside, and P + base tangent area 7
9 is formed.

(12) Then, the oxide layer and BPSG (Boron Phosphorus Sil) are formed by a conventional method.
After insulating and flattening by coating an icon glass layer, a contact hole is formed by implanting a metal to connect the terminals of the BJT and MOSFET components, and then a further protective film (Passivation) is formed.
Is added to protect the metal wire, and finally several windows are opened in the protective film to serve as a tangent wire when packaging the integrated circuit. Then, as shown in FIG. 12, when heat treatment is added in these latter steps, the BJT
Since the base tangential area 79 on the side of the emitter area is diffused laterally and connected to the base connecting area 66,
The electric resistance of the base is greatly reduced to improve the performance of BJT. The above is the NPN type BJT manufacturing step,
In the case of PNP type BJT, the field ion implantation of boron in the field region of the P type well is simply replaced with the N type well, the base connection region is implanted with phosphorus or arsenic ions, and the polysilicon doping is performed. It is only necessary to replace it with elementary ion implantation, and since it belongs to an extremely simple technique in the manufacturing steps, it is not talked about here.

[0023]

The present invention constructed as described above has the following features.
The following effects are obtained in the process of manufacturing a bipolar transistor for iCMOS and its product: In addition, since it is not necessary to plant another base connecting area and the base area and the base tangential area are directly connected, the electric resistance of the base can be reduced.

2. Since the base tangential area and the connection surface depth of the base area are shallow, the vertical standard size can be reduced very easily.

3. Since the distance between the tangential area of the base and the emitter-base connecting surface is relatively long, the leakage does not easily occur and the reliability becomes high.

4. Since the base tangential area does not diffuse into the base area, no reduction in current gain occurs.

5. Therefore, the current gain of the manufactured BJT is improved, and the performance of the bipolar transistor used in BiCMOS is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a step of manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 2 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 3 is a diagram showing a manufacturing step of a BiCMOS bipolar transistor of the present invention.

FIG. 4 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 5 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 6 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 7 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 8 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 9 is a diagram showing the manufacturing steps of the BiCMOS bipolar transistor of the present invention.

FIG. 10 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 11 is a diagram showing the manufacturing steps of the BiCMOS bipolar transistor of the present invention.

FIG. 12 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 13 is a diagram showing a structural example of a conventional BiCMOS bipolar transistor.

FIG. 14 is a diagram showing another structural example of the conventional BiCMOS bipolar transistor.

[Explanation of symbols]

 31 Base 33 Single Buried Layer 35 Twin Buried Layer 37 Epitaxy Layer 39 N-type Well 41 P-type Well 43 Silica Layer 45 Silicon Nitride Acid 47 Field Area 49 Field Oxide Layer 51 Field Oxide Layer 53 Base Oxide Layer 55 Sacrificial Oxide Layer 57 Ion layer 61 Oxide layer 63 BJT base area 65 Base connecting area 67 Polysilicon 69 Emitter area 71 Oxide layer 73 Polysilicon emitter spacing 75 Drain 79 P + base tangent area

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[Procedure amendment]

[Submission date] January 20, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title: BiCMOS bipolar transistor manufacturing method

[Claims]

DETAILED DESCRIPTION OF THE INVENTION 1

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor, and more particularly to a BiCMOS (BismuthCompli).
mentally metalloid semico
The present invention relates to a method for manufacturing a high performance bipolar transistor used for a high frequency bipolar transistor.

[0002]

2. Description of the Related Art By the way, various kinds of bipolar transistors (BJTs) are used in BiCMOS, but there are two types that are most commonly used. The first type BJT is a base oxide region (Base). oxi
The emitter region is determined by de), and the structure of the bipolar transistor which is often used in this type of BiCMOS has the base region 12 and the base contact region 13 of the base oxide region 11 of the BJT1 as shown in FIG. The base region 12 and the base contact region 13 are indirectly grown by implanting and growing the base connecting boron ions that are connected to each other. Therefore, when the electric resistance of the base is relatively large and the diffusion of boron ions progresses while the base oxide region 11 is growing, the base connecting surface becomes considerably deep and the base and collector are connected. The breakdown voltage BV _{cbo of the} surface decreases, and on the other hand, the base connecting region 14 also diffuses and enters the base region 12. However, the current gain of the BJT is lowered and the performance is adversely affected.

The structure of the second type of BJT is the conventional Bi
As shown in FIG. 14 which is a schematic view of a bipolar transistor structure used in CMOS, the BJT 2 separates a base region 22 and a base contact region 23 by a side wall spacer 21. Although the distance between the base region 22 and the base contact region 23 can be shortened by this, the electrical resistance of the base can be greatly reduced and the performance of the BJT can be improved, but the implantation of high-concentration boron ions on the base contact region 23 considerably increases the emitter of the BJT. Since it is close to the base connection surface, a high electric field is generated between the emitter and the substrate, and the breakdown lightning voltage BV _ebo of the emitter base connection surface is reduced,
Problems such as leakage and reliability may easily occur at the interface, and, of course, it is conceivable to increase the thickness of the sidewall spacers 21 to reduce this effect, but this will greatly affect the characteristics of the MOS. .

[0004]

The above-mentioned conventional BiCMO
In view of the problems in the method for manufacturing an S bipolar transistor, an object of the present invention is to provide a method for manufacturing a BiCMOS bipolar transistor that can reduce the base electric resistance of the bipolar transistor and improve the current gain thereof.

[0005]

In order to achieve the above object, the present invention provides a first step of forming a single / double buried layer on a substrate by an ion implantation method; a top surface of the single / double buried layer. A second step of growing an epitaxy layer on the substrate; a third step of forming an N-type well and a P-type well by a conventional method; and, after growing an oxide film on the upper surface thereof, vapor-depositing silicon nitride, Next, the photomask is used to etch away the silicon nitride in the field region, and the photomask is used again to perform field ion implantation of boron into the field region of the P-type well to form a field oxide layer. Fourth to grow
Next, the silicon nitride is partially etched away again using the photomask, and then a base oxide layer is grown on the etched away portion to form BJ.
Fifth step of defining the emitter region of T; then all remaining silicon nitride and underlying oxide is etched away to form a layer of sacrificial oxide (Sacrifi).
cal oxide), and then MOSFE
Sixth step of performing ion implantation of T critical voltage and ion implantation of BJT deep collector to reduce series electric resistance of BJT collector; and etching away the sacrificial oxide layer and further oxidation. The layer is grown to form an oxide film for the MOSFET gate, and then the upper oxide layer to be the BJT base region is removed by etching using a photomask, and boron ions are added to the BJT base region on the BJT base region.
Seventh step of implanting as T-base ions; and then vapor-depositing a layer of polysilicon to form MOSFET gates and BJT emitters, followed by implanting polysilicon and doping the polysilicon with phosphorus / arsenic ions. Eighth step of further driving in at high temperature to diffuse above the base region of the silicon surface opening to form an emitter region; Next, the polysilicon is etched away by a photomask, and the MOSFET is formed in the remaining polysilicon region.
After configuring the gate and the emitter of the BJT, general MO
N-LDD and P-LDD based on SFET-made
9th step of performing ion implantation of BJT and coating a single oxide layer thereabove; anisotropic etching is performed on the coated oxide layer to form a suitable spacer. Since there is a spacer region all around the silicon emitter, the tenth step of overetching is performed to completely etch the spacer region; and ion implantation is performed on the source and drain of the MOSFET. Eleventh step of implanting P + ions also outside the polysilicon emitter spacers to form P + base contact regions; followed by conventional methods for coating and insulating and planarizing the oxide and BPSG layers; After depositing metal through the contact holes and connecting and forming the terminals of BJT and MOSFET parts, Configured to perform the order; added a protective film to protect the metal lines, and finally opening the several windows in the protective film, twelfth step of causing aid in connection when the integrated circuit package.

The fourth step is followed by "And, after growing a silica layer on the upper surface, vapor-depositing silicon nitride and then etching the silicon nitride in the field region portion using a photomask. Removed,
Further, it is more preferable to perform the field ion implantation of boron into the field region of the N-type well again using the photomask to grow a further field oxide layer. "

[0007]

As described above, according to the present invention, since a thinner base oxide layer is first grown before implanting ions into the base connecting region, some of the ions are oxidized during base ion implantation. Through the layer, an elongated base connecting region can be formed thereunder to connect the BJT base and the base contact region, and the base contact region is ion-implanted at the end of the manufacturing step. In the step involving the high temperature in the first half of the step, the heavily doped base contact region does not diffuse and penetrate into the base region.

Then, the fourth step is followed by "And, after growing a silica layer on the upper surface, vapor-depositing silicon nitride and then etching the silicon nitride in the field region portion using a photomask. Removed,
Then, by using a photomask again, field ion implantation of boron is performed in the field region of the N-type well to grow a further field oxide layer. "Not only the NPN-type BJT but also the PNP-type BJT
It also becomes a manufacturing step.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a BiCMOS bipolar transistor manufacturing method of the present invention will be described. In the present invention, the first type BJT manufacturing method described in the above-mentioned "Prior Art" is too complicated and the base connection is performed. The electric resistance of the region increases, and in the manufacturing process, the base coupling boron ion diffuses to the base region to reduce the current gain, and in the second type of BJT manufacturing method, at the emitter-base connection surface. Since a high electric field occurs and there is a problem of leakage and reliability in the connection surface, we have researched and developed the manufacturing method of the high performance bipolar transistor of the present invention, directly implanting substrate ions and utilizing it for substrate connection, A connecting region is formed between the base region and the base contact region, and at the same time, during the manufacturing process, between the base contact region and the emitter-base connecting surface. By controlling is to improve the current gain to prevent leakage of the connecting surface.

FIG. 1 is a view showing the steps of manufacturing the BiCMOS bipolar transistor of the present invention, and each manufacturing step will be described in order with reference to the drawings; (1) As shown in FIG. First, an N + buried layer (Buried Layer) is formed on the P-type substrate 31 by an ion implantation method.
er) 33 or both buried layers of N + and P buried layers are formed.

(2) Next, as shown in FIG. 2, an N-- epitaxy layer 37 or a P-- epitaxy layer (Epitaxy Layer) is grown on the upper surface thereof.

(3) Further, as shown in FIG. 3, an N-type well (Well) 39 and a P-type well 41 are formed based on a conventional method.

(4) Then, as shown in FIG. 4, an oxide film (SiO ₂ ) 43 is grown on the upper surface thereof, and then silicon nitride (Si ₃ N ₄ ) 45 is vapor-phase deposited (CVD). The field area (Field
(Region) 47, the silicon nitride 45 in the region 47 is removed by etching, and field ion implantation (Field Implant) 49 of boron is performed again in the field region of the P-type well 41 by using a photomask to form a further field oxide layer ( Field Ox
ide) 51 is grown. This is a general LOCOS
(Local oxidation On silic
on) It is the same as the working method of insulation technology.

(5) Then, as shown in FIG. 5, the silicon nitride is partially etched away again using a photomask, and then the base oxide layer (Base oxide) 53 is formed in the etched away portion. To limit the emitter area of the BJT. This base oxide layer 5
The growth of No. 3 is similar to that of the field oxide layer 51, and the only difference is that no field ion implantation is performed.

(6) In this step, as shown in FIG. 6, all the remaining silicon nitride and the oxide film layer 43 thereunder are removed by etching, and one sacrificial oxide layer (S
A crystalline oxide (55) is grown, and after that, a MOSFET (Metal oxide semi) is grown.
conductor field effect tr
and the BJT deep collector (Deep co).
The collector region 59 is formed by ion implantation to form a collector, and the series electric resistance of the BJT collector is reduced.

(7) Next, as shown in FIG. 7, the sacrificial oxide layer 55 is removed by etching, and one oxide layer 6 is formed.
1 is grown as an oxide layer of the MOSFET gate, then the oxide layer on the upper surface of the region to be the BJT base region 63 is etched away by a photomask, and further boron ions are implanted as BJT base ions. ,
A P-type base 65 and a base connecting region 66 are formed.

(8) Then, as shown in FIG. 8, a single layer of polysilicon (Poly Si) 67 is vapor-deposited to form M.
It is used as the gate of the OSFET and the emitter of the BJT, and then phosphorus (P) or arsenic (As) ions are implanted, the doping (Dope) of polysilicon is changed to N +, and high temperature drive-in (Drive in) is performed. The upper surface of the base region 65 of the surface opening diffuses to form an N + emitter region 69.

(9) As shown in FIG. 9, the polysilicon 67 is removed by etching with a photomask to form a MOSFET gate and a BJT emitter 69 in the remaining polysilicon region. N-LDD (Light Doped D)
lane) and P-LDD are ion-implanted, of which NMOS is N-LDD ion-implanted, and
Although the P-LDD ion implantation is performed in the MOS and BJT portions, it is also possible to completely implant the N-LDD ion implantation. (In the figure, since the manufacturing process of the NMOS portion belongs to the conventional technique, only the BJT portion is formed. Is displayed), and then
A single oxide layer 71 is coated thereover.

(10) As shown in FIG. 10, LDD is performed by anisotropically etching the covering oxide layer 71.
A side wall spacer (Spacer) 73 is formed, and at this time,
There is a spacer region at the peripheries of the polysilicon gate of the MOSFET and the polysilicon emitter of the BJT, and since the spacer region is completely etched, the overetching is always performed to make the spacer 73 of the polysilicon emitter 69. Completely etch away the base oxide layer on the outer edge of the.

(11) In the subsequent step, as shown in FIG. 11 including the MOS portion and the BJT portion, this step is the same as in the general MOSFET manufacturing process. First, the N + photomask (n-select mask) is used.
Source of NMOS transistor (Source
e) N + ions are implanted into the drain and drain regions to form the MOS source / drain 75. After that, P + photomask (p-select mask)
Using k), P + ions are implanted into the source and drain regions of the PMOS transistor to form the MOS source / drain 77. At this time, P + ions are also implanted outside the polysilicon emitter spacer 73 to form a P + base contact region 79.

(12) Then, the oxide layer and BPSG (Boron Phosphorus S) are formed by a conventional method.
After coating and isolating and planarizing the ilicon glass layer, and then depositing metal by forming a contact hole (Contact) to connect and form the terminals of the BJT and MOSFET components, another passivation layer (Passivati) is formed.
ON) is added to protect the metal wire, and finally several windows are opened in the protective film to help connection during packaging of the integrated circuit. Then, as shown in FIG. 12, when heat treatment is added in these latter steps, the BJ
Since the base contact region 79 on the side surface of the T emitter region is laterally diffused and connected to the base connecting region 66, the electric resistance of the base is significantly reduced and the BJT performance is improved. The above is the NPN type BJT manufacturing step. However, in the case of the PNP type BJT, the field ion implantation of boron in the field region of the P type well is replaced by the N type well, and the base connection region is made of phosphorus or Implantation with arsenic ions and polysilicon doping may be replaced with boron ion implantation, which belongs to an extremely simple technique in the manufacturing steps, and therefore will not be talked about here.

[0023]

The present invention constructed as described above has the following features.
The following effects are obtained in the process of manufacturing a bipolar transistor for iCMOS and its product: In addition, since it is not necessary to inject another base connecting region and the base region and the base contact region are directly connected, the electric resistance of the base can be reduced.

2. Since the connection surface depth of the base contact region and the base region is shallow, the standard size in the vertical direction can be reduced very easily.

3. Base contact area and emitter
Since the distance to the base connection surface is relatively long, the leakage current does not easily occur and the reliability is high.

4. Since the base contact region does not diffuse and enter the base region, the current gain is not reduced.

5. Therefore, the current gain of the manufactured BJT is improved, and the performance of the bipolar transistor used in BiCMOS is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a step of manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 2 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 3 is a diagram showing a manufacturing step of a BiCMOS bipolar transistor of the present invention.

FIG. 4 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 5 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 6 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 7 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 8 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 9 is a diagram showing the manufacturing steps of the BiCMOS bipolar transistor of the present invention.

FIG. 10 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 11 is a diagram showing the manufacturing steps of the BiCMOS bipolar transistor of the present invention.

FIG. 12 is a diagram showing steps for manufacturing a BiCMOS bipolar transistor of the present invention.

FIG. 13 is a diagram showing a structural example of a conventional BiCMOS bipolar transistor.

FIG. 14 is a diagram showing another structural example of the conventional BiCMOS bipolar transistor.

[Description of Reference Signs] 31 Base 33 Single Buried Layer 35 Twin Buried Layer 37 Epitaxy Layer 39 N-type Well 41 P-type Well 43 Silicon Dioxide 45 Silicon Nitride 47 Field Region 49 Field Oxide Layer 51 Field Oxide Layer 53 Base Oxide Layer 55 Sacrificial oxide layer 57 Ion layer 61 Oxide layer 63 BJT base region 65 Base connecting region 67 Polysilicon 69 Emitter region 71 Oxide layer 73 Polysilicon emitter spacer 75 Drain 79 P + base contact region

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FIG. 11

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 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Zhang Wen, No. 2 Rukuji, Hsinchu City Science Park, Taiwan (72) Inventor, Kebun River, No. 2 Rukuji, Hsinchu City Science Park, Taiwan

Claims (2)

[Claims] 1. A first step of implanting a single / twin buried layer (33, 35) on a base (31) by an ion implantation method; on the upper surface of the single / twin buried layer (33, 35). A second step of growing the epitaxy layer (37); a third step of making N-type well (39) and P-type well (41) by conventional methods; and a silica layer (43) on top of it.
And then vapor-depositing the silicon nitride (45), and then using a photomask to etch away the silicon nitride (45) in the field area (47).
And again using the optical mask, P-type well (41)
A field ion implantation of boron (49) is performed on the field area of the layer to form a single field oxide layer (51).
A fourth step of growing the silicon oxide; then, using the photomask again, the partial silicon nitride acid is etched away, and then the base oxide layer (53) is formed on the etched away portion.
Fifth step to grow BJT to define the emitter area of the BJT; then etch away any remaining silicon nitride nitride and underlying silica layer (43) to form a sacrificial oxide layer (55). And then MOSFET
Ionic layer (57) implantation at critical voltage, and B
Sixth step of implanting ions in the JT deep collector to reduce the series electrical resistance of the BJT collector; and further, etching away the sacrificial oxide layer (55) and growing one oxide layer (61). A seventh step of etching away the oxide layer on the upper surface which is to be the oxide layer of the MOSFET gate and then to the BJT base area (63) by means of a photomask, on which boron ions are implanted as BJT base ions; Then, a layer of polysilicon (67) is vapor-deposited to form a MOSFET gate and B
As an emitter of the JT, the polysilicon is subsequently doped with phosphorous / arsenic ions by implanting ions and then driven in at high temperature for the base area of the silicon surface opening (65).
Eighth diffused upward to form emitter area (69)
Next, after the polysilicon (67) is etched away by a photomask to form the MOSFET gate and the BJT emitter in the remaining polysilicon area, the N-LDD is formed according to a general MOSFET manufacturing process.
And a ninth step of ion-implanting P-LDD and overlying a layer of oxide (71) thereon; Forming a gap, and at this time, there is a gap area on the periphery of the polysilicon emitter of the BJT as well, and a tenth step of performing overetching to completely etch the gap area; and MOSF.
Ion implantation of the source and drain (75) of the ET is performed, in which P + ions are also implanted outside the polysilicon emitter spacing (73) and the P + base tangent area (79).
Eleventh step of forming BJT and MOSFET components by subsequently coating and insulating and planarizing the oxide and BPSG layers by conventional methods and then implanting metal through the contact holes. After connecting and forming a layer, a layer of protection film is added again to protect the metal wire, and finally several windows are opened in the protection film to serve as tangent lines for packaging the integrated circuit. BiCM performed in order
Bipolar transistor manufacturing method for OS. 2. The fourth step is described as follows: "And after growing a silica layer (43) on top of it, vapor deposition of silicon nitride (45), then using a photomask. Silicon nitride (45) in the field area (47)
, And again using a photomask to perform field ion implantation of boron (49) in the field area of the N-type well (39) to grow a further field oxide layer (51). " The method for manufacturing a BiCMOS bipolar transistor according to claim 1, wherein