CN112071757A - Method for manufacturing silicon-germanium heterojunction bipolar transistor based on BiCMOS (bipolar complementary metal oxide semiconductor) process - Google Patents
Method for manufacturing silicon-germanium heterojunction bipolar transistor based on BiCMOS (bipolar complementary metal oxide semiconductor) process Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
Abstract
The invention discloses a method for manufacturing a silicon-germanium heterojunction bipolar transistor based on a BiCMOS (bipolar complementary metal oxide semiconductor) process, which comprises the following steps of: 1) growing a LOCOS isolation field oxide layer to form an optimal silicon-based substrate; 2) forming a LOCOS field oxide layer between an emitter active region and a collector active region of the SiGe HBT transistor and a LOCOS oxide layer for isolation between devices; 3) forming a SiGe HBT transistor base region window on the surface of the optimal silicon-based substrate; 4) forming a SiGe HBT transistor base region epitaxial material layer on the surface of the optimal silicon-based substrate; 5) forming a SiGe HBT transistor emitter region window on the surface of the optimal silicon-based substrate; 6) forming a SiGe HBT transistor polycrystalline emitter junction fine structure and an outer base region on the surface of the optimal silicon-based substrate; 7) and depositing a dielectric layer on the surface of the optimal silicon-based substrate to complete metal interconnection, and forming the SiGe HBT transistor. The invention adopts a local twice silicon nitride hard mask oxidation process method, reduces the high step of the outer base region of the HBT transistor, thereby reducing the influence of the high step reflection of the outer base region on the emitter junction polycrystalline lithography.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method for manufacturing a silicon-germanium heterojunction bipolar transistor based on a BiCMOS (bipolar complementary metal oxide semiconductor) process.
Background
The silicon-based bipolar transistor device needs to take current amplification factor and breakdown into consideration, and the base region cannot be heavily doped, so that the carrier transit time is long, the frequency is low, and the requirements of high-frequency circuits such as a radio frequency communication system and the like cannot be met. Ge is introduced into a base silicon material of the bipolar transistor to form a SiGe alloy semiconductor so as to adjust an energy band structure of the SiGe alloy semiconductor, improve the injection efficiency of the emitter structure and increase the current amplification factor of the device; and secondly, the high doping of the SiGe base region is utilized to reduce the resistance of the base region and improve the characteristic frequency of the device. In addition, the process for manufacturing a SiGe HBT (silicon germanium heterojunction bipolar transistor) device is easy to realize compatibility with the process for manufacturing a silicon-based CMOS device, so that the SiGeBiCMOS process technology is one of the preferred process technologies for manufacturing the ultrahigh frequency IC chip and is widely applied to the development and processing of the radio frequency front end component of the communication system.
The SiGe HBT heterojunction transistor is a core device of the SiGeBiCMOS process technology, the structure of a polycrystalline emitter of the device is complex, the characteristic dimension is minimum, meanwhile, an outer base region high-step structure is formed by field oxygen isolation of a traditional outer base region LOCOS, the high step formed in front of an HBT outer base region and an emitter active region exists in the side wall of the high step during emitter polycrystalline photoetching, so that the formation of a polycrystalline emitting fine structure is influenced, part of patterns are distorted, HBT heterojunction transistor patterns distributed at different positions on a wafer are not distorted uniformly, and the repeatability and uniformity of HBT heterojunction transistor parameters of the core device of the SiGeBiCMOS process technology are seriously influenced.
In the traditional SiGeBiCMOS process technology, a LOCOS field oxygen isolation technology is adopted for the separation between HBT bipolar collector transistors and CMOS type transistor devices, an emitter junction of the HBT device is of a longitudinal structure, a base region and a collector region are of a transverse structure, the structure isolation shares the LOCOS field oxygen isolation technology, and the high step of an outer base region of the HBT device is caused. The formation of such high steps brings about numerous drawbacks and concerns in the subsequent deep sub-micron lithography process.
Disclosure of Invention
The invention aims to provide a method for manufacturing a silicon-germanium heterojunction bipolar transistor based on a BiCMOS (bipolar complementary metal oxide semiconductor) process, which comprises the following steps of:
1) and selecting a silicon-based substrate.
2) And growing a LOCOS isolation field oxide layer between an emitter active region and a collector active region of the SiGe HBT by using a silicon nitride hard mask method, and performing wet etching on the LOCOS isolation field oxide layer to form the optimal silicon-based substrate.
The steps for forming the optimal silicon-based substrate are as follows:
2.1) depositing a thin oxide layer I and a silicon nitride layer I on the silicon-based substrate in sequence.
2.2) determining an isolation pattern I between an emitter and a collector of the SiGe HBT transistor and manufacturing a photoetching plate.
And 2.3) carrying out photoetching exposure on the silicon nitride layer I according to the pattern of the photomask, and etching the silicon nitride layer I to obtain an isolation region I between the emitter and the collector.
2.4) growing a LOCOS oxide layer I in the isolation region between the emitter and the collector. The thickness of the LOCOS oxide layer I is recorded as h1, and the thickness of the LOCOS oxide layer II is recorded as h 2; wherein h1 ═ 0.7h2, 1.3h2] > 0; h2> 0.
And 2.5) stripping the silicon nitride layer I by a wet method, and corroding the oxide layer I by the wet method to form the optimal silicon-based substrate.
3) And forming a LOCOS field oxide layer between an emitter active region and a collector active region of the SiGe HBT transistor and a LOCOS oxide layer for isolation between devices by using a secondary silicon nitride hard mask method.
The device comprises a SiGe HBT transistor, an NMOS device and a PMOS device;
the steps of forming the LOCOS field oxide layer between the emitter active region and the collector active region of the SiGe HBT transistor and the LOCOS oxide layer for isolation between devices are as follows:
3.1) depositing a thin oxide layer II and a silicon nitride layer II on the optimal silicon-based substrate.
And 3.2) determining an isolation pattern II and an inter-device isolation pattern III between an emitter active region and a collector active region of the SiGe HBT, and manufacturing a photoetching plate.
The determinant of the isolation pattern II between the emitter active region and the collector active region of the SiGe HBT transistor comprises the isolation pattern I between the emitter and the collector of the SiGe HBT transistor.
And 3.3) carrying out photoetching exposure on the silicon nitride layer II according to the pattern of the photoetching plate, and etching the silicon nitride layer II to obtain an isolation region II between the active region of the emitting electrode and the active region of the collecting electrode and an isolation region III between devices.
3.4) growing a LOCOS oxide layer II in the isolation region II between the emitter active region and the collector active region and the inter-device isolation region III.
And 3.5) stripping the silicon nitride layer II by a wet method, and corroding the oxide layer II by the wet method to form a low-step outer base region of the SiGe HBT transistor, active regions of other devices and field regions of other devices.
Including active and passive devices other than SiGe HBT transistors.
4) And forming a base region window of the SiGe HBT transistor on the surface of the optimal silicon-based substrate.
The steps of forming the base region window of the SiGe HBT transistor are as follows:
4.1) depositing a silicon oxide layer III and an amorphous silicon layer I on the surfaces of the active area of the SiGe HBT transistor and the LOCOS oxide layer II in sequence.
And 4.2) sequentially etching the amorphous silicon layer I and the silicon oxide layer III to form a base region window.
5) And forming a SiGe HBT transistor base region epitaxial material layer on the surface of the optimal silicon-based substrate.
The steps of forming the epitaxial material layer of the base region of the SiGe HBT transistor are as follows:
and 5.1) cleaning the optimal silicon-based substrate surface before deposition.
And 5.2) after the cleaning is finished, growing a SiGe epitaxial material layer on the optimal silicon-based substrate surface by utilizing rapid thermal treatment chemical vapor deposition. The SiGe epitaxial material layer comprises a silicon buffer layer, a SiGe layer and a silicon cap layer. The SiGe epitaxial material layer comprises a germanium concentration fast rising region, a platform region and a gradual reduction region.
6) And forming an emitter region window of the SiGe HBT transistor on the surface of the optimal silicon-based substrate.
The steps of forming the emitter window of the SiGe HBT transistor are as follows:
6.1) depositing a silicon oxide layer IV, an amorphous silicon layer II and an antireflection material layer on the surface of the SiGe epitaxial material layer in sequence.
6.2) etching the anti-reflection material layer, the amorphous silicon layer II and the silicon oxide layer IV in sequence until the silicon cap layer is exposed to form an emitting area window.
7) And forming a polycrystalline emitter junction fine structure and an outer base region of the SiGe HBT transistor on the surface of the optimal silicon-based substrate.
The steps of forming the fine structure of the polycrystalline emitter junction and the outer base region of the SiGe HBT transistor are as follows:
7.1) filling the emitter region window with polysilicon and impurity doping to form a polysilicon layer III serving as an emitter.
7.2) spin-coating an anti-reflection coating and a photoresist on the surface of the polycrystalline silicon layer III, and forming a polycrystalline emission fine structure by dry etching.
7.3) forming the SiGe HBT transistor outer base region by utilizing dry etching and tape glue injection.
7.4) carrying out impurity activation of the emitter region and the base region by utilizing rapid thermal annealing.
8) And depositing a dielectric layer on the surface of the optimal silicon-based substrate to complete the interconnection of metal and form a complete SiGe HBT transistor.
The steps for forming a complete SiGe HBT transistor are as follows:
8.1) formation of Ti/Co salicide.
And 8.2) depositing a dielectric layer on the surface of the optimal silicon-based substrate.
8.3) completing the photoetching and etching of the contact hole to form a contact hole tungsten plug structure.
8.4) completing the deposition, photoetching and etching of the metal electrode.
And 8.5) arranging a metal connecting wire to form a metal interconnection layer, thereby finishing the CMOS processing technology and obtaining the complete SiGe HBT transistor.
The invention has the advantages that the invention adds one time of photoetching to the LOCOS field oxide layer between the emitter and the collector of the SiGe HBT transistor before the process step of forming the emitter and the collector of the SiGe HBT transistor and the LOCOS isolation field oxide layer at the periphery of the device, and adopts a process method of growing the LOCOS oxide layer by using a local twice silicon nitride hard mask method to isolate the emitter and the collector of the SiGe HBT transistor, thereby reducing the high step of the outer base region of the HBT transistor, further reducing the influence of the high step reflection of the outer base region on the emitter junction polycrystalline photoetching, improving the formation of the fine structure of the SiGe HBT polycrystalline emitter, greatly improving the structural integrity of the SiGe HBT device, improving the repeatability and uniformity of key parameters of the device and greatly improving the manufacturing yield of the transistor.
Drawings
FIG. 1(a) is a flow chart of a conventional manufacturing method;
fig. 1(b) is a flow of a method for manufacturing a silicon germanium heterojunction bipolar transistor based on a BiCMOS process according to the present invention;
FIG. 2 is a process I for forming an optimized silicon-based substrate in the fabrication flow of the present invention;
FIG. 3 is a process II for forming an optimized silicon-based substrate in the fabrication flow of the present invention;
FIG. 4 is a process III for forming a silicon-based substrate optimized in the fabrication flow of the present invention;
FIG. 5 is a process IV for forming a silicon-based substrate optimized in the fabrication flow of the present invention;
FIG. 6 is a process V for forming a silicon-based substrate optimized in the fabrication flow of the present invention;
FIG. 7 is a schematic diagram of a device after depositing a thin oxide layer II and a silicon nitride layer II on an optimal silicon-based substrate in the manufacturing process of the present invention;
FIG. 8 is a schematic diagram of a device after deposition of a thin oxide layer II and etching of a silicon nitride layer II on an optimal silicon-based substrate in a manufacturing process of the present invention;
fig. 9 is a schematic view of a device after a LOCOS oxide layer II is grown in an isolation region II between an emitter active region and a collector active region and an inter-device isolation region III in a manufacturing process of the present invention;
fig. 10 is a schematic diagram of the completed low-step extrinsic base region, active region of other devices, and field region of a SiGe HBT transistor in accordance with the method of the present invention;
FIG. 11 is a schematic cross-sectional view illustrating the completion of window etching of the base region of a SiGe HBT transistor in the method of the present invention;
FIG. 12 is a schematic cross-sectional view illustrating the completion of SiGe HBT transistor base region SiGe epitaxial material growth in accordance with the present invention;
FIG. 13 is a schematic cross-sectional view illustrating the completion of window etching of the emitter region of a SiGe HBT transistor in accordance with the method of the present invention;
FIG. 14 is a schematic cross-sectional view of a device prior to emitter poly deposition and emitter poly lithography for a SiGe HBT transistor completed in accordance with the method of the present invention;
FIG. 15 is a schematic cross-sectional view of a device having completed an etching of the emitter of a SiGe HBT transistor in accordance with the method of the present invention;
FIG. 16 is a schematic cross-sectional view of a device having completed the outer base region etching and implantation of a SiGe HBT transistor in accordance with the method of the present invention;
figure 17 is a schematic cross-sectional view of a completed SiGe HBT transistor formed by deposition of a dielectric layer and metal interconnection in accordance with the method of the present invention;
in the figure, an optimal silicon-based substrate 100, a thin oxide layer I101, a silicon nitride layer I102, a LOCOS oxide layer I103, a thin oxide layer II104, a silicon nitride layer II105, a LOCOS oxide layer II106, a silicon oxide layer III107, an amorphous silicon layer I108, a base region epitaxial material layer 109, a silicon oxide layer IV110, an amorphous silicon layer II111, an anti-reflection material layer 112, a polysilicon layer III113, a dielectric layer 114, a contact hole tungsten plug structure 115 and a metal interconnection layer 116 are shown.
Detailed Description
The present invention is further illustrated by the following examples, but it should not be construed that the scope of the above-described subject matter is limited to the following examples. Various substitutions and alterations can be made without departing from the technical idea of the invention and the scope of the invention is covered by the present invention according to the common technical knowledge and the conventional means in the field.
Example 1:
referring to fig. 1 to 17, a method for manufacturing a silicon germanium heterojunction bipolar transistor based on a BiCMOS process includes the following steps:
1) and selecting a silicon-based substrate.
2) A LOCOS (local oxidation isolation of silicon) isolation field oxide layer is grown between an emitter active region and a collector active region of a SiGe (silicon germanium) HBT transistor by using a silicon nitride hard mask method at one time, and the LOCOS isolation field oxide layer is subjected to wet etching to form the optimal silicon-based substrate 100.
The steps for forming the optimal silicon-based substrate 100 are as follows:
2.1) depositing a thin oxide layer I101 and a silicon nitride layer I102 on the silicon substrate in sequence.
2.2) determining an isolation pattern I between an emitter and a collector of the SiGe HBT transistor and manufacturing a photoetching plate.
And 2.3) carrying out photoetching exposure on the silicon nitride layer I102 according to the pattern of the photoetching plate, and etching the silicon nitride layer I102 to obtain an isolation region I between the emitter and the collector.
2.4) growing a LOCOS oxide layer I103 in the isolation region between the emitter and the collector. The thickness of the LOCOS oxide layer I103 is 0.7-1.3 times of the LOCOS oxide layer II106 in the subsequent process steps;
2.5) wet stripping the silicon nitride layer I102 and wet etching the oxide layer I101 to form the optimal silicon-based substrate 100.
3) And forming a LOCOS field oxide layer between an emitter active region and a collector active region of the SiGe HBT transistor and a LOCOS oxide layer for isolation between devices by using a secondary silicon nitride hard mask method.
The devices refer to active devices and passive devices provided by other platforms such as SiGe HBT transistors, NMOS and PMOS provided by the BiCMOS process.
The BiCMOS process is a novel process technology for simultaneously integrating Bipolar Junction Transistors (BJTs) and CMOS devices on the same chip.
The LOCOS field oxide layer between the emitter active region and the collector active region and the LOCOS oxide layer for isolation between devices are grown simultaneously by the same thermal oxidation process, so that the thicknesses are the same, and the positions are determined by corresponding layout design patterns.
The steps of forming the LOCOS field oxide layer between the emitter active region and the collector active region of the SiGe HBT transistor and the LOCOS oxide layer for isolation between devices are as follows:
3.1) depositing a thin oxide layer II104 and a silicon nitride layer II105 on the optimal silicon-based substrate 100.
And 3.2) determining an isolation pattern II and an inter-device isolation pattern III between an emitter active region and a collector active region of the SiGe HBT, and manufacturing a photoetching plate.
The determinant of the isolation pattern II between the emitter active region and the collector active region of the SiGe HBT transistor comprises the isolation pattern I between the emitter and the collector of the SiGe HBT transistor.
3.3) carrying out photoetching exposure on the silicon nitride layer II105 according to the pattern of the photoetching plate, and etching the silicon nitride layer II105 to obtain an isolation region II between an emitter active region and a collector active region and an inter-device isolation region III.
3.4) growing a LOCOS oxide layer II106 within the isolation region II between the emitter and collector active regions and the inter-device isolation region III.
And 3.5) wet stripping the silicon nitride layer II105, and wet etching the oxide layer II104 to form a low-step outer base region of the SiGe HBT transistor, active regions of other devices and field regions of other devices.
The other devices refer to other active devices and passive devices such as NMOS and PMOS except SiGe HBT transistor provided by BiCMOS process.
4) And forming a base region window of the SiGe HBT transistor on the surface of the optimal silicon-based substrate 100.
The steps of forming the base region window of the SiGe HBT transistor are as follows:
4.1) depositing a silicon oxide layer III107 and an amorphous silicon layer I108 on the surfaces of the active area of the SiGe HBT transistor and the LOCOS oxide layer II106 in sequence.
4.2) etching the amorphous silicon layer I108 and the silicon oxide layer III107 in sequence to form a base window.
5) A SiGe HBT transistor base epitaxial material layer 109 is formed on the surface of the optimal silicon-based substrate 100.
The steps of forming the SiGe HBT transistor base epitaxial material layer 109 are as follows:
5.1) performing pre-deposition cleaning on the surface of the optimal silicon-based substrate 100.
5.2) after the cleaning is finished, growing a SiGe epitaxial material layer 109 on the surface of the optimal silicon-based substrate 100 by utilizing rapid thermal processing chemical vapor deposition. The SiGe epitaxial material layer 109 includes a silicon buffer layer, a SiGe layer, and a silicon cap layer. The SiGe epitaxial material layer 109 includes a germanium concentration ramp-up region, a plateau region, and a step-down region.
6) And forming an emitter region window of the SiGe HBT transistor on the surface of the optimal silicon-based substrate 100.
The steps of forming the emitter window of the SiGe HBT transistor are as follows:
6.1) depositing a silicon oxide layer IV110, an amorphous silicon layer II111 and an antireflection material layer 112 on the surface of the SiGe epitaxial material layer 109 in sequence.
6.2) etching the anti-reflection material layer 112, the amorphous silicon layer II111 and the silicon oxide layer IV110 in sequence until the silicon cap layer is exposed to form an emitting area window.
7) And forming a polycrystalline emitter junction fine structure and an outer base region of the SiGe HBT transistor on the surface of the optimal silicon-based substrate 100.
The steps of forming the fine structure of the polycrystalline emitter junction and the outer base region of the SiGe HBT transistor are as follows:
7.1) filling the emitter region window with polysilicon and impurity doping, a polysilicon layer III113 serving as an emitter is formed.
7.2) spin-coating an anti-reflection coating and a photoresist on the surface of the polycrystalline silicon layer III113, and forming a polycrystalline emission fine structure by dry etching.
7.3) forming the SiGe HBT transistor outer base region by utilizing dry etching and tape glue injection.
7.4) carrying out impurity activation of the emitter region and the base region by utilizing rapid thermal annealing.
8) And depositing a dielectric layer 114 on the surface of the optimal silicon-based substrate 100 to complete the interconnection of metal, thereby forming a complete SiGe HBT transistor.
The steps for forming a complete SiGe HBT transistor are as follows:
8.1) formation of Ti/Co salicide (titanium silicon compound or cobalt silicon compound). Salicide stands for Salicide.
8.2) depositing a dielectric layer 114 on the surface of the optimized silicon-based substrate 100.
8.3) completing the photoetching and etching of the contact hole to form a contact hole tungsten plug structure 115.
8.4) completing the deposition, photoetching and etching of the metal electrode.
8.5) forming metal interconnection lines to form metal interconnection layers 116, thereby completing the CMOS process to obtain the complete SiGe HBT transistor, see fig. 14, wherein B, E, C respectively indicates the base, emitter and collector of the SiGe HBT transistor.
Example 2:
a method for manufacturing a silicon germanium heterojunction bipolar transistor based on a BiCMOS process comprises the following steps:
1) and forming the optimized silicon-based substrate by adopting a silicon nitride hard mask LOCOS field oxygen method.
In this embodiment, referring to fig. 2 to 6, a substrate (silicon wafer) 100 is cleaned in a conventional SPM manner, after cleaning, a pad oxide layer 101 is grown on the substrate by a thermal oxidation method, a silicon nitride layer 102 is deposited by an LPCVD method, and after cleaning, photolithography exposure and etching of the silicon nitride layer are performed for isolation between an emitter and a collector of the SiGe HBT transistor. After the growth of the LOCOS field oxide layer is completed, the silicon nitride and all oxide layers on the surface of the silicon are stripped by adopting a wet etching method to form an optimized silicon-based substrate, as shown in FIG. 6.
In this embodiment, the isolation pattern design between the emitter and the collector of the SiGe HBT transistor needs to be matched with the LOCOS isolation pattern in the subsequent step S102, and the growth thickness of the LOCOS field oxide layer needs to be precisely controlled.
2) And forming a LOCOS field oxide isolation region on the surface of the substrate by using a secondary silicon nitride hard mask.
In this embodiment, the optimized silicon substrate (silicon wafer) 100 is cleaned by a conventional SPM method, after cleaning, a second pad oxide layer 104 is grown on the substrate by a thermal oxidation method, a second silicon nitride layer 105 is deposited by an LPCVD method, and after completion, the LOCOS active region is subjected to photolithography exposure and silicon nitride layer etching. After that, the LOCOS field oxide layer is grown, and then the silicon nitride on the silicon surface is stripped by wet etching to form a LOCOS field oxide isolation region and an active device region of the device, as shown in fig. 10.
In this embodiment, the LOCOS isolation pattern design in step S102 needs to be matched with the LOCOS isolation pattern design in the LOCOS active region, and the LOCOS field oxide isolation region and the active device region of the device are formed after all processes are completed, where the step difference is greatly reduced in comparison with the silicon surface of the active region in the outer base region step and the device isolation field oxide step of the SiGe HBT transistor. This lays a good foundation for the subsequent emitter junction lithography.
3) And forming a SiGe HBT transistor base region window on the surface of the substrate.
In this embodiment, referring to fig. 10, a substrate is cleaned by a conventional SPM method, after the cleaning, a first silicon oxide layer 12 is deposited in an active region and a field oxide region by an LPTEOS method, then a third pad oxide layer 107 and a base window amorphous silicon layer 108 are deposited by LPCVD, and the amorphous silicon layer 108 and the third pad oxide layer 107 are sequentially etched to form a transistor base window, as shown in fig. 11.
4) And forming a SiGe HBT transistor base region epitaxial material layer on the surface of the substrate.
In this embodiment, referring to fig. 11, a conventional SC1+ SC2+50:1HF manner is adopted to clean the surface of the silicon wafer before deposition, and after cleaning, a SiGe composite layer 109 is grown on the surface of the silicon wafer by using rapid thermal processing chemical vapor deposition (RPCVD), where the SiGe composite layer 109 includes a silicon buffer layer, a SiGe layer, and a silicon cap layer. The silicon buffer layer is mainly used for buffering the interface of the SiGe layer and the silicon substrate so as to reduce defects; the SiGe layer is used as a base region, wherein the SiGe layer comprises a germanium concentration rapid rising region, a platform region and a gradual reduction region; the silicon cap layer is used for doping impurity ions in the polycrystalline silicon to diffuse towards the monocrystalline silicon to form a shallow emitter junction.
5) A SiGe HBT transistor emitter window is formed on a surface of the substrate.
In this embodiment, referring to fig. 12, the silicon wafer surface is cleaned before deposition by using a conventional SPM + SC1+ SC2 method. After the cleaning is finished, an emitter junction pad oxide layer 110, an emitter junction amorphous silicon layer 111 and an emitter junction anti-reflection material layer 112 are deposited on the SiGe composite layer 109 structure in sequence.
The position of the emitting region window is defined by photoetching with photoresist, the anti-reflection material layer 112, the emitting junction amorphous silicon layer 111 and the emitting junction pad oxide layer 110 are etched in sequence until the SiGe composite layer 109 is exposed, and generally, dry plasma etching can be adopted for etching the anti-reflection material layer 112 and the emitting junction amorphous silicon layer 111. And the etching of the emitter junction pad oxide layer 110 is usually performed by wet etching to ensure that the SiGe composite layer 109 is not damaged, which is beneficial to controlling the defects of the emitter junction interface and improving the device characteristics. In this embodiment, the thickness of the anti-reflection material layer is 30-40nm, and the material is a silicon nitride layer.
6) And forming a SiGe HBT transistor polycrystalline emitter junction fine structure and an outer base region on the surface of the substrate.
In this embodiment, referring to fig. 13, LPCVD is used to deposit an emitter poly layer 113 on the surface of the silicon wafer, and the emitter poly layer 113 is doped by implanting P element or As element. After the completion, the position of the emitter is defined by photoetching with photoresist, and the anti-reflection material layer 112 and the emitter junction amorphous layer 111 are etched in sequence by dry etching, so that the polycrystalline emitter fine structure of the SiGe HBT transistor is formed. In this embodiment, the thickness of the anti-reflective coating is 50-60nm, and the thickness of the photoresist is 800-1000 nm. In the step S101-S102, a local two-time silicon nitride hard mask oxidation process method is implemented for the LOCOS field oxide layer between the emitter and the collector of the SiGe HBT, so that the high step of the outer base region of the HBT is reduced, the influence of reflection of the high step of the outer base region on emitter junction polycrystalline lithography is reduced, the formation of a fine structure of the SiGe HBT polycrystalline emitter is improved, the structural integrity of a SiGe HBT device is greatly improved, the repeatability and uniformity of key parameters of the device are improved, and the yield is greatly improved.
In this embodiment, referring to fig. 15, the subsequent processes further include deposition and etching of an oxide layer on the sidewall of the emitter, and photolithography and etching of the outer base region, and finally a complete SiGe HBT device structure is formed as shown in fig. 16.
7) A SiGe HBT transistor is formed. Completing interconnection to form a complete SiGe HBT transistor;
in this embodiment, referring to fig. 16, deposition of a dielectric layer 114, filling of a contact hole tungsten plug 115, deposition of a metal interconnection layer 116, photolithography, etching, and the like are completed. And after the processing technology is finished, forming a complete SiGe HBT transistor.
Claims (10)
1. A method for manufacturing a silicon germanium heterojunction bipolar transistor based on a BiCMOS process is characterized by comprising the following steps:
1) and selecting the silicon-based substrate.
2) Growing a LOCOS isolation field oxide layer between an emitter active region and a collector active region of the SiGeHBT transistor by using a silicon nitride hard mask method, and performing wet etching on the LOCOS isolation field oxide layer to form an optimal silicon-based substrate (100);
3) forming a LOCOS field oxide layer between an emitter active region and a collector active region of the SiGe HBT transistor and a LOCOS oxide layer for isolation between devices by using a secondary silicon nitride hard mask method; the device comprises a SiGe HBT transistor, an NMOS device and a PMOS device;
4) forming a SiGe HBT transistor base region window on the surface of the optimal silicon-based substrate (100);
5) forming a SiGeHBT transistor base region epitaxial material layer (109) on the surface of the optimal silicon-based substrate (100);
6) forming a SiGe HBT transistor emitter window on the surface of an optimal silicon-based substrate (100);
7) forming a SiGe HBT transistor polycrystalline emitter junction fine structure and an outer base region on the surface of an optimal silicon-based substrate (100);
8) and depositing a dielectric layer (114) on the surface of the optimal silicon-based substrate (100), and completing the interconnection of metal to form a complete SiGe HBT transistor.
2. Method of manufacturing a silicon germanium heterojunction bipolar transistor according to claim 1 or 2, characterized in that the step of forming an optimized silicon based substrate (100) is as follows:
1) depositing a thin oxide layer I (101) and a silicon nitride layer I (102) on a silicon-based substrate in sequence;
2) determining an isolation graph I between an emitter and a collector of the SiGeHBT transistor, and manufacturing a photoetching plate;
3) photoetching and exposing the silicon nitride layer I (102) according to the pattern of the photomask, and etching the silicon nitride layer I (102) to obtain an isolation region I between the emitter and the collector;
4) growing a LOCOS oxide layer I (103) in an isolation region between an emitter and a collector;
5) and wet stripping the silicon nitride layer I (102) and wet etching the oxide layer I (101) to form the optimal silicon-based substrate (100).
3. The method of claim 1, wherein the steps of forming a LOCOS field oxide layer between an emitter active region and a collector active region of the SiGe HBT transistor and a LOCOS oxide layer for isolation between devices are as follows:
1) depositing a thin oxide layer II (104) and a silicon nitride layer II (105) on an optimized silicon-based substrate (100);
2) determining an isolation pattern II and an isolation pattern III between devices between an emitter active region and a collector active region of the SiGe HBT transistor, and manufacturing a photoetching plate;
3) photoetching and exposing the silicon nitride layer II (105) according to the pattern of the photoetching plate, and etching the silicon nitride layer II (105) to obtain an isolation region II between an emitter active region and a collector active region and an isolation region III between devices;
4) growing a LOCOS oxide layer II (106) in an isolation region II between an emitter active region and a collector active region and an inter-device isolation region III;
5) wet stripping the silicon nitride layer II (105), and wet etching the oxide layer II (104) to form a low-step outer base region of the SiGe HBT transistor, an active region of other devices and field regions of other devices; including active and passive devices other than SiGe HBT transistors.
4. The method as claimed in claim 1, wherein the determining factor of the isolation pattern II between the emitter active region and the collector active region of the SiGe HBT transistor comprises an isolation pattern I between the emitter and the collector of the SiGe HBT transistor.
5. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 1, wherein the step of forming the base window of the SiGe HBT transistor is as follows:
1) depositing a silicon oxide layer III (107) and an amorphous silicon layer I (108) on the surfaces of the active area of the SiGe HBT transistor and the LOCOS oxide layer II (106) in sequence;
2) and etching the amorphous silicon layer I (108) and the silicon oxide layer III (107) in sequence to form a base region window.
6. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 1, wherein the step of forming the SiGe HBT transistor base epitaxial material layer (109) is as follows:
1) cleaning the surface of the optimal silicon-based substrate (100) before deposition;
2) after cleaning, growing a SiGe epitaxial material layer (109) on the surface of the optimal silicon-based substrate (100) by utilizing rapid thermal processing chemical vapor deposition; the SiGe epitaxial material layer (109) comprises a silicon buffer layer, a SiGe layer and a silicon cap layer; the SiGe epitaxial material layer (109) comprises a germanium concentration fast-rise region, a plateau region and a step-down region.
7. The method of manufacturing a SiGe heterojunction bipolar transistor according to claim 1, wherein the step of forming the emitter window of the SiGe HBT transistor is as follows:
1) depositing a silicon oxide layer IV (110), an amorphous silicon layer II (111) and an anti-reflection material layer (112) on the surface of the SiGe epitaxial material layer (109) in sequence;
2) and etching the anti-reflection material layer (112), the amorphous silicon layer II (111) and the silicon oxide layer IV (110) in sequence until the silicon cap layer is exposed to form an emitting area window.
8. The method for manufacturing the silicon-germanium heterojunction bipolar transistor according to claim 1, wherein the steps of forming the polycrystalline emitter junction fine structure and the extrinsic base region of the SiGe HBT transistor are as follows:
1) filling the emitter region window with polysilicon, and performing impurity doping to form a polysilicon layer III (113) serving as an emitter;
2) spin-coating an anti-reflection coating and photoresist on the surface of the polycrystalline silicon layer III (113), and forming a polycrystalline emission fine structure through dry etching;
3) forming an outer base region of the SiGe HBT transistor by using dry etching and tape glue injection;
4) and carrying out impurity activation on the emitter region and the base region by utilizing rapid thermal annealing.
9. The method of manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 1, wherein the step of forming a complete SiGe HBT transistor is as follows:
1) forming Ti/Co salicide;
2) depositing a dielectric layer (114) on the surface of the optimal silicon-based substrate (100);
3) completing photoetching and etching of the contact hole to form a contact hole tungsten plug structure (115);
4) finishing the deposition, photoetching and etching of the metal electrode;
5) and arranging metal connecting wires and forming a metal interconnection layer (116), thereby completing the CMOS processing technology and obtaining the complete SiGe HBT transistor.
10. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 1, wherein the thickness of the LOCOS oxide layer I (103) is denoted by h1, and the thickness of the LOCOS oxide layer II (106) is denoted by h 2; wherein h1 ═ 0.7h2, 1.3h2] > 0; h2> 0.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224375A (en) * | 1992-12-18 | 1994-08-12 | Kaho Denshi Kofun Yugenkoshi | Preparing bipolar transistor for bicmos |
| US20020142558A1 (en) * | 2001-03-29 | 2002-10-03 | Hsu Sheng Teng | Self-aligned SiGe HBT BiCMOS on SOI substrate and method of fabricating the same |
| US6617619B1 (en) * | 2002-02-04 | 2003-09-09 | Newport Fab, Llc | Structure for a selective epitaxial HBT emitter |
| US20050051797A1 (en) * | 2003-09-05 | 2005-03-10 | United Microelectronics Corp. | Fabrication method for heterojunction bipolar transistor |
| US20070202642A1 (en) * | 2006-02-24 | 2007-08-30 | Nanda Arun K | Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method |
| US20090206335A1 (en) * | 2003-12-05 | 2009-08-20 | Bernd Heinemann | Bipolar complementary semiconductor device |
| US20120091509A1 (en) * | 2010-10-14 | 2012-04-19 | Donghua Liu | Silicon-germanium heterojunction bipolar transistor |
| CN102723361A (en) * | 2012-07-16 | 2012-10-10 | 西安电子科技大学 | Self-aligned-technology-based tri-polycrystal SOI (Silicon On Insulator), SiGe and HBT (Heterojunction Bipolar Transistor) integrated device and preparation method thereof |
| US20150162322A1 (en) * | 2013-12-05 | 2015-06-11 | Northrop Grumman Systems Corporation | Bipolar junction transistor device and method of making the same |
| CN105990254A (en) * | 2015-03-05 | 2016-10-05 | 北大方正集团有限公司 | Manufacturing method of BiCMOS integrated circuit |
| CN108615682A (en) * | 2018-05-18 | 2018-10-02 | 中国电子科技集团公司第二十四研究所 | The production method of silicon-germanium heterojunction bipolar transistor emitter |
| CN108630748A (en) * | 2018-05-09 | 2018-10-09 | 燕山大学 | Whole plane Terahertz composite strain Si/SiGe heterojunction bipolar transistors and preparation method |
-
2020
- 2020-08-28 CN CN202010884582.XA patent/CN112071757B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224375A (en) * | 1992-12-18 | 1994-08-12 | Kaho Denshi Kofun Yugenkoshi | Preparing bipolar transistor for bicmos |
| US20020142558A1 (en) * | 2001-03-29 | 2002-10-03 | Hsu Sheng Teng | Self-aligned SiGe HBT BiCMOS on SOI substrate and method of fabricating the same |
| US6617619B1 (en) * | 2002-02-04 | 2003-09-09 | Newport Fab, Llc | Structure for a selective epitaxial HBT emitter |
| US20050051797A1 (en) * | 2003-09-05 | 2005-03-10 | United Microelectronics Corp. | Fabrication method for heterojunction bipolar transistor |
| US20090206335A1 (en) * | 2003-12-05 | 2009-08-20 | Bernd Heinemann | Bipolar complementary semiconductor device |
| US20070202642A1 (en) * | 2006-02-24 | 2007-08-30 | Nanda Arun K | Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method |
| US20120091509A1 (en) * | 2010-10-14 | 2012-04-19 | Donghua Liu | Silicon-germanium heterojunction bipolar transistor |
| CN102723361A (en) * | 2012-07-16 | 2012-10-10 | 西安电子科技大学 | Self-aligned-technology-based tri-polycrystal SOI (Silicon On Insulator), SiGe and HBT (Heterojunction Bipolar Transistor) integrated device and preparation method thereof |
| US20150162322A1 (en) * | 2013-12-05 | 2015-06-11 | Northrop Grumman Systems Corporation | Bipolar junction transistor device and method of making the same |
| CN105990254A (en) * | 2015-03-05 | 2016-10-05 | 北大方正集团有限公司 | Manufacturing method of BiCMOS integrated circuit |
| CN108630748A (en) * | 2018-05-09 | 2018-10-09 | 燕山大学 | Whole plane Terahertz composite strain Si/SiGe heterojunction bipolar transistors and preparation method |
| CN108615682A (en) * | 2018-05-18 | 2018-10-02 | 中国电子科技集团公司第二十四研究所 | The production method of silicon-germanium heterojunction bipolar transistor emitter |
Non-Patent Citations (1)
| Title |
|---|
| 钟怡: "20GHz SiGe HBT器件设计与工艺研究", 中国优秀硕士学位论文全文数据库 信息科技辑, no. 03 * |
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