JPH11204668A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which the number of impurity implantation steps is reduced, while ensuring the drain withstanding voltage of a MOS transistor. SOLUTION: Even when boron concentration for forming a lightly doped drain LD of a double diffusion drain D which exists in a PMOS region 44 is made the same as a boron concentration necessary for forming an active base AB present in an NPN region 46, a channel length CL is made long, so that a drain withstanding voltage becomes a predetermined value or higher. Therefore, even if boron is subjected to injection and diffusion for forming the drain LD and boron is injected and diffused for forming the base AB in the same process, the drain withstanding voltage of a P-channel MOS transistor can be ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a MOS having a double diffusion drain.
The present invention relates to a technique for forming a transistor and a bipolar transistor on the same semiconductor substrate.

[0002]

2. Description of the Related Art A bi-CMOS type IC in which a MOS transistor having a double diffusion drain for increasing a drain breakdown voltage and a bipolar transistor are formed on one chip is known. FIGS. 6A to 7B are cross-sectional views for explaining a manufacturing process of such a bi-CMOS type IC.

To manufacture a bi-CMOS type IC, FIG.
As shown in A, an N-type epitaxial growth layer 4, an N ⁺ -type buried layer 6, a field oxide film 8, a gate oxide film 10, and a gate 12 are prepared on a P-type semiconductor substrate 2.

Then, using resist 20 and field oxide film 8 as a mask, base forming region 1 of NPN region 16 for forming an NPN bipolar transistor is formed.
8 is injected with a low concentration of boron (B).

The conditions for implanting boron ions are as follows: ion concentration Q = 1 × 10 ¹³ [cm ⁻² ] implantation energy E = 30 [KeV].

Next, after removing the resist 20, 9
A heat treatment (annealing treatment) is performed at 50 ° C. for 30 minutes. As a result, the boron ions implanted into the base formation region 18 diffuse to some extent (see FIG. 6B).

Further, as shown in FIG. 6B, using another resist 22, field oxide film 8 and gate 14 as a mask, source / drain formation region 2 of PMOS region 14 for forming a P-channel type MOS transistor.
4 is implanted with a low concentration of boron (B).

The conditions for implanting boron ions are as follows: ion concentration Q = 1 × 10 ¹² [cm ⁻² ]; implantation energy E = 30 [KeV].

Next, after removing the resist 22, 1
A heat treatment (annealing treatment) is performed at 000 ° C. for 30 minutes. This causes the boron ions implanted into the source / drain formation region 24 to diffuse, as shown in FIG. 7A.
At this time, the boron ions previously implanted into the base formation region 18 are further diffused. Next, high-concentration boron ions and high-concentration phosphorus ions or arsenic ions are implanted and diffused into a predetermined region, thereby obtaining a structure shown in FIG. As shown in FIG. 3, the emitter E and the external base E
B and a collector C are formed, and a high concentration source HS and a high concentration drain HD are formed in the source / drain formation region 24.

The emitter E and the external base EB in the base forming region 18 into which low concentration boron ions are implanted and diffused.
The other part becomes the active base AB. In the source / drain formation region 24 into which the low concentration boron ions have been implanted and diffused, portions other than the high concentration source HS and the high concentration drain HD become the low concentration source LS and the low concentration drain LD, respectively. The high concentration source HS and the low concentration source LS form a double diffusion source S. The double diffusion drain D is formed by the high concentration drain HD and the low concentration drain LD.

In this manner, a bi-CMOS type IC in which a MOS transistor having a double diffusion drain D for increasing the drain withstand voltage and a bipolar transistor are formed on one chip can be formed.

[0012]

However, the above-mentioned conventional method for manufacturing a bi-CMOS type IC has the following problems. As mentioned above, conventional bi-CM
In the method of manufacturing the OS-type IC, the base formation region 18
And a step of implanting and diffusing low-concentration boron (B) into the source / drain formation region 24 are separately performed. This is for the following reason.

To function as an activity-based AB,
As described above, it is necessary to implant boron ions having an ion concentration of about 1 × 10 ¹³ [cm ⁻² ]. On the other hand, if the concentration of boron ions implanted into the source / drain formation region 24 is set to this level, the boron concentration of the low-concentration drain LD becomes too high, and the drain breakdown voltage decreases.

In the step of implanting and diffusing low-concentration boron (B) into the source / drain formation region 24,
The step of implanting and diffusing low-concentration boron (B) into the base formation region 18 is performed separately with the ion concentration Q = 1 × 10 ¹² [cm ⁻² ]. By doing so, the drain withstand voltage is secured.

However, the impurity implantation / diffusion step involves a number of steps (resist coating, pre-baking (pre-baking), exposure, development, baking (post-baking), ion implantation, resist stripping, annealing, etc.). Therefore, if the number of impurity implantation / diffusion steps is large, the manufacturing cost of the semiconductor device increases, and the manufacturing time is prolonged, resulting in poor productivity.

The present invention solves such a problem,
It is an object of the present invention to provide a method of manufacturing a semiconductor device having a small number of impurity implantation steps while ensuring a drain breakdown voltage of a MOS transistor.

[0017]

Means for Solving the Problems, Functions and Effects of the Invention
The method of manufacturing a semiconductor device according to claim 1, wherein the concentration of the impurity of the first conductivity type for forming the low concentration diffusion region of the double diffusion drain is the first conductivity type required for forming the base region of the bipolar transistor. The channel length of the MOS transistor is increased so that the drain breakdown voltage of the MOS transistor is equal to or higher than a predetermined value even when the impurity concentration is the same.

Therefore, by increasing the channel length of the MOS transistor, the implantation and diffusion of the impurity for forming the low concentration diffusion region and the implantation and diffusion of the impurity for forming the base region are performed in the same step. Also MO
It is possible to secure the drain breakdown voltage of the S transistor. That is, it is possible to reduce the number of steps of implanting and diffusing impurities while ensuring the drain breakdown voltage of the MOS transistor.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: injecting and diffusing a first conductivity type impurity for forming a low concentration diffusion region; The feature is that the implantation depth of the impurity is increased so that the drain breakdown voltage of the MOS transistor becomes a predetermined value or more even when the implantation diffusion conditions are the same.

By increasing the implantation depth of the impurity, the diffusion distance for obtaining the base region having the required depth can be reduced. If the diffusion distance can be reduced,
The drain withstand voltage of the MOS transistor can be ensured without making the channel length long. That is, it is possible to secure the drain breakdown voltage of the MOS transistor while suppressing an increase in the channel length.

[0021]

1A to 3B are cross-sectional views illustrating a method for manufacturing a bi-CMOS type IC (semiconductor device) according to an embodiment of the present invention. The bi-CMOS type IC in this embodiment is an IC in which a MOS transistor having a double diffusion drain and a double diffusion source and a bipolar transistor are formed on one chip.
It is.

To manufacture this bi-CMOS type IC,
First, as shown in FIG. 1A, a substrate in which an N-type epitaxial growth layer 34, an N ⁺ -type buried layer 36, and a field oxide film 38 are formed on a P-type semiconductor substrate 32 is prepared. The field oxide film 38 is, for example, a LOCOS
(Local Oxidation of Silicon) method.

In the epitaxial growth layer 34, a region for forming a P-channel MOS transistor is
It is called a PMOS region 44. A region for forming an NPN-type bipolar transistor is called an NPN region 46.

Next, as shown in FIG. 1B, a gate oxide film 40
A gate 42 is formed. Gate oxide film 40 is formed by thermally oxidizing the surface of epitaxial growth layer 34.

The gate 42 is, for example, a low pressure CVD (Ch
This is formed by depositing polysilicon using an emical vapor deposition method or the like and then patterning the deposited polysilicon. The polysilicon is patterned by forming a resist (not shown) in a predetermined shape and using the resist as a mask by RIE (reactive ion etching).
In this embodiment, the gate length GL is longer than the conventional gate length. The reason will be described later.

Then, as shown in FIG. 2A, the exposed surfaces of the epitaxial growth layer 34 and the gate 42 are thermally oxidized to form an oxide film 52 (ligated thermal oxidation). In this embodiment, the thickness of the oxide film 52 is about 430 angstroms.

Next, as shown in FIG.
6, the resist 56 and the field oxide film 38 are formed.
Using the gate 42 as a mask, low-concentration boron (B) as a first conductivity type impurity is ion-implanted into the base formation region 48 of the NPN region 46 and the source / drain formation region 54 of the PMOS region 44.

The boron ion implantation conditions are as follows: ion concentration Q = 1 × 10 ¹³ [cm ⁻² ] implantation energy E = 90 [KeV].

Next, after removing the resist 56, a heat treatment (annealing treatment) is performed at about 1000 ° C. for 30 minutes. As a result, as shown in FIG. 3A, the boron ions implanted into the base formation region 48 and the source / drain formation region 54 diffuse.

Next, high-concentration boron ions and high-concentration phosphorus ions or arsenic ions are implanted into predetermined regions and diffused, as shown in FIG.
An emitter E, an external base EB, and a collector C are formed in the region 46, and a high concentration source HS and a high concentration drain HD are formed in the PMOS region 44.

The emitter E and the external base EB in the base forming region 48 into which low concentration boron ions are implanted and diffused.
The other part becomes the active base AB (base region). In the source / drain formation region 54 into which low-concentration boron ions have been implanted and diffused, portions other than the high-concentration source HS and the high-concentration drain HD are low-concentration sources L, respectively.
S, becomes a low concentration drain LD (low concentration diffusion region). The high concentration source HS and the low concentration source LS form a double diffusion source S. The double diffusion drain D is formed by the high concentration drain HD and the low concentration drain LD.

Next, a step of forming an interlayer insulating film (not shown), a step of forming wiring (not shown), a step of forming a passivation film (not shown), etc.
A MOS type IC is manufactured.

As described above, in this embodiment,
The gate length GL is longer than the conventional gate length (see FIG. 1B). Therefore, as shown in FIG. 3B,
Channel length CL of P-channel MOS transistor
Is longer than before. The channel length CL is set to be longer than the conventional one for the following reason.

As described above, in this embodiment,
Two low-concentration boron implantation / diffusion steps which have conventionally been separate steps (ie, low-concentration boron implantation / diffusion step for the base formation region and low-concentration boron implantation / diffusion step for the source / drain formation region of the PMOS region) And a single low-concentration boron implantation / diffusion process.

For this reason, the concentration of boron for forming the low-concentration drain LD is made equal to the concentration of boron necessary for forming the active base AB. As a result, the concentration of boron in the low-concentration drain LD becomes higher than before. Therefore, the channel length CL of the P-channel MOS transistor is set to be longer than before so that the same source-drain breakdown voltage as before can be ensured even if the boron concentration is higher than before. is there.

That is, by setting the channel length CL of the P-channel type MOS transistor to be longer than before, it is possible to reduce the number of steps of implanting and diffusing low-concentration boron while ensuring the drain breakdown voltage of the P-channel type MOS transistor. .

In this embodiment, as described above, the implantation energy of the low-concentration boron is set higher than in the conventional case. This is for the following reason.

As described above, conventionally, boron implanted into the base formation region is subjected to two annealing treatments (annealing treatment for boron implanted into the base formation region and implantation into the source / drain formation region). (Annealing treatment for boron) to obtain a depth required for the active base AB.

However, in this embodiment, as described above, the depth required for the active base AB is set by diffusion by one annealing process. Therefore, if boron is implanted with the same energy as the conventional one, a diffusion distance corresponding to two conventional annealing treatments is necessary to secure the same depth as the conventional one.

As a result, the diffusion distance between the low-concentration source LS and the low-concentration drain LD becomes too large as compared with the conventional case. Low concentration source LS and low concentration drain LD
Increase in the diffusion distance of P-channel type M
The channel length of the OS transistor is shortened,
This makes it impossible to ensure the drain breakdown voltage. In order to ensure the source-drain breakdown voltage, the channel length of the P-channel MOS transistor needs to be further increased.

Therefore, the annealing process for the implanted boron is set to be substantially the same as the annealing process for the boron implanted in the conventional source / drain formation region, so that the source / drain can be formed without further increasing the channel length. By ensuring a high breakdown voltage and setting the implantation energy of low-concentration boron higher than before,
The depth of the active base AB is ensured.

That is, by setting the implantation energy of low-concentration boron higher than before, it is possible to secure the drain breakdown voltage of the MOS transistor while suppressing an increase in the channel length.

By setting the implantation energy of the low-concentration boron higher than in the prior art, the low-concentration drain LD
Becomes deeper than before. For this reason, the withstand voltage between the drain and the substrate is higher than in the conventional case.

Next, FIGS. 4A to 5B show a bi-CMOS type IC (semiconductor device) according to another embodiment of the present invention.
Is a cross-sectional view for explaining the method of manufacturing the semiconductor device. The bi-CMOS type IC in this embodiment does not have a double diffusion source unlike the above-described embodiment. That is, while the drain has a double diffusion structure, the source is composed of only a normal high concentration diffusion layer.

The method of manufacturing the bi-CMOS type IC is similar to the above-described embodiment. 4A are the same as the steps shown in FIGS. 1A to 2A described above.

Next, as shown in FIG.
6, the resist 56 and the field oxide film 38 are formed.
And gate 42 as a mask, drain formation region 60 of base formation region 48 of NPN region 46 and source / drain formation region 54 of PMOS region 44
Then, low-concentration boron (B) as an impurity is ion-implanted.

Unlike the above-described embodiment, the source forming region 58 is masked with a resist 56. Therefore,
Low concentration boron is not implanted into the source forming region 58. The conditions for implanting boron ions are the same as in the above-described embodiment.

Next, after removing the resist 56, an annealing process is performed. The conditions for the annealing treatment are the same as those in the above-described embodiment. As a result, as shown in FIG. 5A, the base formation region 48 and the drain formation region 6 are formed.
The boron ions implanted into the region 0 diffuse.

Next, high-concentration boron ions and high-concentration phosphorus ions or arsenic ions are implanted into predetermined regions and diffused, thereby obtaining NPN as shown in FIG. 5B.
An emitter E, an external base EB, and a collector C are formed in the region 46, and a source S and a high-concentration drain HD are formed in the PMOS region 44.

The emitter E and the external base EB in the base forming region 48 into which low-concentration boron ions are implanted and diffused.
Except for this, the active base AB (base region) is the same as in the above-described embodiment.

In the drain formation region 60 into which low-concentration boron ions are implanted and diffused, the high-concentration drain HD
Except for the low concentration drain LD (low concentration diffusion region)
Becomes High concentration drain HD and low concentration drain LD
As a result, a double diffusion drain D is formed. As described above, the source S is composed of only a normal high concentration diffusion layer.

Next, similarly to the above-described embodiment, a step of forming an interlayer insulating film (not shown), a step of forming a wiring (not shown), a step of forming a passivation film (not shown), and the like. After that, a bi-CMOS type IC is manufactured.

In each of the above embodiments, the first
Although the implantation depth of the conductivity type impurity is increased, the depth of the base region may be shallow, or the depth of the base region is required but the drain breakdown voltage of the MOS transistor may be low. The implantation depth of the impurity of the first conductivity type does not necessarily have to be deep.

In addition, although the depth of the base region is required and the drain breakdown voltage of the MOS transistor must be ensured, the first conductivity type can be used even when the channel length can be increased. It is not necessary to increase the implantation depth of the impurity.

In each of the above embodiments, the MO
Although an example has been described where the S transistor is a P-channel type MOS transistor and the bipolar transistor is an NPN type bipolar transistor, the present invention is not limited to such a case. For example, MO
The present invention can also be applied to a case where the S transistor is an N-channel type MOS transistor and the bipolar transistor is a PNP type bipolar transistor.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views illustrating a method of manufacturing a bi-CMOS type IC according to an embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating a method of manufacturing a bi-CMOS type IC according to an embodiment of the present invention.

FIGS. 3A and 3B are cross-sectional views illustrating a method of manufacturing a bi-CMOS type IC according to an embodiment of the present invention;

FIGS. 4A and 4B are cross-sectional views illustrating a method of manufacturing a bi-CMOS IC according to another embodiment of the present invention.

5A and 5B are cross-sectional views illustrating a method of manufacturing a bi-CMOS type IC according to another embodiment of the present invention.

FIGS. 6A and 6B are cross-sectional views illustrating a method for manufacturing a conventional bi-CMOS type IC.

FIGS. 7A and 7B are cross-sectional views for explaining a conventional method of manufacturing a bi-CMOS IC.

[Explanation of symbols]

 44... PMOS region 46... NPN region AB... Active base CL... Channel length D... Double diffusion drain LD. Concentration drain

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device in which a MOS transistor having a double diffusion drain and a bipolar transistor are provided on the same semiconductor substrate, the method comprising forming a low concentration diffusion region of the double diffusion drain. Even when the concentration of the one conductivity type impurity is the same as the concentration of the first conductivity type impurity necessary for forming the base region of the bipolar transistor, the drain breakdown voltage of the MOS transistor is equal to or higher than a predetermined value. And a channel length of the MOS transistor is increased. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a condition for implanting and diffusing a first conductivity type impurity for forming said low concentration diffusion region is a first conductivity type necessary for forming said base region. The depth of the impurity implantation is increased so that the drain withstand voltage of the MOS transistor is equal to or higher than a predetermined value even when the conditions for the implantation and diffusion of the impurity of the type are the same.