KR100190045B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100190045B1 KR100190045B1 KR1019960020366A KR19960020366A KR100190045B1 KR 100190045 B1 KR100190045 B1 KR 100190045B1 KR 1019960020366 A KR1019960020366 A KR 1019960020366A KR 19960020366 A KR19960020366 A KR 19960020366A KR 100190045 B1 KR100190045 B1 KR 100190045B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 51
- 239000012535 impurity Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims abstract description 20
- 239000011810 insulating material Substances 0.000 claims abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 11
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000002955 isolation Methods 0.000 description 9
- 238000007796 conventional method Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- High Energy & Nuclear Physics (AREA)
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Abstract
리트로그레이드웰을 갖는 반도체장치의 제조방법 및 그 구조가 개시되어 있다. 제1 도전형의 불순물이 도핑된 반도체기판 상에 게이트절연막 및 게이트전극을 순차적으로 형성한다. 게이트전극의 측벽에 절연물질로 이루어진 스페이서를 형성한다. 사진공정으로 제1 도전형 또는 그 반대의 제2 도전형의 모스 트랜지스터가 형성될 영역을 오픈시킨다. 오픈된 영역에, 스페이서를 마스크로 이용하여 제1 도전형 또는 제2 도전형의 제1 불순물로 웰 이온주입을 실시하고, 제1 도저형 또는 제2 도전형의 제2 불순물로 소오스/드레인 이온주입을 실시한다. 공정을 단순화하여 공정시간을 훨씬 감소시키며, 소자에 대한 이온주입의 영향을 확실하게 모니터링할 수 있다.A method of manufacturing a semiconductor device having a retrograde well and a structure thereof are disclosed. A gate insulating film and a gate electrode are sequentially formed on the semiconductor substrate doped with the impurity of the first conductivity type. A spacer made of an insulating material is formed on the sidewall of the gate electrode. The region in which the MOS transistor of the first conductivity type or the opposite conductivity type of the second conductivity type is to be formed is opened in the photolithography process. Well is ion-implanted into the open region with the first impurity of the first conductivity type or the second conductivity type using the spacer as a mask, and the second impurity of the first or second conductivity type is used as the source / Perform injection. The process can be simplified and the process time can be greatly reduced, and the influence of ion implantation on the device can be reliably monitored.
Description
제1a도 내지 제1f도는 종래방법에 의한 반도체장치의 제조방법을 설명하기 위한 단면도들.FIGS. 1A through 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a conventional method. FIG.
제2a도 내지 제2d도는 본 발명에 의한 반도체장치의 제조방법을 설명하기 위한 단면도들.FIGS. 2a through 2d are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
제3a도 및 제3b도는 종래방법 및 본 발명에 의해 제조된 반도체장치의 웰도핑 프로파일을 나타내는 단면도.Figs. 3a and 3b are cross-sectional views showing the well-doped profile of the semiconductor device manufactured by the conventional method and the present invention. Fig.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
1 : 소자분리막 2, 2' : 웰1: Element isolation film 2, 2 ': Well
4 : 게이트전극 5 : N-소오스/드레인 영역4: gate electrode 5: N - source / drain region
6 : P-소오스/드레인 영역 7 : 스페이서6: P - source / drain region 7: spacer
8 : N-소오스/드레인 영역 9 : P+소오스/드레인 영역8: N - source / drain region 9: P + source / drain region
10 : 게이트절연막 11 : 반도체기판10: gate insulating film 11: semiconductor substrate
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 리트리그레이드웰(Retrograde well)을 적용하는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a retrograde well.
일반적으로, 실리콘기판을 도핑시키는 기술로서 이온주입 설비를 이용하는 기술이 널리 사용되어 왔다. 특히, 통상의 CMOS(Complementary MOS) 기술에서는, 도판트(dopant)를 이온주입한 후 고온 장시간의 열처리 공정(예컨대, 1150℃, 8시간 이상)을 거쳐 상기 이온주입된 도판트를 적절한 깊이까지 확산시키면서 웰(well)을 형성한다(이하, 확산웰이라 한다. 그러나, 상기한 방법에 의하면 확산이 기판의 종방향뿐만 아니라 횡방향으로도 진행되기 때문에, 집적도가 떨어지게 되는 문제가 발생한다.In general, a technique of using an ion implantation facility as a technique of doping a silicon substrate has been widely used. Particularly, in a conventional CMOS (Complementary MOS) technology, a dopant is ion-implanted and then the implanted dopant is diffused to a proper depth through a high-temperature and long-time heat treatment process (for example, (Hereinafter, referred to as diffusion wells). However, according to the above-described method, since the diffusion proceeds not only in the longitudinal direction but also in the lateral direction of the substrate, there arises a problem that the degree of integration is lowered.
따라서, 소자분리막을 먼저 형성한 후 도판트가 적절한 깊이에 위치하도록 고에너지 이온주입에 의해 웰을 형성하는 방법이 개발되었는데, 상기한 웰은 실리콘기판 내의 어떤 깊이에서 불순물농도의 피크(peak)치가 나타나고 기판 표면으로 갈수록 불순물농도가 감소하기 때문에 리트로그레이드웰로 칭해진다. 상기 리트로그레이드웰은 웰형성시에 종래의 확산웰에서 사용되는 고온, 장시간의 확산공정이 생략되어 공정이 단순화되어 공정원가 절감에 큰 기여를 하며, 래치업(latch-up) 및 소프트 에러율(Soft Error Rate)등을 억제시켜 소자의 전기적 특성을 향상시키는 장점을 갖는다.Thus, a method has been developed for forming a well by high energy ion implantation so that the device isolation film is formed first and the dopant is located at an appropriate depth. The above-mentioned well has a peak value of the impurity concentration at a certain depth in the silicon substrate And is referred to as retrograded well because the impurity concentration decreases toward the substrate surface. The retrogradation well is advantageous in that the process is simplified by omitting the diffusion process at a high temperature and a long time used in a conventional diffusion well at the time of forming a well, thereby contributing to the reduction of the process cost and the latch-up and the soft error rate Error Rate) and the like, thereby improving the electrical characteristics of the device.
제1a도 내지 제1f도는 종래방법에 의한 반도체장치의 제조방법을 설명하기 위한 단면도들이다.FIGS. 1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a conventional method.
제1a도를 참조하면, 제1 도전형, 예컨대 P형의 실리콘기판(11) 상에 통상의 소자분리 공정으로 소자분리막(1)을 형성함으로써, 소자들이 형성될 활성영역을 정의한다. 사진공정으로 제2 도전형, 예컨대 N형의 모스 트랜지스터들이 형성될 영을 오픈시키는 제1 포토레지스트 패턴(12)을 형성한다. 상기 제1 포토레지스트 패턴(12)을 마스크로 하여 P형의 불순물을 고에너지로 이온주입하여 리토로그레이드 P웰(2)을 형성한다. 계속해서, 소자분리 특성을 강화시키기 위해 P형의 불순물로 필드 이온주입을 실시한 후, N형 모스 트랜지스터의 문턱전압(threshold voltage : 이하 Vt라 한다)을 조절하기 위해 P형의 불순물로 Vt이온주입을 실시한다.Referring to FIG. 1A, the device isolation film 1 is formed on a first conductive type, for example, a P-type silicon substrate 11 by a conventional device isolation process, thereby defining active regions in which devices are to be formed. A first photoresist pattern 12 is formed to expose a region where a second conductive type, for example, an N type MOS transistor is to be formed. Using the first photoresist pattern 12 as a mask, P-type impurities are ion-implanted at a high energy to form the ritolored P-well 2. Next, field ion implantation is performed with a P-type impurity to enhance device isolation characteristics. Then, to adjust the threshold voltage (Vt) of the N-type MOS transistor, Vt ion implantation .
제1b도를 참조하면, 상기 제1 포토레지스트 패턴(12)을 제거한 후, 사진공정으로 P형의 모스 트랜지스터들이 형성될 영역을 오픈시키는 제2 포토레지스트 패턴을(3)을 형성한다. 상기 제2 포토레지스트 패턴을(3) 마스프로 하여 N형의 불순물을 고에너지로 이온주입하여 리트로그레이트 N웰(2')을 형성하고, 계속해서, 필드 이온주입 및 Vt 이온주입을 실시한다.Referring to FIG. 1B, after the first photoresist pattern 12 is removed, a second photoresist pattern 3 is formed to expose a region where P-type MOS transistors are to be formed in the photolithography process. The second photoresist pattern is masked by (3) implanting N-type impurities at high energy to form retrograde N-wells 2 ', followed by field ion implantation and Vt ion implantation.
제1c도를 참조하면, 상기 제2 포토레지스트 패턴(3)을 제거한 후, 결과물 상에 게이트절연막(10)을 형성한다. 이어서, 상기 게이트절연막(10) 상에 불순물이 도핑된폴리실리콘을 증착하고 이를 사진식각 공정으로 패터닝함으로써, 게이트전극(4)을 형성한다. 다음에, 사진공정으로 상기 P웰(2)을 오픈시키는 제3 포토레지스트 패턴(13)을 형성한 후, 상기 게이트전극(4)을 마스크로 이용하여 N형 불순물을 이온주입함으로써 N-소오스/드레인 영역(5)을 형성한다.Referring to FIG. 1C, after the second photoresist pattern 3 is removed, a gate insulating film 10 is formed on the resultant structure. Then, polysilicon doped with an impurity is deposited on the gate insulating film 10 and patterned by a photolithography process to form a gate electrode 4. Next, a third photoresist pattern 13 for opening the P-well 2 is formed in the photolithography process, and an N-type impurity is ion-implanted using the gate electrode 4 as a mask to form an N - source / Drain regions 5 are formed.
제1d도를 참조하면, 상기 제3 포토레지스트 패턴(13)을 제거한 후, 사진공정으로 상기 N웰(2')을 오픈시키는 제4 포토레지스트 패턴(14)을 형성한다. 상기 게이트전극(4)을 측벽에 스페이서(7)를 형성한다. 다음에, 사진공정으로 상기 P웰(2)을 오픈시키는 제5 포토레지스트 패턴(15)을 형성한 후, 상기 스페이서(7)를 마스크로 이용하여 N형 불순물을 이온주입함으로써 N+소오스/드레인 영역(8)을 형성한다.Referring to FIG. 1d, after the third photoresist pattern 13 is removed, a fourth photoresist pattern 14 is formed to expose the N-well 2 'by photolithography. A spacer 7 is formed on the sidewall of the gate electrode 4. Next, after forming a fifth photoresist pattern 15 for opening the P-well 2 in the photolithography process, the N-type impurity is ion-implanted using the spacer 7 as a mask to form an N + source / drain Regions 8 are formed.
제1f도를 참조하면, 상기 제5 포토레지스트 패턴(15)을 제거한 후, 사진공정으로 상기 N웰(2')을 오픈시키는 제6 포토레지스트 패턴(16)을 형성한다. 상기 스페이서(7)를 마스크로 이용하여 P형 불순물을 이온주입함으로써 P+소오스/드레인 영역(9)을 형성한다. 상기한 공정들의 결과로 N형 및 P형 모스 트랜지스터들이 완성된다.Referring to FIG. 1F, after the fifth photoresist pattern 15 is removed, a sixth photoresist pattern 16 is formed to expose the N-well 2 'by photolithography. The P + source / drain region 9 is formed by ion implantation of the P-type impurity using the spacer 7 as a mask. As a result of the above processes, N-type and P-type MOS transistors are completed.
상술한 종래방법에 의하면, 실리콘기판을 도핑하는 단계가 트랜지스터를 형성하는 단계까지 총 6단계로 되어 있어, 각 단계에서의 실리콘기판의 도핑 정도를 콘트롤하여야 한다. 또한, 각 도핑 단계 사이에 다른 공정들(확산, 증착, 식각 등)이 수행되므로, 이온주입의 영향을 정확히 평가할 수 없다는 단점이 있다.According to the above-described conventional method, the doping of the silicon substrate is performed in six steps up to the step of forming the transistor, and the degree of doping of the silicon substrate in each step must be controlled. Further, since different processes (diffusion, deposition, etching, etc.) are performed between the respective doping steps, the influence of ion implantation can not be accurately evaluated.
따라서, 본 발명의 목적은 공정 단순화를 도모하고 소자에 대한 이온주입의 영향을 확실하게 모니터링할 수 있는 반도체장치의 제조방법을 제공하는데 있다.It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device capable of simplifying the process and monitoring the influence of ion implantation on the device with certainty.
본 발명의 다른 모적은 상기 반도체장치의 제조방법에 의해 제조되는 반도체장치의 구조를 제공하는데 있다.Another aspect of the present invention is to provide a structure of a semiconductor device manufactured by the method for manufacturing a semiconductor device.
상기 목적을 달성하기 위하여 본 발명은, 제1 도전형의 불순물이 도핑된 반도체기판 상에 게이트절연막 및 게이트전극을 순차적으로 형성하는 단계, 상기 게이트전극의 측벽에 절연물질로 이루어진 스페이서를 형성하는 단계, 사진공정으로 제1 도전형 또는 그 반대의 제2 도전형의 모스 트랜지스터가 형성될 영역을 오픈시키는 단계, 및 상기 오픈된 영역에, 상기 스페이서를 마스크로 이요하여 제1 도전형 또는 제2 도전형의 제1 불순물로 웰 이온주입을 실시하고, 제1 도전형 또는 제2 도전형의 제2 불순물로 소오스/드레인 이온주입을 실시하는 단계를 구비하는 것을 특징으로 하는 반도체장치의 제조방법을 제공한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: sequentially forming a gate insulating film and a gate electrode on a semiconductor substrate doped with an impurity of a first conductivity type; forming a spacer made of an insulating material on a sidewall of the gate electrode A step of opening a region where a MOS transistor of the second conductivity type of the first conductivity type or the opposite conductivity type is to be formed in the photolithography process and a step of forming a first conductivity type or a second conductivity type And performing a source / drain ion implantation with a second impurity of a first conductivity type or a second conductivity type by performing well ion implantation with a first impurity of the first conductivity type or a second conductivity type of the second conductivity type do.
본 발명의 바람직한 실시예에 의하며, 상기 웰 이온주입 및 소오스/드레인 이온주입을 실시하는 단계에서, 제1 도전형 또는 제2 도전형의 제3 불순물로 필드 이온주입을 실시하고 제1 도전형 또는 2 도전형의 제4 불순물로 문턱전압 이온주입을 실시하는 단계를 더 구비한다.According to a preferred embodiment of the present invention, in the step of performing the well ion implantation and the source / drain ion implantation, field ion implantation is performed with a third impurity of a first conductivity type or a second conductivity type, And performing a threshold voltage ion implantation with a fourth impurity of a two-conductivity type.
또한, 상기 웰 이온주입 및 소오스/드레인 이온주입을 실시하는 단계에서, 제1 도전형 또는 제2 도전형의 제5 불순물로 저농도의 소오스/드레인 이온주입을 실시하는 단계를 더 구비할 수 있다. 이때, 상기 저농도의 소오스/드레인 이온주입은 주사각을 8∼60°로 하여 실시하는 것이 바람직한다.In addition, the step of performing the well ion implantation and the source / drain ion implantation may further include the step of performing low-concentration source / drain ion implantation with the fifth impurity of the first conductivity type or the second conductivity type. At this time, it is preferable that the low-concentration source / drain ion implantation is performed with a scanning angle of 8 to 60 degrees.
상기 웰 이온주입에 의해 형성되는 도핑 프로파일은 W자형을 갖는다.The doping profile formed by the well ion implantation has a W-shape.
상기 다른 목적을 달성하기 위하여 본 발명은, 주표면을 갖는 제1 도전형의 불순물로 도핑된 반도체기판, 상기 제1 도전형 또는 그 반대의 제2 도전형의 불순물로 상기 기판의 소정영역에 도핑된 제1 웰, 및 상기 제1 웰의 주표면에 서로 이격되어 형성된 소오스 및 드레인 영역과, 상기 소오스 및 드레인 영역 사이의 기판 상에 게이트절연막을 개재하여 형성된 게이트전극을 구비하며, 상기 제1 웰은 상기 게이트전극의 하부에서는 얕게 형성되고 상기 소오스 및 드레인 영역의 하부에서는 깊게 형성됨으로써, W자형의도핑 프로파일을 갖는 것을 특징으로 하는 반도체장치의 구조를 제공한다.According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate doped with an impurity of a first conductivity type having a main surface; an impurity of a second conductivity type opposite to the first conductivity type, And a gate electrode formed on the substrate between the source and drain regions via a gate insulating film, wherein the first well and the second well are formed on the main surface of the first well, Is formed shallow at the bottom of the gate electrode and deep at the bottom of the source and drain regions to have a W-shaped doping profile.
본 발며의 바람직한 실시예에 의하면, 상기 제1 웰을 제외한 상기 기판에, 상기 제1 웰과는 반대의 도전형의 불순물로 도핑된 제2 웰을 더 구비한다. 상기 제2 웰은, 상기 제2 웰 상에 형성되는 게이트전극의 하부에서는 얕게 형성되고 소오스 및 드레인 영역의 하부에서는 깊게 형성됨으로써, W자형의 도핑 프로파일을 갖는 것이 바람직하다.According to a preferred embodiment of the present invention, the substrate other than the first well further includes a second well doped with a conductive impurity opposite to the first well. The second well may be formed shallow at the bottom of the gate electrode formed on the second well and deeply formed at the bottom of the source and drain regions to have a W-shaped doping profile.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2d도는 본 발명에 의한 반도체장치의 제조방법을 설명하기 위한 다면도들이다.FIGS. 2a to 2d are views for explaining a method of manufacturing a semiconductor device according to the present invention.
제2a도는 소자분리막(1)을 형성하는 단계를 도시한다. 제1 도전형, 예컨대 P형의 불순물이 도핑된 실리콘기판(11)상에 통상의 소자분리 공정, 예컨대 실리콘부분산화법(Local Oxidation of Silicon : LOCOS) 또는 선택적폴리실리콘산화법(Selective Polysilicon Oxidation : SEPOX) 등을 실시하여 약 3000∼5000Å의 두께의 소자분리막(1)을 형성한다. 그 결과, 모스 트랜지스터와 같은 소자들이 형성될 활성영역이 정의된다.2 (a) shows the step of forming the device isolation film 1. For example, local oxidation of silicon (LOCOS) or selective polysilicon oxidation (SEPOX) on a silicon substrate 11 doped with a first conductivity type, for example, a P type impurity, To form an element isolation film 1 having a thickness of about 3000 to 5000 ANGSTROM. As a result, an active region in which elements such as a MOS transistor are to be formed is defined.
제2b도는 게이트전극(4)을 형성하는 단계를 도시한다. 상기 실리콘기판(11)의 활성영역 상에 게이트절연막(10)을 성장시킨 후, 그 위에 도전물질, 예컨대 불순물이 도핑된 폴리실리콘을 약 2000Å 두께로 증착한다. 사진식각 공정으로 상기 폴리실리콘층 및 게이트절연막(10)을 패터닝함으로써, 게이트전극(4)을 형성한다.Figure 2b shows the step of forming the gate electrode 4. [ A gate insulating film 10 is grown on the active region of the silicon substrate 11 and a conductive material such as polysilicon doped with impurities is deposited thereon to a thickness of about 2000 Å. The gate electrode 4 is formed by patterning the polysilicon layer and the gate insulating film 10 by a photolithography process.
제2c도는 P웰 이온주입, 필드 이온주입, Vt 이온주입, N-소오스/드레인 이온주입 및 N+소오스/드레인 이온주입을 실시하는 단계를 도시한다. 상기 게이트전극(4)이 형성된 결과물 전면에 절연물질, 예컨대 산화물을 화학기상증착(chemical vapor deposition : CVD)방법으로 증착한 후 이를 이방성 식각함으로써, 상기 게이트전극(4)의 측벽에 산화물 스페이서(7)를 형성한다. 이어서, 사진공정으로 N형의 모스 트랜지스터들이 형성될 영역을 오픈시키는 제1 포토레지스트 패턴(18)을 형성한다. 노출된 상기 스페이서(7)를 마스크로 이용하여, 상기 게이트전극(4)의 두께만큼 투사범위(projected range : 이하 RP라 한다)를 보상할 수 있는 고에너지로 P형 불순물을 이온주입함으로써, 리트로그레이드 P웰(2)을 형성한다. 더 구체적으로, 첫 번째로 보론(B+)을 400keV의 에너지의 5E12/㎠의 도즈로 이온주입하고, 두 번째로 B+을 650keV의 에너지의 2E13/㎠의 도즈로 이온주입함으로써, 도핑 프로파일이 이중 피크치를 갖는 리트로그레이드 P웰(2)을 형성한다. 여기서, 첫 번째 이온주입된 영역은 소자의 특성을 좌우하며, 두 번째 이온주입된 영역은 래치업이나 소프트에러율과 같은 특성을 좌우한다.Figure 2c shows the step of performing P-well ion implantation, field ion implantation, Vt ion implantation, N - source / drain ion implantation and N + source / drain ion implantation. An insulating material such as an oxide is deposited on the entire surface of the resultant structure on which the gate electrode 4 is formed by chemical vapor deposition (CVD) and anisotropically etched to form oxide spacers 7 ). Subsequently, a first photoresist pattern 18 is formed to expose the region where the N-type MOS transistors are to be formed in the photolithography process. The P-type impurity is ion-implanted with a high energy capable of compensating for a projected range (hereinafter referred to as R P ) by the thickness of the gate electrode 4 by using the exposed spacer 7 as a mask, Thereby forming a retrograded P-well 2. More specifically, first, boron (B +) is ion-implanted at a dose of 5E12 / cm2 with an energy of 400 keV, and secondly, B + is ion- implanted at a dose of 2E13 / cm2 with an energy of 650 keV, To form a retrograded P-well 2 having a peak value. Here, the first implanted region dominates the device characteristics, and the second implanted region dominates such characteristics as latch up and soft error rate.
계속해서, 상기 스페이서(7)를 마스크로 이용하여, P형 불순물, 예컨대 B+을 140keV의 에너지와 5E12/㎠의 도즈로써 필드 이온주입을 실시하여 N형 모스 트랜지스터들의 소자분리 특성을 강화시킨 후, 다시 P형 분순물로써 N형 모스 트랜지스터의 Vt 이온주입을 실시한다.Subsequently, field ion implantation is performed using P-type impurities such as B + with an energy of 140 keV and a dose of 5E12 / cm 2 using the spacer 7 as a mask to enhance the element isolation characteristics of the N-type MOS transistors , And Vt ion implantation of the N-type MOS transistor is performed again as the P-type impurity.
계속해서, 상기 스페이서(7)를 마스크로 이용하여, N형 불순물, 예컨대 인(P)을 주사각(tilt angle)을 8∼60°로써 이온주입함으로써, N-소오스/드레인 영역(5)을 형성한다. 상기 N-소오스/드레인 영역(5)은 LDD(lightly Doped Drain) 구조를 이루는 것으로, 종래에는 주사각을 0∼7°로 하였으나 최근의 이온주입 설비로는 0∼60°까지 주사각을 줄 수 있으므로, 스페이서(7)를 고려하여 종래보다 에너지를 높이고 주사각을 크게 하여 이온주입한다.Subsequently, the N - source / drain region 5 is formed by implanting N type impurities such as phosphorus (P) at a tilt angle of 8 to 60 degrees using the spacer 7 as a mask . The N - source / drain region 5 has a lightly doped drain (LDD) structure. Conventionally, the sidewall angle is 0 to 7 degrees. However, in recent ion implantation facilities, Therefore, in consideration of the spacer 7, the energy is increased and the injection angle is increased by ion implantation.
계속해서, 상기 스페이서(7)를 마스크로 이용하여, N형 불순물, 예컨대 비소(As)를 높은 도즈로 이온주입함으로써, N+소오스/드레인 영역(8)을 형성한다.Subsequently, an N + source / drain region 8 is formed by ion-implanting N-type impurity such as arsenic (As) at a high dose using the spacer 7 as a mask.
제2d도는 N웰 이온주입, 필드 이온주입, Vt 이온주입, P-소오스/드레인 이온주입 및 P+소오스/드레인 이온주입 을 실시한 단계를 도시한다. 상기 제1 포토레지스트 패턴(18)을 제거한 후, 사진공정으로 P형의 모스 트랜지스터들이 형성될 영역을 오픈시키는 제2 포토레지스트 패턴(20)을 형성한다. 노출된 상기 스페이서(7)를 마스크로 이용하여, 상기 게이트전극(4)의 두께만큼 RP를 보상할 수 있는 고에너지로 N형 불순물을 이온주입함으로써 리트로그레이드 N웰(2')을 형성한다. 이때, 상기 N웰(2') 역시 P웰(2)과 마찬가지로 이중 피크치의 도핑 프로파일을 갖도록 형성한다.2d shows the steps performed by N well ion implantation, field ion implantation, Vt ion implantation, P - source / drain ion implantation and P + source / drain ion implantation. After the first photoresist pattern 18 is removed, a second photoresist pattern 20 is formed to expose a region where P-type MOS transistors are to be formed in the photolithography process. By using the exposed spacers 7 as a mask, N-type impurities are ion-implanted at a high energy capable of compensating for R P by the thickness of the gate electrode 4 to form a retrograded N-well 2 ' . At this time, the N well 2 'is also formed so as to have a double peak doping profile like the P well 2.
계속해서, 상기 스페이서(7)를 마스크로 이용하여, N형 불순물, 예컨대 인으로 필드 이온주입을 실시하여 P형 모스 트랜지스터들의 소자분리 특성을 강화시킨 후, P형 모스 트랜지스터의 Vt 이온주입을 실시한다.Subsequently, field ion implantation is performed with an N-type impurity, for example, phosphorus using the spacer 7 as a mask to enhance the element isolation characteristics of the P-type MOS transistors, and then Vt ion implantation of the P-type MOS transistor is performed do.
계속해서, 상기 스페이서(7)를 마스크로 이용하여 P형 불순물을 주사각을 8∼60°로써 이온주입함으로써, P-소오스/드레인 영역(6)을 형성한다. 상기 P-소오스/드렌인 영역(6) 역시 스페이서(7)를 고려하여 종래보다 에너지를 높이고 주사각을 크게 하 하여 이온주입한다.Subsequently, the P-type impurity is ion-implanted at a scanning angle of 8 to 60 degrees using the spacer 7 as a mask to form a P - source / drain region 6. The P - source / drain region 6 is also ion-implanted in consideration of the spacer 7 by increasing the energy and increasing the pouring angle.
계속해서, 상기 스페이서(7)를 마스크로 이용하여 P형 불순물을 높은 도즈로 이온주입함으로써, P+소오스/드레인 영역(9)을 형성한다.Then, the P + source / drain region 9 is formed by ion-implanting the P-type impurity at a high dose using the spacer 7 as a mask.
제3a도 및 제3b도는 종래방법 및 본 발명에 의해 제조된 반도체장치의 웰 도핑 프로파일을 나타내는 단면도이다.3a and 3b are cross-sectional views showing the well doping profile of the semiconductor device manufactured by the conventional method and the present invention.
제3a도와 제3b도를 비교하면, 본 발명에 의한 웰 도핑 프로파일은 소오스/드레인 영역의 하부에서 종래방법보다 깊게 형성되고 도핑 농도도 높다 (B 참조). 따라서, 소오소/드레인 영역에서 실리콘기판(11)으로의 누설전류가 작아진다. 또한, 본 발명에 의한 웰 도핑 프로파일은 게이트전극의 하부에서 종래방법보다 얕게 형성되어, 게이트전압의 인가시 채널을 더 용이하게 유도할 수 있다 (A 참조).Comparing Figures 3a and 3b, the well doping profile of the present invention is deeper than the conventional method at the bottom of the source / drain region and has a higher doping concentration (see B). Therefore, the leak current to the silicon substrate 11 in the source / drain region is reduced. In addition, the well doping profile according to the present invention is formed shallower than the conventional method in the lower portion of the gate electrode, so that the channel can be more easily induced when the gate voltage is applied (see A).
상술한 바와 같이 본 발명에 의하면, 게이트전극의 형성 후, 상기 게이트전극의 두께만큼 RP를 보상하는 에너지를 선택하여 웰, 필드, Vt, 및 소오스/드레인 이온주입을 실시한다. 따라서, 종래방법보다 공정이 단순화되어 공정시간이 훨씬 감소된다. 또한, 이온주입 단계들 사이에 어떠한 공정들(확산, 증착, 식각 등)도 포함되지 않으므로, 소자에 대한 이온주입의 영향을 확실하게 모니터링할 수 있다.As described above, according to the present invention, after the formation of the gate electrode, energy for compensating for R P by the thickness of the gate electrode is selected to perform well, field, Vt, and source / drain ion implantation. Thus, the process is simplified compared to the conventional method, and the process time is greatly reduced. In addition, since any processes (diffusion, deposition, etching, etc.) are not included between the ion implantation steps, the influence of ion implantation on the element can be reliably monitored.
특히, 본 발명에 의해 도핑된 웰은 게이트전극의 두께와 소오스/ 드레인 영역의 단차 차이로 인하여 자기정렬된 도핑층을 갖기 때문에, 게이트 인가전압이 낮은 저전압 구동 트랜지스터의 경우에도 채널 형성이 용이하다. 또한, 소오스/드레인 영역의 하부에서 높은 도핑 농도가 깊은 도핑층을 갖기 때문에, 소오스/드레인 영역으로부터 실리콘기판으로의 누설전류를 감소시키고 래치업 및 소프트에러율 등을 감소시키는데 더 큰 효과를 얻을 수 있다.In particular, since the wells doped by the present invention have a self-aligned doping layer due to the difference in thickness between the gate electrode and the source / drain regions, channel formation is easy even in the case of a low-voltage driving transistor having a low gate-applying voltage. In addition, since the high doping concentration at the bottom of the source / drain region has a deep doping layer, a greater effect can be obtained in reducing leakage current from the source / drain region to the silicon substrate and reducing latch up and soft error rate and the like .
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당분야에서 통상의 가진 자에 의하여 가능함은 명백하다.It is apparent that the present invention is not limited to the above embodiments, and many modifications are possible within the technical scope of the present invention by those skilled in the art.
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