KR0151081B1 - Method of fabricating semiconductor device - Google Patents

Abstract

A novel method of manufacturing a semiconductor device is disclosed. A gate insulating film, a gate conductive layer, and a first insulating film are sequentially formed on the semiconductor substrate. The gate insulating layer is formed by patterning the first insulating layer and the gate conductive layer by a photolithography process. After implanting the first impurity on the entire surface of the resultant, a second insulating film is formed on the entire surface. A portion of the second insulating film is anisotropically etched to form a spacer on the sidewall of the gate electrode, and a portion of the second insulating film is also left on the substrate. The second impurity is ion-implanted on the entire surface of the resultant to form a high concentration junction region, and then the planarization film is deposited on the entire surface. Due to the insulating film remaining on the junction region, it is possible to prevent the diffusion of impurities from the planarization film into the junction region and to form a shallow junction easily.

Description

Manufacturing Method of Semiconductor Device

1A to 1F are cross-sectional views illustrating a conventional method for manufacturing an LDD MOS transistor.

2A and 2B are graphs showing doping profiles according to depths of junction regions in conventional LDD type MOS transistors and SD type MOS transistors, respectively.

3A and 3B are cross-sectional views for explaining a method of forming a planarization film and metal wiring in a manufacturing process of a conventional LDD type CMOS device.

4 is a cross-sectional view for explaining a further insulating film stacking process in a conventional LDD type CMOS device.

5A to 5E are cross-sectional views for explaining a method for manufacturing an LDD type CMOS device according to the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 active region

4 inactive region 6 gate insulating film

8 gate electrode 10 first insulating film

13a: spacer 13: second insulating film

13b: impurity diffusion preventing layer 14: planarization film

15: contact window 16: metal wiring

17: third insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device capable of preventing diffusion of impurities from a planarization film and forming a shallow junction in a LDD (Lightly Doped Drain) CMOS device manufacturing process. It relates to a manufacturing method.

As the degree of integration of semiconductor integrated circuits increases, not only the device size but also the vertical scale down is required. The most important of the reductions in the vertical structure is the reduction in the junction depth. For example, in a MOS device having a channel length of 0.8 mu m or less, sufficient source / drain junction depth should be 0.25 mu m or less to ensure sufficient device operation.

As a conventional method of forming a shallow junction, the method of ion implantation and annealing has been most used. In the case of NMOS transistors having N ⁺ junctions, it is easy to form very shallow junctions because arsenic (As) has a very small projected range (hereinafter referred to as Rp) at an energy of 75 keV to about 0.05 μm. On the other hand, in the case of the PMOS transistor having a P ⁺ junction, since the boron (B) is very light, the diffusion coefficient is large, so that a source / drain junction deeper than that of the NMOS transistor is formed even in the same heat treatment. In particular, when the boron is ion implanted at room temperature, since the surface of the substrate is difficult to form amorphous silicon, the ion is deeply implanted due to the tail due to channeling phenomenon during ion implantation. Due to these problems, efforts have been steadily studied to form shallow junctions in sub-micron device manufacturing processes.

Submicron devices are commonly used in high-density (VLSI) circuits. In these submicron devices, the internal electric field during operation tends to be large and the signal to be handled tends to be small. it's difficult. In particular, phenomena related to reliability such as breakdown of the gate insulating film, variations in device characteristics due to hot carrier injection, and soft-error due to α-rays may limit the limit of the submicron device. As a phenomenon, many researchers have elucidated and solved the phenomenon. One of the most representative measures to counteract variations in device characteristics due to hot-carrier injection is the LDD structure.

1A to 1F are cross-sectional views illustrating a manufacturing method of a conventional LDD type MOS transistor. (Reference: IEEE Trans. Electron Device, 1980, ED-27, p. 1359, S, Ogura) Etc).

Referring to FIG. 1A, a gate insulating film 6, a polysilicon layer 8 ', and a second insulating film are formed on a semiconductor substrate 1 divided into an active region 2 and an inactive region 4 by a conventional device isolation process. One insulating film 10 is formed in sequence.

Referring to FIG. 1B, a gate electrode 8 is formed by etching the first insulating layer 10 and the polysilicon layer 8 ′ through a photolithography process.

Referring to FIG. 1C, an N ^- type source / drain is formed on the surface of the substrate on both sides of the gate electrode 8 by ion implantation of low concentration N-type impurities on the entire surface of the resultant product.

Referring to FIG. 1d, a second insulating layer 13 is formed on the entire surface of the resultant product.

Referring to FIG. 1E, the spacer 13a is formed on the sidewall of the gate electrode 8 by anisotropically etching the second insulating layer 13.

Referring to FIG. 1f, by using the spacer 13a as an ion implantation mask, ion implantation of more N-type impurities than the amount of N ⁻ -type impurities formed in FIG. 1c provides a constant from the spacer 13a. The active region is formed of N ⁺ type source / drain.

In the above-described MOS transistor of the LDD structure, the drain is formed by two ion implantation holes. That is, the first is ion implantation for the portion self-aligned by the gate electrode, and the second is ion implantation for the portion self-aligned by the spacer. At this time, since the amount of impurities during the first ion implantation is small, the electric field is reduced by 30 to 40%, thereby reducing the gate current caused by hot electrons. The second ion implantation is an ion implantation into a region self-aligned by a spacer on the sidewall of the gate electrode. Since the actual junction region is determined by the ion implantation, it is very important to set the spacer length. In general, as shown in FIG. 1E, a spacer is formed by anisotropically etching the second insulating layer stacked on the front surface so that the spacer is formed only on the sidewall of the gate electrode. Accordingly, the length of the spacer is determined by the thickness of the stacked second insulating film. Typically, the thickness of the second insulating film is about 1000 GPa to 2000 GPa, and the length of the spacer is almost equal to the thickness of the stacked second insulating film.

2A and 2B are graphs showing doping profiles according to depths of junction regions in conventional LDD type MOS transistors and single drain type MOS transistors, respectively.

2A and 2B, the bonding depth is about 0.45 mu m in the most common SD structure, while the bonding depth is about 0.4 mu m in the LDD structure. At this time, the length of the spacer in the LDD structure is about 0.3㎛.

In the manufacturing process of the LDD type CMOS device forming the junction by the above-described method, after forming the gate electrode, the spacer, the junction region, etc., the contact window and the wiring process for interconnection are performed. In this case, in order to facilitate the wiring process, the gate electrode, the junction region and the other conductive layer, and an insulating film such as borophosphosilicate glass (BPSG) are used to insulate the insulating role as well as the planarization function simultaneously.

3A and 3B are cross-sectional views for explaining a method of forming a planarization film and metal wiring in a manufacturing process of a conventional LDD type CMOS device.

Referring to FIG. 3A, the processes described with reference to FIGS. 1A through 1F are performed in the same manner to complete the LDD type MOS transistor, and then the planarization film 14 is deposited on the entire surface of the resultant. In this case, the planarization film 14 generally uses a film quality such as photophosilicate glass (PSG) or BPSG. After the planarization film 14 is deposited, heat treatment is performed at a high temperature of 800 ° C. or higher to flow it.

Referring to FIG. 3B, the planarization layer 14 is etched through a photolithography process to form a contact window 15 exposing the source / drain regions, and then a metal layer is deposited on the entire surface of the resultant. Subsequently, the metal layer 16 is formed by patterning the metal layer by a photolithography process.

When the manufacturing process of the LDD type CMOS device as described above is applied to the process of the actual integrated circuit, there are the following problems.

First, there is a problem that impurities contained in the planarization film are diffused into the junction region. In the manufacturing process of the LDD type CMOS device, after forming a transistor, an insulating film for insulation and planarization is formed on the entire surface of the resultant. PSG or BPSG is used as the planarization film, and the resultant is infiltrated and flowed by high temperature heat treatment of 800 ° C or higher. Planarize. At this time, boron included in the BPSG, phosphorus (P) contained in the PSG, and the like are diffused into the junction region during the high temperature heat treatment, and the impurity concentration required as the junction region is changed. Accordingly, the sheet resistance of the junction region is increased or the line resistance of the other wirings is increased, which has a fatal adverse effect on the device.

Second, there is a problem that the process is added. That is, in order to solve the first problem described above, another third insulating film (reference numeral 17 of FIG. 4) is inserted between the junction region and the planarization film to prevent the diffusion of impurities. As a result of the experiment, it can be seen that when the third insulating film is formed of a high temperature oxide film, at least 300 kW or more can be used to prevent diffusion of impurities. As such, additional work requiring a third insulating film to be formed between the junction region and the planarization film is necessary to prevent diffusion of impurities (see FIG. 4).

Fifth, it is very difficult to form shallow junctions. In other words, as the device becomes more integrated, shallower junctions are required. In the manufacturing process of the LDD transistor, since the substrate of the portion to be the junction region is exposed after the spacers are formed on the sidewall of the gate electrode, the impurities are exposed. Even when Rp is adjusted during ion implantation, it is very difficult to form a shallow junction.

Accordingly, an object of the present invention is to solve the problems of the conventional method described above, and in the manufacturing process of an LDD type CMOS device, a semiconductor device manufacturing method capable of preventing diffusion of impurities from a planarization film and forming a shallow junction can be provided. To provide.

The present invention to achieve the above object,

Sequentially forming a gate insulating film, a gate conductive layer, and a first insulating film on the semiconductor substrate;

Patterning the first insulating layer and the gate conductive layer by a photolithography process to form a gate electrode;

Ion implanting a first impurity in front of the resultant; Forming a second insulating film on the entire surface of the resultant product;

Anisotropically etching a portion of the second insulating layer to form a spacer on sidewalls of the gate electrode, and leaving a portion of the second insulating layer on the substrate;

Ion-implanting a second impurity on the entire surface of the resultant to form a high concentration junction region; And

And depositing a planarization film on the entire surface of the resultant.

The first and second insulating layers may be formed of any one of an oxide film such as a high temperature oxide film (HTO), a low temperature oxide film (LTO), PE-SiH ₄ , PE-SiN, or an oxynitride-based insulating film. The first and second insulating films are preferably formed to a thickness of about 500 to 2500 kPa.

In the anisotropic etching of the second insulating film, it is preferable to leave 300 second or more of the second insulating film on the substrate.

The planarization film is preferably formed of an oxide film containing impurities such as BPSG and PSG. After the planarization film is deposited, the planarization film is planarized by heat treatment.

The first impurity is ion implanted with a dose of 1.0E13 / cm 2 to 8.0E13 / cm 2 and energy of 30 keV to 60 keV, and the second impurity is energy of 30 keV to 120 keV with a dose of 1.0E15 / cm 2 to 8.0E15 / cm 2. It is preferable to ion implant.

In addition, to achieve the above object, the present invention comprises the steps of forming a gate insulating film, a gate conductive layer and a first insulating film on a semiconductor substrate; Patterning the first insulating layer and the gate conductive layer by a photolithography process to form a gate electrode; Ion implanting a first impurity in front of the resultant; Forming a second insulating film on the entire surface of the resultant product; Ion-implanting a second impurity on the entire surface of the resultant to form a high concentration junction region; And depositing a planarization film on the entire surface of the resultant.

According to the present invention, there is no need for an additional insulating film stacking step to prevent diffusion of impurities into the junction region, and at the same time obtaining a spacer having a desired length, the remaining insulating film does not cause deep ion implantation to form a shallow junction. Can be.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5A to 5E are cross-sectional views illustrating a method for manufacturing an LDD CMOS device according to the present invention.

5A shows the step of forming the low concentration first junction region 7. The gate insulating film 6, the first conductive layer, and the first insulating film 10 are sequentially formed on the entire surface of the semiconductor substrate 1 divided into the active region 2 and the inactive region 4 by a conventional device isolation process. Here, the gate insulating film 6 usually uses a thermal oxide film (SiO ₂ ), and is formed to a thickness of about 50 to about 200 kPa. The first conductive layer is a material to be used as a gate electrode, and typically uses polysilicon, which is doped or in-situ doped with POCL ₃ by thermal diffusion after polysilicon deposition. Polysilicon can be used. The first insulating layer 10 is to protect the gate electrode or to insulate the gate electrode from another conductive layer, and may be an oxide film by chemical vapor deposition (CVD), for example, a high temperature oxide film, a low temperature oxide film, or a plasma oxide film. Use

Subsequently, a photoresist of about 1 μm or more is applied onto the resultant and then photoresist patterning is performed to form a gate electrode. Subsequently, the gate electrode 8 is formed by anisotropically etching the first insulating layer 10 and the first conductive layer using the patterned photoresist as an etching mask. In this case, it is preferable to use Cl ₂ : SF _{6 at} about 50:20 for etching the first conductive layer, and to increase the selectivity with the gate insulating layer by using HBr after the etching is finished.

Next, after removing the photoresist, the first impurity of low concentration is ion implanted to form the first junction region 7. In this case, the first impurity is preferably ion implanted with a dose of 1.0E13 / cm 2 to 8.0E13 / cm 2 and energy of 30keV to 60keV.

5B shows the step of forming the second insulating film 13. A second insulating layer 13 is formed by depositing a material such as a material constituting the first insulating layer 10 on the entire surface of the resultant. Since the second insulating layer 13 is to be used as a spacer and an impurity diffusion preventing layer, unlike the conventional method in which the thickness is determined according to the desired spacer length, the second insulating layer 13 in the present invention is smaller than the length of the desired spacer. It must be formed to a greater thickness.

5C shows the steps of forming the spacer 13a and the impurity diffusion barrier layer 13b. The second insulating layer 13 is anisotropically etched to form an insulating film spacer 13a on the sidewall of the gate electrode 8. At this time, the second insulating layer 13 is etched so that the substrate portions other than the spacer 13a are not exposed, thereby leaving the second insulating layer on the first junction region 7 to form the impurity diffusion preventing layer 13b. Preferably, the impurity diffusion barrier layer 13b is formed at least 300 GPa.

5d shows the step of forming a high concentration of the second junction region 11. The second junction region 11 is formed by ion implanting a second impurity having a higher degree of motion than the first impurity on the entire surface of the resultant product. At this time, the LDD transistor is formed by the spacer 13a on the side wall of the gate electrode 8 as well as a shallow junction is formed by the impurity diffusion preventing layer 13b remaining on the junction region. The second impurity is preferably ion implanted with a dose of 1.0E15 cm 2 to 8.0E15 cm 2 and an energy of 30 keV to 120 keV.

FIG. 5E shows the steps of forming the planarization film 14 and the metallization wiring 16. As shown in FIG. After depositing an insulating material such as BPSG or PSG on the resultant to form a planarization film 14, the resultant is flattened by performing heat treatment at a high temperature of 800 ° C or higher. Subsequently, the planarization layer 14 is etched through a photolithography process to form a contact window 15 exposing the source / drain regions, and then a metal layer is deposited on the entire surface of the resultant. Next, the metal layer is patterned by the photolithography process to form the metal wiring 16, thereby completing the manufacturing process of the LDD type CMOS device.

Although not shown, according to another preferred embodiment of the present invention, the second impurity of high concentration can be ion-implanted in a state where the second insulating film is stacked as it is without performing spacer etching in the step of FIG. 4C.

Therefore, according to the method of manufacturing the semiconductor device according to the present invention as described above, the following effects can be obtained.

First, even after the process of forming the LDD transistor is completed, even if the planarization layer is directly stacked without additional processes, diffusion of impurities can be easily prevented. That is, when forming the spacer on the sidewall of the gate electrode, the spacer insulating film is left at least 300 mW over the junction region, thereby preventing the diffusion of impurities into the junction region during the subsequent planarization film process.

Second, shallow junctions can be easily formed without further processing. That is, since the insulating film for spacers remains at a predetermined thickness at the site where the impurity for bonding is to be ion implanted, the Rp control for shallow lowering during ion implantation becomes very easy.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (8)

Sequentially forming a gate insulating film, a gate conductive layer, and a first insulating film on the semiconductor substrate; Patterning the first insulating layer and the gate conductive layer by a photolithography process to form a gate electrode; Ion implanting a first impurity in front of the resultant; Forming a second insulating film on the entire surface of the resultant product; Anisotropically etching a portion of the second insulating layer to form a spacer on sidewalls of the gate electrode, and leaving a portion of the second insulating layer on the substrate; Ion-implanting a second impurity on the entire surface of the resultant to form a high concentration junction region; And depositing a flattening film on the entire surface of the resultant product. The method of claim 1, wherein the first and second insulating films are formed of any one of an oxide film such as a high temperature oxide film (HTO), a low temperature oxide film (LTO), PE-SiH ₄ , PE-SiN, or an oxynitride-based insulating film. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second insulating films are formed to a thickness of about 500 kPa to about 2500 kPa. 2. The method of claim 1, wherein in the anisotropic etching of the second insulating film, a second insulating film is left on the substrate at about 300 GPa or more. The method of manufacturing a semiconductor device according to claim 1, wherein the planarization film is formed of an oxide film containing impurities such as BPSG and PSG. The method of claim 1, wherein the planarization film is infiltrated and then planarized by heat treatment. The method of claim 1, wherein the first impurity is ion implanted at a dose of 1.0E13 / cm2 to 8.0E13 / cm2 and an energy of 30 keV to 60keV, and the second impurity is 1.0E15 / cm2 to 8.0E15 / cm2. A method for manufacturing a semiconductor device, comprising ion implantation at an energy of 30 keV to 120 keV. Sequentially forming a gate insulating film, a gate conductive layer, and a first insulating film on the semiconductor substrate; Patterning the first insulating layer and the gate conductive layer by a photolithography process to form a gate electrode; Ion implanting a first impurity in front of the resultant; Forming a second impurity on the entire surface of the resultant product; Forming a junction region of high concentration by ion implanting a second impurity on the entire surface of the resultant product; And depositing a planarization film on the entire surface of the resultant product.