JPH01112763A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent increasing of junction capacitance between collector bases which is caused in a thin epitaxial layer and to realize a high cut-off frequency bi-polar transistor, by making a collector region at an extremely low impurity density between a buried layer and a section at least under an emitter region of a bi-polar transistor. CONSTITUTION:After diffusion of an n<-> well region 4 is carried out for a p-type semiconductor 1 on the surface of its epitaxial layer, a p<-> well region 5 is formed for n channel MOS FET. At this time, p-type impurity is diffused also on a region 16 which becomes at least a base of a bi-polar transistor within the n<-> well region 4 to make a p<-> well layer 16. An n-type impurity resin 16 of extremely low density is thus formed by diffusing p-type impurity in a part of the n<-> well region 4 while forming the p<-> well region 5. A base region 7 and an emitter region 8 are formed in a well region, whereon a low density region 16 is formed, to constitute a bi-polar transistor.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is a method for converting high-performance bipolar transistors into complementary MOS transistors.
The present invention relates to a semiconductor device formed on the same semiconductor substrate as a transistor.

<Prior Art> With the remarkable progress in integrated circuit technology and the advancement of methods for applying them to various electronic devices, bipolar transistors and MOS transistors are not only of a single type each, but also of both types. A Bi-CMO3 integrated circuit that takes advantage of the characteristics of transistors has been developed and is now in practical use.

FIG. 2 is a sectional view of this type of semiconductor device conventionally used. In the figure, a n-bottle buried layer 2 and a p+ buried layer 3 are formed on the surface of a PW semiconductor substrate 1, and an n-type epitaxial layer deposited on both buried layers 2.3 is formed.
- A well layer 4 and a p-well layer 5 are formed respectively. The n-well layer 4 includes a collector diffusion layer 6. A p+<- emitter layer 7 and an n-type emitter layer 8 are respectively formed to form an NPN bipolar transistor, and Un-type polysilicon is formed as an electrode on the n+ emitter layer 8. Further, a source and drain layer IO is formed in the p-well layer 5 by diffusion of n-type impurities, and a gate tffll made of polysilicon is formed on the gate oxide film.

For the NPN bipolar transistor 100 and the n-channel MOS transistor 101, the other n-well layer 4 has a source and drain 12 formed by diffusing n-type impurities, and a polysilicon layer is formed on the gate oxide film. A t7'cp channel MOS transistor is formed with a gate electrode 13 made of Bi-CMO5 on the same semiconductor substrate.
is configured.

In the bipolar transistor in the Bi-CMO3 semiconductor device described above, when forming the n-well layer 4 in the p-epitaxial layer formed overlying the male buried layer 2, the n-type impurity diffusion for forming the n-well layer is The impurity concentration is substantially uniform until the bottom surface reaches the n+ buried layer 2.

<Problems to be Solved by the Invention> The Bi-CMO5 semiconductor device with the conventional structure described above has improved latch-up resistance due to the effect of the highly doped buried layer, and has the advantages of high speed, high integration, and low power consumption. To make the most of the characteristics of a Bi-CMOS integrated circuit, a bipolar transistor with a high cutoff frequency fT (hereinafter simply referred to as fT) is required. Make it as thin as possible and call it tahes? It is important to reduce the distance of the buried layer.

However, in the conventional configuration, if the epitaxial layer is made extremely thin, the highly doped male buried layer approaches the tapase, which increases the collector-base junction capacitance more than the effect of forming the current path described above. There were drawbacks that prevented its realization.

The present invention has been proposed to improve this drawback.

Means for Solving Problems〉 ゛ The present invention provides a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate. The impurity concentration in the region is formed to be extremely low.

By having an extremely low concentration layer in the region between the tapase region and the n+ buried layer, it is possible to prevent the increase in junction capacitance between the collector and paste that occurs when the epitaxial layer is thinned, and to realize a high fT bipolar transistor. enable.

<Example> An example of the present invention will be described using FIGS. 1(a) to (c).

As shown in FIG. 1(a), n-type impurities such as antimony and arsenic are diffused at a high concentration in a region 2 of a P-type semiconductor substrate 1 where a bipolar transistor and an n-channel MOS FET are planned to be formed, and Channel MOS FET
An n-type impurity such as boron is diffused at a high concentration into the region 3 where the formation of the n-type impurity is planned. Embedded layer 2 formed as described above.
3, a p-epitaxial layer 15 is grown. Next, a photoresist is applied to the surface of the epitaxial layer 15, and holes are formed in the regions of the photoresist film where the bipolar transistor and hill channel MO3FET are to be formed, and n-type impurities are diffused to form the n-well region 4.
form.

The semiconductor substrate having the n-well region 4 diffused into the surface of the epitaxial layer is then used to form a p-well region 5 for an n-channel MOS FET, as shown in FIG. 1(b). At this time, n-type impurities are simultaneously diffused into at least the region 16 of the n-well region 4 which will serve as a base for the bipolar transistor.
form. In this way, p-
By diffusing the n-type impurity simultaneously with the formation of the well region 5, an n-type impurity region 16 with an extremely low concentration is formed.

In the well region where the low concentration region 16 is formed, a first
As shown in Figure (C), base diffusion and emitter diffusion are performed to form a bipolar transistor to form a space region 7 and an emitter region 8, and further, in the tower region 5, as in the conventional device, an n-channel MOS transistor,
A p-channel MOS transistor is formed in the n-well region 4 to constitute a Bi-CMO 5.

In the above embodiment, the n-low concentration region 16 is formed by diffusion of n-type impurities.
Although the structure in which the low concentration region is formed under the emitter region has been described, the low concentration region can also be formed over the entire bottom surface of the space region.

Although the figure shows an example in which diffusion from polysilicon is used for the emitter of a bipolar transistor, it can also be formed simultaneously with diffusion of the source and drain of an n-channel MO5FET. Further, the base diffusion of the bipolar transistor and the source/drain diffusion of the p-channel MO8FET may be formed simultaneously or separately.

<Effects of the Invention> As explained above, according to the present invention, it is possible to form an extremely low concentration layer between the base layer and the male buried layer of a bipolar transistor in a semiconductor device having a Bi-CMO5 structure. It is possible to prevent the increase in junction capacitance between collector layers due to thinning of the epitaxial layer, etc., making it possible to form high fT bipolar transistors, significantly expanding the scope of use of semiconductor devices, and improving the reliability of semiconductor devices. It can also improve your sexuality.

[Brief explanation of the drawing]

FIGS. 1(a) to (c)H are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional device. 1: P-type semiconductor substrate 2: N+ buried layer 3: P+ buried layer 4: Well region 5: P- well region 6
: Collector 72 pace 8: Emitter 10: Source,
Drain 12: Nance, drain 16: Low concentration area agent Patent attorney Takeshi Sugiyama (and 1 other person) Figure 1 NPN nch Pc
h 21st

Claims (1)

[Claims] 1. A second conductivity type channel MOS transistor and a bipolar transistor are formed in a first conductivity type well formed in a semiconductor substrate, and a first conductivity type channel MOS transistor is formed in the second conductivity type well. 1. A semiconductor device formed by forming a bipolar transistor, wherein the impurity concentration of at least the collector region under the emitter region of the bipolar transistor is lower than that of the first conductivity type well.