JPH03165522A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid decrease in the punch-through breakdown strength between an emitter and a collector by a method wherein an impurity layer in the same conductivity type as that of a base region is formed simultaneously with a channel stopper of a MOSFET part on the lower part of an element isolating film in contact with an emitter region. CONSTITUTION:An N channel MOSFET is composed of a gate oxide film 2, a gate electrode 3, a source drain 4 formed on a P type silicon substrate 1. Said MOSFET is isolated from an adjacent N channel MOSFET by an element isolating film 5 and a channel stopper 6 comprising, P type impurities. A vertical NPN bipolar transistor is composed of a base region 8 comprising the P type impurities formed on the surface of an N type well 7 formed in the P type silicon substrate 1, an emitter region 9 comprising N type impurities formed on the surface of the substrate 1 in the base region 8 as well as a potential leading-out part 10 of a collector. Finally, a P type impurity layer 6 in the same conductivity type as that of the base region 8 is formed simultaneously with the channel stopper 6 in the N channel MOSFET on the lower part of the element isolating film 5 in contact with the emitter region 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a MOSFET and a bipolar transistor are mixed on the same substrate.

[Prior art] Vertical NPN bipolar transistor and N-channel M
FIG. 3 shows a cross-sectional view of the structure of a conventional semiconductor device in which an OSFET and an OSFET are formed on the same substrate.

The N-channel MOSFET includes a gate oxide film 2 formed on the surface of a P-type silicon substrate 1, a gate electrode 3, a source, and a drain 4. Adjacent N-channel MOSFETs are separated from each other by an element isolation film 5 and a channel stopper 6 made of P-type impurities.

The vertical NPN bipolar transistor is formed on the surface of an N-type well 7 formed in a P-type silicon substrate 1.
Base region made of P-type impurity. Emitter region made of N-type impurity formed on the substrate surface within 8° space.9. It is constituted by a potential extraction section 10 of the collector.

The bipolar transistor has a so-called walled emitter structure in which the emitter region 9 is in contact with the element isolation film 5 for miniaturization.

[Problems to be Solved by the Invention] In the case of a walled emitter structure, the low concentration portion of the base region and the emitter region overlap, so there is a problem that the bunch-through breakdown voltage between the emitter and the collector decreases. Was.

Therefore, the present invention attempts to solve such problems, and its purpose is to form a MOSFET and a vertical bipolar transistor on one surface of a semiconductor substrate. An object of the present invention is to provide a semiconductor device in which at least a portion of an emitter region is in contact with an element isolation film, in which a bunch-through breakdown voltage between an emitter and a collector does not decrease.

[Means for Solving the Problems] A semiconductor device of the present invention includes a MOS on one surface of a semiconductor substrate.
In a semiconductor device in which a FET and a vertical bipolar transistor are formed, and at least a portion of an emitter region of the vertical bipolar transistor is in contact with an element isolation film, the element portion l in contact with the emitter region is provided.
A feature is that an impurity layer of the same conductivity type as the base region is formed at the same time as the channel stopper of the MOSFET section under the l1jIO.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a structural sectional view of a semiconductor device according to the present invention, which is a BiCMO8 structure semiconductor device in which a vertical NPN bipolar transistor having a walled emitter structure and an N-channel MO8FET are formed on the same substrate.

The N-channel MO8FET includes a gate oxide film 2 formed on the surface of a P-type silicon substrate 1, a gate electrode 3, a source, and a drain 4. Adjacent N-channel MO8FETs are separated by an element isolation film 5 and a channel stopper 6 made of P-type impurity.

The vertical NPN bipolar transistor is formed on the surface of an N-type well 7 formed in a P-type silicon substrate 1.
Base region made of P-type impurity 8. Emitter region made of N-type impurity formed on the substrate surface within the base.9. It is constituted by a potential extraction section 10 of the collector. In the lower part of the element lm1115 that the emitter region 9 is in contact with,
A P-type impurity layer 6 of the same conductivity type as the base region is formed simultaneously with the channel stopper 6 of the N-channel MO8FET section.

Next, a second embodiment of the method for manufacturing a semiconductor device of the present invention will be described.
This will be explained based on FIGS. (a) to (d).

First, as shown in FIG. 2(a), phosphorus ions are injected into the P-type silicon substrate 1 in the region where the NPN bipolar transistor is to be formed at an energy of 120 KeV at I x 10''/c.
An N-type well 2 is formed by implanting d ions.

Next, 5i021111 and silicon nitride [12] are formed on the entire surface of the substrate, and the portion where the element isolation film is to be formed is removed by etching using a resist pattern. and,
Using the silicon nitride film 12 and photoresist 13 as a mask, boron ions are applied to the isolation region between adjacent N-channel MO3FETs and the region where the emitter and base of the bipolar transistor overlap at 10"/cd to 10/c/d with an energy of 30 KeV. CD implantation is performed to form a channel stopper of the N-channel MO3FET and a P-type impurity layer 6 for increasing the bunch-through breakdown voltage between the emitter and collector of the bipolar transistor.This state is shown in FIG. 2(b).

Next, as shown in FIG. 2(C), an element isolation film 5 of about 1 μm is formed by thermal oxidation in a portion other than the silicon nitride film 12, and then the silicon nitride film is removed.

Next, as shown in FIG. 2(d), after forming the gate insulating film 2,
A base region 8 and an emitter region 9 of an NPN bipolar transistor are formed. The base region 8 is formed by IXIQz/cd implantation of boron ions at 35 KeV, and the emitter 9 is formed by implanting arsenic ions at 1×101e at 80 KeV.
/c! Il implantation is performed.

The depth of the base formed is approximately 0.3 μm, and the depth of the emitter is approximately 0.15 μm.

After that, vertical NPN bipolar transistor and N-channel MO3 are formed through the normal 0MO8 formation process.
A FET can be formed to obtain the structure of the embodiment of the invention shown in FIG.

Although this embodiment has been described for the case where the bipolar transistor is an NPN bipolar transistor, it can also be applied to the case of a PNP bipolar transistor by replacing the impurity types.

[Effects of the Invention] As described above, the present invention has a great effect in that the bunch-through breakdown voltage between the emitter and the collector does not decrease in the case of a bipolar transistor having a so-called walled emitter structure.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a semiconductor device of the present invention. FIGS. 2(a) to 2(d) are diagrams showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIG. 3 is a cross-sectional view showing the structure of a conventional semiconductor device. 1... P-type silicon substrate 2... Gate oxide film 5 ・ 6 ・ 7 ・ 8 ・ 9 ・ 10 ・ l 1 ・ 12 ・ 13 ・ Gate electrode ・ Source of N-channel MO3FET. Drain, element isolation film, P-type impurity layer, N-type well, space region, emitter region, collector electrode extraction region, 5i0211i, silicon nitride film, photoresist top

Claims (1)

[Claims] A semiconductor device in which a MOSFET and a vertical bipolar transistor are formed on one surface of a semiconductor substrate, and at least a portion of an emitter region of the vertical bipolar transistor is in contact with an element isolation film. Below the element isolation film is a MOSFET.
A semiconductor device characterized in that an impurity layer of the same conductivity type as a base region is formed simultaneously with a channel stopper of an ET section.