JPH04218972A - Fabrication of semiconductor device including dmos - Google Patents

Abstract

PURPOSE:To lower the fabrication cost and improve the reproducibility of an isolation characteristic by forming an n-type isolation well on a p-type bulk wafer, and forming a drain well on the isolation well. CONSTITUTION:An n-type isolation well 2 is formed on a p-type substrate 1 by doping an n-type impurity using an oxide film and a resist as a mask, and performing thermal diffusion after removing the resist. Then, a p-type drain well 3 is formed by doping a p-type impurity using an oxide film and a resist as a mask, and performing thermal diffusion after removing the resist. Then, after a field oxide film 8 is formed, a gate oxide film 13 is formed on a drain well 3. Then, a gate electrode 4 is formed by forming poly Si on the gate oxide film 13 and patterning the same. Then, phosphorus is doped onto the drain well 3 using the gate electrode 4 and a resist as a mask. Then, an n-type high concentration diffusion region 9 is formed by ion-implantation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to voltage regulators, motor controls,
The present invention relates to a method of manufacturing a semiconductor device including a DMOS (double diffused field effect transistor) that can be driven with high power and is used in audio amplifiers and the like.

[Summary of the Invention] A DMOS is a transistor in which a base region and a source region are formed by self-alignment using a gate electrode as a mask, and the base and region under the gate electrode function as a channel. In DMOS, the channel length is determined by the difference in lateral diffusion between the base region and the source region, so when manufactured using the same design rules, the channel length is It has the characteristics of short length, high K value, and low on-resistance, making it suitable for high-power driving. The drain region of the DMOS is composed of a low concentration well region surrounding the base region and the source region, and a high concentration diffusion region for making ohmic contact with a wiring electrode arranged on the well region. . On the other hand, since a semiconductor substrate usually has the same potential as a power supply wiring or a ground wiring, in a circuit configuration in which the drain of a DMOS and a power supply wiring or a ground wiring do not have the same potential, an epitaxial substrate is used as the semiconductor substrate, so that the drain well The semiconductor substrate was electrically isolated. In the present invention, by forming an isolation well surrounding a drain well on a semiconductor substrate,
This eliminates the need for an epitaxial substrate that is expensive to manufacture.

[Prior Art] Regarding a conventional method for manufacturing a semiconductor device including a DMOS,
This will be explained using sequential cross-sectional views of manufacturing steps shown in FIGS. 2(a) to 2(c). FIG. 2(a) shows a semiconductor device after a process in which an N-type epitaxial layer 12 is formed on a P-type substrate 11, and a P-type drain well 3 is formed by diffusion on the epitaxial layer 12 using an oxide film 7 as a mask. FIG. Next, the oxide film 7 is removed, a field oxide film 8 is formed on the epitaxial layer 12, a gate oxide film 13 is formed on the drain well 3, and a gate electrode 4 is formed on the gate oxide film 13 (see FIG. (b)). Next, an N-type base 6 is formed on the drain well 3 using the gate electrode 4 as a mask, then an N-type high concentration diffusion region 9 for taking out the base electrode is formed, and then a P-type source 5 and a drain electrode are formed. A P-type high concentration diffusion region 10 for extraction is formed (FIG. 2(c)).

[Problem to be solved by the invention] For example, when a board is electrically connected to a ground wiring, a P-type D
When forming a MOS, it is necessary to form a semiconductor device on an epitaxial wafer in which an N-type epitaxial layer is formed on a P-type substrate in order to electrically isolate a P-type substrate and a P-type drain well. There is. However, epitaxial wafers are about twice as expensive in material cost as bulk wafers in which P-type or N-type impurities are uniformly diffused. Furthermore, when using an epitaxial wafer, the thickness of the epitaxial layer, the depth of the well, and the amount of autodoping from the substrate to the epitaxial layer must be controlled with good reproducibility to prevent electrical connection between the substrate and the well. There was a problem that it had to be done.

[Means for Solving the Problems] An N-type isolation well is formed on a P-type bulk wafer, and the drain well is formed on the isolation well.

[Operation] Since no epitaxial wafer is used, manufacturing costs can be reduced. Since the separation characteristics between the drain well and the substrate are determined by the separation diffusion process, the reproducibility of the separation characteristics is improved.

[Example] An example of a method for manufacturing a semiconductor device including a DMOS according to the present invention will be described using sequential cross-sectional views of manufacturing steps shown in FIGS. 1(a) to 1(d). FIG. 1(a) After doping N-type impurities such as phosphorus on a P-type substrate 1 by ion implantation using an oxide film and a resist as a mask, and removing the resist,
FIG. 3 is a cross-sectional view of the semiconductor device after performing thermal diffusion at 1000 to 1100° C. to form an N-type isolation well 2. FIG. Next, using the oxide film and resist as a mask, a P-type inert substance such as boron is doped by ion implantation, and after removing the resist, thermal diffusion is performed at 1000 to 1200°C to form a P-type drain well. (Figure 1(b)). The ion implantation conditions are such that the phosphorus ions are implanted at an energy of 100 to 20
0 Kev, the dose amount is 1012 to 1014 cm-2, the implantation energy of the boron ions is 60 to 200 Kev,
A dose of 1012 to 1014 cm-2 is used. Another embodiment of the present invention is also possible in which the drive-in process for the phosphorus ions and the boron ions is performed simultaneously by thermal diffusion immediately after the boron ion implantation, without performing thermal diffusion immediately after the phosphorus ion implantation. Next, the oxide film 7 is removed and the field oxide film 8 is removed by LOCOS method or the like.
After forming 200 to 100
A gate oxide film 13 with a thickness of 0 Å is formed. Next, polySi with a thickness of 2000 to 5000 Å is deposited on the gate oxide film 13 by CVD.
The gate electrode 4 is formed by patterning using a photolithography method and a dry etching method (FIG. 1(c)). Next, using the gate electrode and the resist as a mask, phosphorus is doped onto the drain well by ion implantation, and thermal diffusion at 900 to 1000° C. is performed as necessary to form the base 6. Next, ion injection of phosphorus or arsenic is performed to form an N-type high concentration diffusion region 9,
Boron ions are implanted to form a source 5 and a P-type high concentration diffusion region 10 (FIG. 1(d)). The channel length of a DMOS can be controlled by the ion implantation conditions and heat treatment conditions of the base 6 and source 5, and even with a low-cost process where the minimum line width is 3 to 5 μm, which is mainly produced by photolithography, the effective channel length can be 0.5 μm. Short channel transistors as short as 5 to 1.0 μm can be formed.

[Effects of the Invention] According to the method of manufacturing a semiconductor device including a DMOS of the present invention, the drain and substrate of the DMOS can be electrically separated using a bulk wafer, which is cheaper in material cost than an epitaxial wafer, and thus manufacturing costs can be reduced. Furthermore, the isolation characteristics between the drain and the substrate can be controlled simply by the diffusion conditions of the isolation well and the drain well, making it easy to set process conditions with a large margin. In the embodiments of the present invention, a case has been described in which a P-type DMOS is formed on a P-type substrate, but even when an N-type DMOS is formed on an N-type substrate, a P-type DMOS is formed on a P-type substrate.
It is clear that the same effects as in the embodiments of the present invention can be obtained by using a type separation well.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are step-by-step cross-sectional views of a method for manufacturing a semiconductor device including a DMOS according to the present invention, and FIGS. 2(a) to (c) are
1A and 1B are step-by-step cross-sectional views of a conventional method for manufacturing a semiconductor device including a DMOS. 1... P type substrate 2... N type isolation well 3... P type drain well 4... Gate electrode 5... Source 6... Base 7... Oxide film 8... Field oxide film 9... N type high concentration diffusion region 10... P type High concentration diffusion region 11...P-type substrate 12...N-type epitaxial layer 13...Gate oxide film Applicant: Seiko Electronics Co., Ltd. Agent Patent attorney: Keinosuke Hayashi

Claims (1)

[Claims] a step of forming an isolation well region of an opposite conductivity type on a semiconductor substrate of one conductivity type; a step of forming a drain region of one conductivity type on the isolation well region separated from the semiconductor substrate; forming a base region of opposite conductivity type on the base region; forming a source region of one conductivity type on the base region; and forming a base region on the surface of the base region sandwiched between the drain region and the source region. A method of manufacturing a semiconductor device including a DMOS, comprising the step of forming a channel region.