JPH09213708A - Lateral bipolar transistor and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve withstand voltage between an emitter region and a collector region in a fine lateral bipolar transistor. SOLUTION: The lateral bipolar transistor has a conductor pattern formed on the surface of one conductive semiconductor substrate through an oxide film 8, and reverse conducting emitter region 5 and collector region 6, which are formed in self alignment for the conductor pattern. The conductor pattern exists on a base region between the emitter region and the collector region 6, and the conductor pattern is connected so that potential becomes equal to that of the emitter region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral bipolar transistor and its manufacturing method, and in particular to a BiC in which a bipolar transistor and a MOS transistor are mixed.
The present invention relates to a lateral bipolar transistor formed in a semiconductor integrated circuit called MOS.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device composed of BiCMOS, an emitter region and a collector region of a lateral bipolar transistor can be formed in a self-aligned manner (self-aligned) with a gate electrode pattern like a P channel MOS transistor.

The lateral bipolar transistor thus formed will be described with reference to FIG. FIG. 5 is a sectional view of a lateral bipolar transistor described in Japanese Patent Laid-Open No. 64-82560. As shown in FIG.
An epitaxial layer 32 having an N conductivity type is formed on the surface of a silicon substrate 31 having a P conductivity type. The region where the lateral PNP transistor (hereinafter referred to as L-PNP transistor) is formed is separated by the P-type isolation region 33 and the field oxide film 34. Then, an N-type buried layer 35 is provided below the epitaxial layer 32. The buried layer 35 is formed over the region where the emitter region 36, the collector region 37 and the base contact region 38 are provided.

On the surface of the base epitaxial layer 32, the emitter region 36 and the collector region 37 are formed by ion implantation or diffusion of P-type impurities in self-alignment with the polysilicon layer 40 formed on the oxide film 39 as a mask. Has been done. Then, the polysilicon layer 40 remains, an interlayer insulating film 41 is deposited on the polysilicon layer 40, and contact holes are formed in the emitter region 36, the collector region 37, the base contact region 38, and the polysilicon layer 40, respectively. An emitter electrode 42, a collector electrode 43, a base electrode 44 and a polysilicon layer electrode 45 which are connected through the contact holes are formed.

Of these electrodes, the base electrode 4
4 and the polysilicon layer electrode 45 are short-circuited.

According to this technique, the epitaxial layer 32 and the polysilicon layer 40, which are base regions, are held at the same potential. Then, it becomes difficult for a depletion layer to be formed in the base region between the emitter region 36 and the collector region 37.

[0007]

However, in the case of this conventional technique, since the impurity concentration of the base region is low, the breakdown voltage between the emitter region and the collector region is low, and further,
Due to the operating state of the L-PNP transistor, the suppression of the formation of the depletion layer in the base region between the emitter region 36 and the collector region 37 becomes insufficient. It appears especially when the base electrode 44 and the polysilicon layer electrode 45 change from a positive potential to 0V. This is because of the resistance of the epitaxial layer 32 including the buried layer 35, even if the base electrode 44 becomes 0 V, the emitter region 36 and the collector region 37 are temporarily provided.
This is because the potential of the base region between them remains a positive potential. Then, instantaneously, the above depletion layer is easily formed on the surface of the base region below the polysilicon layer electrode 45.

Further, in the case of this conventional technique, when a large amount of boron impurities are introduced into the polysilicon layer 40, the Fermi level of the polysilicon layer 40 is lowered. Here, the introduction of the boron impurity occurs when the P ⁺ type emitter region 36 and the collector region 37 are formed. In this case, a large internal potential is generated between the polysilicon layer 40 and the base region between the emitter region 36 and the collector region 37. Then, this internal potential facilitates the formation of the depletion layer. The formation of these depletion layers reduces the punch-through breakdown voltage between the emitter region and the collector region.

An object of the present invention is to solve the above problems,
The purpose is to completely suppress the above-mentioned depletion layer and prevent punch-through which tends to occur between the emitter region and the collector region.

[0010]

To this end, the lateral bipolar transistor of the present invention includes a conductor pattern formed on the surface of a semiconductor substrate of one conductivity type through an oxide film and a conductor pattern for the conductor pattern. It has an opposite conductivity type emitter region and a collector region formed in self-alignment,
The conductor pattern is present on the base region between the emitter region and the collector region, and the conductor pattern is connected so as to have the same potential as the emitter region.

Further, in the lateral bipolar transistor of the present invention, a base contact region is formed on the surface of the semiconductor substrate and outside the conductor pattern, the emitter region and the collector region.
A buried layer having the same conductivity type and a high concentration of impurities is formed inside the semiconductor substrate and over the entire region located under the conductor pattern, the emitter region, the collector region and the base contact region.

According to the method of manufacturing a lateral bipolar transistor of the present invention, impurity ions of the same conductivity type are selectively ion-implanted from the surface of a semiconductor substrate of one conductivity type with high acceleration energy, and a high concentration is introduced into the inside of the semiconductor substrate. A step of forming a buried layer containing impurities; a step of forming and patterning a conductor film on the surface of the semiconductor substrate via an oxide film; and a step of using the patterned conductor film as a mask to remove impurity ions of opposite conductivity type. Ion implantation to form an emitter region and a collector region on the surface of the semiconductor substrate;
Forming a base contact region by ion-implanting an impurity of the same conductivity type into a region located outside the emitter region and the collector region; and forming a base contact region on the emitter region, the collector region, the base contact region and the patterned conductor film, respectively. Forming an electrode and connecting the electrode on the emitter region and the electrode on the patterned conductor film.

When the potential of the conductor pattern becomes the same as the potential of the emitter, this potential has a function of bringing the lower base region via the oxide film of the conductor pattern into a state of carrier accumulation. Therefore, the formation of a depletion layer between the emitter region and the collector region, which is formed in self-alignment with this conductor pattern, is suppressed, and the breakdown voltage between them is improved.

[0014]

FIG. 1 shows an embodiment of the present invention.
It will be described based on. FIG. 1 shows an L-PN according to the present invention.
It is sectional drawing of a P transistor.

As shown in FIG. 1, an epitaxial layer 2 having a conductivity type of N is formed on the surface of a silicon substrate 1 having a conductivity type of P as in the prior art. Here, the film thickness of the epitaxial layer 2 is 1 to 2 μm. The impurity concentration of this layer is set to about 10 ¹⁶ atoms / cm ³ . Further, the region where the L-PNP transistor is formed is separated from the P-type isolation region (not shown) by the field oxide film 3. And the epitaxial layer 2
An N-type buried layer 4 is provided under. As shown in FIG. 1, this buried layer 4 is formed on the surface of the epitaxial layer 2 over the region where the emitter region 5, the collector region 6 and the base contact region 7 are provided.

Further, similarly to the conventional technique, the emitter region 5 and the collector region 6 are self-aligned on the surface of the epitaxial layer 2 serving as the base, using the polycide layer 9 formed on the oxide film 8 as a mask. ing. Then, the polycide layer 9 remains, and the CV is applied from above.
The D oxide film 10 is deposited, and the CVD oxide film 1 is further deposited.
0 to deposit a BPSG oxide film 11. Then, contact holes are respectively formed on the emitter region 5, the collector region 6, the base contact region 7, and the polycide layer 9, and the emitter electrode 12, the collector electrode 13, the base electrode 14, and the polycide layer electrode which are connected through the contact holes are connected. 15 is formed.

Of these electrodes, the emitter electrode 12 and the polycide layer electrode 15 are short-circuited.

In the case of the present invention, the emitter region 12 and the polycide layer 9 are held at the same potential. Then, the highest voltage of the L-PNP transistor is applied to the polycide layer 15.

Next, a method of manufacturing the lateral bipolar transistor having the structure of the present invention will be described with reference to FIGS. 2 and 3 are cross-sectional views in the order of manufacturing steps of the L-PNP transistor described in the above embodiment.

As shown in FIG. 2A, after the N-conductivity type epitaxial layer 2 is formed on the surface of the P-conductivity type silicon substrate 1, phosphorus ions are implanted by using the mask 16 as an ion implantation mask and heat treatment is applied. To form the buried layer 4. Here, the film thickness of the epitaxial layer 2 is set to 1.5 μm, and the concentration of the N-type impurity is set to 5 × 10 ¹⁶ atoms / cm ³ . Further, in the ion implantation of phosphorus impurities, the acceleration energy of phosphorus of divalent ions is set to 500 keV and the dose amount of ions is set to 5 × 10 ¹⁴ ions / cm ² .

Next, the mask 16 is removed, and as shown in FIG. 2B, the field oxide film 3 is formed by the known LOCOS method.
Then, an oxide film 8 is formed on the surface of the epitaxial layer 2 by thermal oxidation. Here, the thickness of the oxide film 8 is about 20 nm. And, the film thickness including phosphorus impurities 1
A polysilicon layer having a thickness of 00 nm and a tungsten silicide layer having a thickness of 200 nm are stacked and deposited, and patterned by a known photolithography technique and dry etching technique to form a polycide layer 9.

Next, as shown in FIG. 2C, a resist mask 17 is formed by a known photolithography technique,
Using this as a mask, boron ions 18 are implanted. Here, the implantation energy is 20 keV and the dose is 1 × 10 ¹⁵ ions / cm ² . Thus, the emitter region 5 and the collector region 6 are formed on the surface of the epitaxial layer 2 in self alignment with the polycide layer 9 and the field oxide film 3.

Next, after removing the resist mask 17,
As shown in FIG. 3A, a resist mask 19 is formed by a known photolithography technique. Then, using this as a mask, arsenic ions 20 are implanted. Here, the implantation energy is 50 keV and the dose is 5 × 10 5.
^{It is 15} ions / cm ² . In this way, the base contact region 7 is formed in the field oxide film 3 on the surface of the epitaxial layer 2 in a self-aligned manner.

Next, after removing the resist mask 19,
As shown in FIG. 3B, a CV having a film thickness of about 100 nm
A D oxide film 10 is deposited, and a BPSG oxide film 11 having a film thickness of about 500 nm is further deposited. And 900 ℃
A heat treatment is performed for about 20 minutes to activate boron and arsenic introduced by ion implantation and reflow the BPSG oxide film 11. Here, the CVD oxide film 10 is formed by chemical vapor deposition (C
VD) is a silicon oxide film formed by the BPSG method.
The oxide film 11 is a silicon oxide film containing boron glass and phosphorus glass formed by a CVD method.

Then, contact holes are respectively formed in the CVD oxide film 10 and the BPSG oxide film 11 on the emitter region 5, the collector region 6, the base contact region 7, and the polycide layer 9, and the emitter electrodes connected through the respective contact holes. 12, collector electrode 13, base electrode 14 and polycide layer electrode 15 are formed.
Further, among these electrodes, the emitter electrode 12 and the polycide layer electrode 15 are short-circuited, and the L electrode of the present invention described in FIG.
-The PNP transistor is completed.

Next, the effect of using the lateral bipolar transistor of the present invention in a semiconductor integrated circuit will be described with reference to FIG. FIG. 4 shows resistors 21 and 21.
a, load PNP transistors 22 and 22a, drive P
It is a part of a circuit composed of NP transistors 23 and 23a, an input terminal 24, and an output terminal 25. In such a circuit, when the small signal applied to the input terminal 24 falls from a high positive voltage value to a low positive voltage value, that is, the driving PNP.
When transistors 23 and 23a change from a non-conducting state to a conducting state, output terminal 25 drops from a high positive voltage, eg 5V, to a low voltage near 0V. Then, at this time, the potentials of the bases of the load PNP transistors 22 and 22a also decrease from a high voltage to a low voltage close to 0V.

In such a transient state where the voltage changes,
In the case of the conventional technique, since the polysilicon layer 45 is connected to the base electrode 44, as described in the problem to be solved by the invention described above, the polysilicon layer 45 is located in the base region of the load PNP transistors 22 and 22a. Potential difference occurs,
A depletion layer is easily formed between the collector region and the base region. Then, when the base width becomes narrower due to the miniaturization of the semiconductor element, punch-through occurs between the emitter region and the collector region.

On the other hand, in the case of the present invention, the polycide layer 9 described above is connected to the emitter electrode having the highest positive voltage. It works to suppress the formation of depletion layers.

Therefore, in the case of the present invention, a sufficient breakdown voltage can be obtained between the emitter region and the collector region even when the semiconductor element becomes fine and the base width becomes small.

In the embodiment of the present invention described above,
Although the case where the polycide layer is formed on the base region via the oxide film has been described, it should be noted that the polycide layer may be formed of another conductive material such as a refractory metal.

In the embodiment of the present invention, the L-PNP is used.
Although the case where the transistor is formed in the epitaxial layer has been described, the L-PNP transistor may be formed in the well layer on the surface of the silicon substrate.

Further, the present invention relates to L described in the embodiment.
-Not limited to PNP transistors, but L-NP
The N-transistor is similarly formed. And LP
The same effect as described for the NP transistor can be obtained. In this case, the conductivity type impurity opposite to that used in the embodiment is used in forming the transistor.

[0033]

As described above, according to the present invention, a lateral bipolar transistor has an emitter region and a collector region which are formed in self alignment in a polycide layer patterned into a gate electrode shape,
The polycide layer and the emitter region are electrically connected so that they have the same potential.

Therefore, no matter what the operating state of the lateral bipolar transistor is, the depletion layer formed between the emitter region and the collector region is suppressed, and punch-through between them is also suppressed. As a result, the breakdown voltage between the emitter region and the collector region is improved.

Furthermore, the problems that occur in the case of the prior art,
That is, when a large amount of boron impurities are introduced into the polysilicon layer 40, the Fermi level of the polysilicon layer 40 decreases. In this case, a large internal potential is generated between the polysilicon layer 40 and the base region between the emitter region 36 and the collector region 37. And this internal potential is
There is no problem of facilitating the formation of the depletion layer and lowering the breakdown voltage of the emitter region and the collector region.

As described above, the present invention completely suppresses the depletion layer as described above, prevents punch-through that tends to occur between the emitter region and the collector region, and suppresses the reduction in breakdown voltage. Then, miniaturization of the lateral bipolar transistor is promoted.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a lateral bipolar transistor of the present invention.

2A to 2D are cross-sectional views in the manufacturing process order of the lateral bipolar transistor of the present invention.

FIG. 3 is a cross-sectional view in the manufacturing process order of the lateral bipolar transistor of the present invention.

FIG. 4 is a circuit diagram for explaining an effect of the present invention.

FIG. 5 is a cross-sectional view of a bipolar transistor for explaining a conventional technique.

[Explanation of symbols]

 1,31 Silicon substrate 2,32 Epitaxial layer 3,34 Field oxide film 4,35 Buried layer 5,36 Emitter region 6,37 Collector region 7,38 Base contact region 8,39 Oxide film 9 Polycide layer 10 CVD oxide film 11 BPSG oxide film 12,42 Emitter electrode 13,43 Collector electrode 14,44 Base electrode 15 Polycide layer electrode 16 Mask 17,19 Resist mask 18 Boron ion 20 Arsenic ion 21 Resistor 22,22a Load PNP transistor 23,23a Driving PNP Transistor 24 Input terminal 25 Output terminal 33 P-type isolation region 40 Polysilicon layer 41 Interlayer insulating film 45 Polysilicon layer electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 27/082

Claims (3)

[Claims] 1. A conductive pattern formed on a surface of a semiconductor substrate of one conductivity type via an oxide film, and an emitter region and a collector region of opposite conductivity type formed in self-alignment with the conductive pattern. And the conductor pattern is present on the base region between the emitter region and the collector region, and the conductor pattern is connected so as to have the same potential as the emitter region. Lateral bipolar transistor. 2. A base contact region is formed on the surface of the semiconductor substrate and outside the conductor pattern, the emitter region and the collector region, and further inside the semiconductor substrate, the conductor 2. The lateral bipolar transistor according to claim 1, wherein a buried layer having the same conductivity type and a high concentration of impurities is formed over the entire region located below the pattern, the emitter region, the collector region and the base contact region. 3. A step of selectively implanting impurity ions of the same conductivity type with high acceleration energy from the surface of a semiconductor substrate of one conductivity type to form a buried layer having a high concentration of impurities inside the semiconductor substrate. A step of forming and patterning a conductor film on the surface of the semiconductor substrate via an oxide film, and impurity ions of the opposite conductivity type are ion-implanted using the patterned conductor film as a mask to the surface of the semiconductor substrate. Forming an emitter region and a collector region,
Forming a base contact region by ion-implanting an impurity of the same conductivity type into a region located outside the emitter region and the collector region; and forming a base contact region on the emitter region, the collector region, the base contact region and the patterned conductor film, respectively. Forming an electrode and connecting the electrode on the emitter region to the electrode on the patterned conductor film, a method for manufacturing a lateral bipolar transistor.