JPH03198349A - Manufacture of mos type semiconductor device - Google Patents
Manufacture of mos type semiconductor deviceInfo
- Publication number
- JPH03198349A JPH03198349A JP1336456A JP33645689A JPH03198349A JP H03198349 A JPH03198349 A JP H03198349A JP 1336456 A JP1336456 A JP 1336456A JP 33645689 A JP33645689 A JP 33645689A JP H03198349 A JPH03198349 A JP H03198349A
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate electrode
- oxide film
- ion
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- -1 oxygen ions Chemical class 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 12
- 229920005591 polysilicon Polymers 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000000059 patterning Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はＬＤＤ構造のＭＯ３型半導体装置、特にＬＤＤ
構造のｌＩＯ３型電界効果トランジスタの製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an MO3 type semiconductor device having an LDD structure, particularly an LDD
The present invention relates to a method of manufacturing an IIO3 type field effect transistor having the structure.
（従来の技術）
ＭＯ３型電界効果トランジスタにおいて、ソース・ドレ
イン間の耐圧の低下やホットキャリア注入による長期信
頼性の低下といった種々の問題を解決するためにドレイ
ン近傍における電界を緩和して衝突電離によるホットキ
ャリアの低減を図るために電界効果トランジスタのゲー
ト電極に最も近いドレイン領域部分の不純物濃度を低く
したいわゆる低濃度ドレイ７（Ｌｉｇｈｔｌｙ Ｄｏｐ
ｅｄ Ｄｒａｉｎ）構造（以下ＬＤＤ構造と称する）の
ものが開発されている。(Prior art) In MO3 type field effect transistors, in order to solve various problems such as a decrease in breakdown voltage between the source and drain and a decrease in long-term reliability due to hot carrier injection, the electric field near the drain is relaxed to prevent impact ionization. In order to reduce hot carriers, the so-called Lightly Dop 7 has a lower impurity concentration in the drain region closest to the gate electrode of the field effect transistor.
ed drain structure (hereinafter referred to as LDD structure) has been developed.
例えば、第２図（ａ）〜第２図（ｄ）に示すように、シ
リコン基板１の表面にゲート酸化膜３を設け、その上に
ゲート電極を構成するためのポリシリコン４を全面に設
け、次いでパターニングを施してゲート電極４を構成す
る。その後上面から燐（Ｐつをイオン注入してＮ−領域
２を形成する（第２図（ａ）参照）。For example, as shown in FIGS. 2(a) to 2(d), a gate oxide film 3 is provided on the surface of a silicon substrate 1, and polysilicon 4 for forming a gate electrode is provided on the entire surface. Then, patterning is performed to form the gate electrode 4. Thereafter, phosphorus (P) is ion-implanted from the top surface to form an N- region 2 (see FIG. 2(a)).
次に、第２図（ｂ）に示すように、表面全体に酸化膜６
を成長させ、その後第２図（ｃ）に示すように、上面か
ら等方性エツチングを施してゲート電極の両側にサイド
ウオール７を残存させるようにする。 最後に、第２図
（ｄ）に示すように、上記サイドウオール７をマスクと
して用いて半導体全体の上面から砒素（Ａｓ−）をイオ
ン注入してシリコン基板１内にＮ十領域８を形成し得る
ようにする。Next, as shown in FIG. 2(b), an oxide film 6 is formed over the entire surface.
Then, as shown in FIG. 2(c), isotropic etching is performed from the top surface to leave sidewalls 7 on both sides of the gate electrode. Finally, as shown in FIG. 2(d), arsenic (As-) is ion-implanted from the top surface of the entire semiconductor using the sidewall 7 as a mask to form an N0 region 8 in the silicon substrate 1. Try to get it.
この種ＬＤＤ構造のＭＯＳ型電界効果トランジスタでは
、ソース側のＮ−領域が寄生抵抗として寄与し、実効相
互コンダクタンスが低下するようになる。In a MOS field effect transistor having this type of LDD structure, the N- region on the source side contributes as a parasitic resistance, resulting in a decrease in effective mutual conductance.
かかる欠点を回避する方法として特開昭６０−５７９６
９号公報に記載されたものがある。As a method to avoid such drawbacks, Japanese Patent Application Laid-Open No. 60-5796
There is one described in Publication No. 9.
即ち、第３図（ａ）〜第３図（ｆ）に示すように、従来
の半導体装置の製造方法により製造したＭＯ３型電界効
果トランジスタにおいては、シリコン基板１１上に熱処
理により酸化膜１２を設け、その上にポリシリコンを設
けてバターニング処理を施してゲート電極１３を構成し
、更にその上全体に窒化膜４を設ける（第３図（ａ）参
照）。That is, as shown in FIGS. 3(a) to 3(f), in the MO3 field effect transistor manufactured by the conventional semiconductor device manufacturing method, an oxide film 12 is formed on a silicon substrate 11 by heat treatment. , polysilicon is provided thereon and subjected to a buttering process to form the gate electrode 13, and a nitride film 4 is further provided on the entire surface thereof (see FIG. 3(a)).
次に、この窒化膜１４に対し、第３図（ｂ）に示すよう
にフォトレジスト２０によるパタニングを施してエツチ
ングを行い、ゲート電極１３の中心部から半導体層の片
側の上方に位置する窒化膜１４を除去する。Next, this nitride film 14 is patterned using a photoresist 20 and etched as shown in FIG. 14 is removed.
次いで、第３図（Ｃ）に示すようにシリコン基板１１の
表面に燐（Ｐ−）をイオン注入し、Ｎ−領域１６を形成
する。Next, as shown in FIG. 3C, phosphorus (P-) is ion-implanted into the surface of the silicon substrate 11 to form an N- region 16.
その後、第３（ｄ）図に示すように全体に熱処理を施し
て窒化膜１４で覆、われた領域以外の領域を酸化する。Thereafter, as shown in FIG. 3(d), the entire structure is subjected to heat treatment to oxidize the regions other than the regions covered with the nitride film 14.
この際、酸化膜１２が成長して肉厚となり、厚い酸化膜
１７を形成する。At this time, the oxide film 12 grows and becomes thick, forming a thick oxide film 17.
次いで第３図（ｅ）に示すように全体に異方性エツチン
グを施して酸化膜１７の露出している部分を前記Ｎ−領
域１６の上側の半導体層表面が露出されるまで除去して
その残存部分によりサイドウオール１８を形成する。Next, as shown in FIG. 3(e), the exposed portion of the oxide film 17 is removed by anisotropic etching until the surface of the semiconductor layer above the N- region 16 is exposed. The remaining portion forms a sidewall 18.
その後、第３図（ｆ）に示すように、等方性エツチング
を施して窒化膜１４を完全に除去し、最後に砒素（Ａｓ
−）をイオン注入してＮ＋領域１９を形成する。Thereafter, as shown in FIG. 3(f), the nitride film 14 is completely removed by isotropic etching, and finally the arsenic (As)
-) is ion-implanted to form an N+ region 19.
（発明が解決しようとする課題〕
この特開昭６０−５７９６９号公報に記載された半導体
装置は、Ｎ−領域１６を形成するために窒化膜１４をバ
ターニングする際に、マスクのアライメント誤差が生じ
るため、微細加工を行うには不所望である。(Problems to be Solved by the Invention) The semiconductor device described in Japanese Patent Laid-Open No. 60-57969 has a mask alignment error when patterning the nitride film 14 to form the N- region 16. This is undesirable for microfabrication.
本発明は上述した問題点を解決し得るように適切に配置
された上述した種類のｌＩＯ３型半導体装置の製造方法
を提供することをその目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an IIO3 type semiconductor device of the type described above, which is appropriately arranged so as to solve the problems described above.
（課題を解決するための手段）
本発明ＭＯＳ型半導体装置の製造方法は第１導電型の半
導体基体の表面にゲート酸化膜を介して半導体ゲート電
極を形成する工程と、イオン注入により第２導電型の低
濃度不純物領域を形成する工程と、酸素イオンをななめ
に注入する工程と、熱処理によりゲート電極の１部の選
択的に酸化する工程と、異方性エツチングによりサイド
ウオールを形成する工程と、イオン注入により第２導電
型の高濃度不純物領域を形成する工程とを具えることを
特徴とする。(Means for Solving the Problems) A method for manufacturing a MOS type semiconductor device of the present invention includes a step of forming a semiconductor gate electrode on the surface of a semiconductor substrate of a first conductivity type via a gate oxide film, and a step of forming a semiconductor gate electrode of a second conductivity type by ion implantation. A process of forming a low-concentration impurity region of the mold, a process of diagonally implanting oxygen ions, a process of selectively oxidizing a part of the gate electrode by heat treatment, and a process of forming sidewalls by anisotropic etching. , forming a second conductivity type high concentration impurity region by ion implantation.
（作用）
かように、本発明によれば、ポリシリコンのゲート電極
に、ななめ上方から酸素をイオン注入して酸化し、上方
からエツチングを行うだけで、マスク合せを行うことな
く、ゲート電極のサイドウオールを片方にのみ形成する
ことができ、マスクのアライメント誤差を発生させるこ
とはない。(Operation) As described above, according to the present invention, the gate electrode can be formed by simply implanting oxygen ions diagonally from above into the polysilicon gate electrode to oxidize it and then etching it from above, without performing mask alignment. The sidewall can be formed on only one side without causing mask alignment errors.
（実施例） 図面につき本発明の詳細な説明する。(Example) The invention will be explained in detail with reference to the drawings.
第１図（ａ）〜第１図（ｅ）に示すように、本発明ＭＯ
Ｓ型電界効果トランジスタでは、シリコン基板１の表面
にゲート酸化膜３を設け、その上にゲート電極を構成す
るためのポリシリコンを全面に設け、次いでバターニン
グを施してポリシリコンのゲート電極４を構成する。そ
の後上面から燐（Ｐ−）をイオン注入してＮ−領域２を
形成する（第１図（ａ）参照）。As shown in FIG. 1(a) to FIG. 1(e), the present invention MO
In an S-type field effect transistor, a gate oxide film 3 is provided on the surface of a silicon substrate 1, polysilicon for forming a gate electrode is provided on the entire surface, and then buttering is performed to form a polysilicon gate electrode 4. Configure. Thereafter, phosphorus (P-) is ion-implanted from the top surface to form an N- region 2 (see FIG. 1(a)).
次いで、第１図（ｂ）に示すように、全体のななめ上方
から酸素（０つをイオン注入してポリシリコンのゲート
電極４の上面および一方の側面に酸素注入領域５を形成
する。その後、第１図（Ｃ）に示すように全体に熱処理
を施して前記ポリシリコンのゲート電極４の一部分およ
びドレイン領域上に酸化膜６を形成する。Next, as shown in FIG. 1(b), oxygen ions are implanted diagonally above the entire structure to form an oxygen implanted region 5 on the upper surface and one side surface of the polysilicon gate electrode 4. As shown in FIG. 1C, the entire structure is subjected to heat treatment to form an oxide film 6 on a portion of the polysilicon gate electrode 4 and the drain region.
次に、第１図（ｄ）に示すように、前記ソース領域の表
面が露出されるまで上方から異方性エツチングを施して
ゲート電極４の側面にサイドウオール７を残存させるよ
うにする。Next, as shown in FIG. 1(d), anisotropic etching is performed from above until the surface of the source region is exposed, so that the sidewall 7 remains on the side surface of the gate electrode 4.
最後に、第１図（ｅ）に示すように、上方から砒素（Ａ
ｓ→をイオン注入してＮ＋領域８を形成する。Finally, as shown in Figure 1(e), arsenic (A
N+ region 8 is formed by ion implantation of s→.
その後、図示しないが、通常のように各領域に電極を設
け、カプセル封止等の実装を行ってＭＯ３型電界効果ト
ランジスタを完成する。Thereafter, although not shown, electrodes are provided in each region as usual, and packaging such as encapsulation is performed to complete the MO3 field effect transistor.
（発明の効果）
上述したように、本発明によればポリシリコンのゲート
電極に、ななめ上方から酸素をイオン注入して酸化し、
上方からエツチングを行うだけで、マスク合せを行うこ
とな（、ゲート電極のサイドウオールを片方にのみ形成
し、これを更にマスクとして用いるだけで、自己整合的
に能動領域を形成することができ、マスクのアライメン
ト誤差を発生させることはなく、半導体装置の微細加工
を良好に行うことができる。(Effects of the Invention) As described above, according to the present invention, oxygen ions are implanted diagonally from above into a polysilicon gate electrode to oxidize it.
By simply etching from above and without mask alignment (by forming the sidewall of the gate electrode on only one side and using this as a mask, the active region can be formed in a self-aligned manner. Fine processing of semiconductor devices can be performed satisfactorily without causing mask alignment errors.
第１図（ａ）〜第１図（ｅ）は本発明半導体装置の製造
方法により製造したＭＯＳ型電界効果トランジスタの種
々の製造工程を示す断面図、第２図（ａ）〜第２図（ｄ
）は従来のＭＯ３型電界効果トランジスタの種々の製造
工程を示す断面図、第３図（ａ）〜第３図（ｆ）は同じ
〈従来のＭＯＳ型電界効果トランジスタの種々の製造工
程を示す断面図である。
シリコン基板
Ｎ−領域
ゲート酸化膜
ポリシリコン
酸素注入領域
酸化膜
サイドウオール
Ｎ＋領領
域リコン基板
酸化膜
ポリシリコン
窒化膜
Ｎ−領域
酸化膜
酸化膜サイドウオール
Ｎ＋領領
域ａ）
一
第１図
ｅ−・Ｎ町積賊。
第２図
第３図
（Ｃ）
（ｅ）
（ｆ）FIGS. 1(a) to 1(e) are cross-sectional views showing various manufacturing steps of a MOS field effect transistor manufactured by the method of manufacturing a semiconductor device of the present invention, and FIGS. 2(a) to 2(e) d
3(a) to 3(f) are cross-sectional views showing various manufacturing steps of a conventional MO3 field effect transistor. It is a diagram. Silicon substrate N- region Gate oxide film Polysilicon Oxygen implantation region Oxide film Sidewall N+ region Recon board oxide film Polysilicon nitride film N- region Oxide film Oxide film Sidewall N+ region a) - Fig. 1 e-・N Town thief. Figure 2 Figure 3 (C) (e) (f)
Claims (1)
して半導体ゲート電極を形成する工程と、イオン注入に
より第２導電型の低濃度不純物領域を形成する工程と、
酸素イオンをななめに注入する工程と、熱処理によりゲ
ート電極の１部の選択的に酸化する工程と、異方性エッ
チングによりサイドウォールを形成する工程と、イオン
注入により第２導電型の高濃度不純物領域を形成する工
程とを具えることを特徴とするＭＯＳ型半導体装置の製
造方法。1. A step of forming a semiconductor gate electrode on the surface of a semiconductor substrate of a first conductivity type via a gate oxide film, and a step of forming a low concentration impurity region of a second conductivity type by ion implantation.
A step of diagonally implanting oxygen ions, a step of selectively oxidizing a part of the gate electrode by heat treatment, a step of forming sidewalls by anisotropic etching, and a step of implanting high concentration impurities of the second conductivity type by ion implantation. 1. A method of manufacturing a MOS type semiconductor device, comprising the step of forming a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1336456A JPH03198349A (en) | 1989-12-27 | 1989-12-27 | Manufacture of mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1336456A JPH03198349A (en) | 1989-12-27 | 1989-12-27 | Manufacture of mos type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03198349A true JPH03198349A (en) | 1991-08-29 |
Family
ID=18299326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1336456A Pending JPH03198349A (en) | 1989-12-27 | 1989-12-27 | Manufacture of mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03198349A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5258319A (en) * | 1988-02-19 | 1993-11-02 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a MOS type field effect transistor using an oblique ion implantation step |
| US5804496A (en) * | 1997-01-08 | 1998-09-08 | Advanced Micro Devices | Semiconductor device having reduced overlap capacitance and method of manufacture thereof |
| US5893739A (en) * | 1996-10-01 | 1999-04-13 | Advanced Micro Devices, Inc. | Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer |
| US5909622A (en) * | 1996-10-01 | 1999-06-01 | Advanced Micro Devices, Inc. | Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant |
| US5985724A (en) * | 1996-10-01 | 1999-11-16 | Advanced Micro Devices, Inc. | Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer |
-
1989
- 1989-12-27 JP JP1336456A patent/JPH03198349A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5258319A (en) * | 1988-02-19 | 1993-11-02 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a MOS type field effect transistor using an oblique ion implantation step |
| US5893739A (en) * | 1996-10-01 | 1999-04-13 | Advanced Micro Devices, Inc. | Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer |
| US5909622A (en) * | 1996-10-01 | 1999-06-01 | Advanced Micro Devices, Inc. | Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant |
| US5985724A (en) * | 1996-10-01 | 1999-11-16 | Advanced Micro Devices, Inc. | Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer |
| US6104064A (en) * | 1996-10-01 | 2000-08-15 | Advanced Micro Devices, Inc. | Asymmetrical transistor structure |
| US5804496A (en) * | 1997-01-08 | 1998-09-08 | Advanced Micro Devices | Semiconductor device having reduced overlap capacitance and method of manufacture thereof |
| US6091118A (en) * | 1997-01-08 | 2000-07-18 | Advanced Micro Devices, Inc. | Semiconductor device having reduced overlap capacitance and method of manufacture thereof |
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