JPS62273774A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a field-effect transistor having a stable LDD structure by simple processes, by utilizing the difference in size of a gate electrode after anisotropic etching and after isotropic etching as the region of low concentration drain and source diffused layer. CONSTITUTION:An isolating oxide film 2 is formed on a silicon substrate 1 having a P-type surface. Thereafter, a gate oxide film 3 is formed in a transistor forming region by a thermal oxidation method. Then, polysilicon 4 for a gate electrode is deposited by a pressure reduced CVD method. Then a gate-electrode forming pattern 5 is formed with positive resist. Thereafter, anisotropic etching of the polysilicon is performed. At this time, the size of the polysilicon after etching is about the same as the size of the resist. Then arsenic ions are implanted without removing the resist, and a high concentration drain and source diffused layer 6 is formed. The gate electrode undergoes isotropic etching. Thereafter the resist is removed by oxygen plasma. With the polysilicon electrode as a mask, arsenic ions are implanted, and a low concentration drain and source diffused layer 7 is formed.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Industrial Field of Application The present invention relates to a method for manufacturing a micro field effect transistor with high withstand voltage. The formation of a structure has become one of the important factors, and one of the most effective means to achieve this, which has become popular in recent years, is to use polysilicon or high-melting point metal compounds for the gate electrode. This method forms drain and source diffusion layers in a self-aligned manner with the gate electrode. Memory devices are the most typical device that has a fine structure using this method. By the way, in an insulated gate field effect transistor having this structure, when the gate length is about 1.5 μm or less, the depth of the drain and source diffusion layers needs to be about 0.3 μm or less to ensure the effective channel length. . In this case, in a simple self-aligned field effect transistor, the drain breakdown voltage decreases, especially due to the large curvature of the drain diffusion layer. In order to prevent this phenomenon, LDD (Litely Doped Dra) is a structure often used when forming fine field effect transistors.
in).

In this method, a low concentration same-type impurity layer is provided inside the high concentration drain diffusion layer on the gate side to prevent electric field concentration in a portion with a large curvature.

Problems to be Solved by the Invention However, the method for obtaining such a structure requires many complicated steps, such as the need to form side walls of polysilicon or the like on the side walls of the gate electrode after forming the gate electrode. It is.

The present invention eliminates the need for complicated and unstable steps such as sidewall formation in conventional methods when implementing LDD structures.

Means for Solving the Problems The method for manufacturing a field effect transistor of the present invention is as follows. The main surface of the semiconductor substrate is divided into a transistor formation region and an isolation region by a well-known selective oxidation method. Next, after forming a gate oxide film in the transistor formation region, polysilicon or a high melting point metal compound is deposited. Next, anisotropic etching is performed using the resist as a mask to form a gate electrode having the same dimensions as the resist. Thereafter, in this state, ion implantation is performed to form highly doped drain and source diffusion layers in a self-aligned manner. Next, after performing isotropic etching of the gate electrode, the resist is removed and low concentration drain and source diffusion layers are formed in a self-aligned manner by second ion implantation. After that, normal annealing is performed, and then a step of forming an upper electrode interlayer film, etc. is carried out.

Function: In the method for forming an electrode effect transistor of the present invention,
The difference in the dimensions of the gate electrode after anisotropic etching and after isotropic etching is the low concentration drain.

This becomes the region of the source diffusion layer. According to the present invention, an insulated gate type field effect transistor having a stable LDD structure can be formed without requiring a complicated process by only requiring a resist as a mask during gate formation.

EXAMPLES Below, examples of the method for manufacturing a field effect transistor of the present invention will be described in detail with reference to the drawings. In Figure 1, P type (
After forming an isolation oxide film 2 having a thickness of approximately 7000 μm on a silicon substrate 1 having a surface of 100 μm by selective oxidation method, an isolation oxide film 2 having a thickness of approximately 700 μm is formed in the transistor formation region by thermal oxidation method.
0 gate oxide film 3 is formed. Next, approximately 500 layers of polysilicon 4 for a gate electrode are deposited by low pressure CVD. Then, the polysilicon is doped with phosphorus and 6.
After lowering the specific resistance, a pattern 5 for forming a gate electrode is formed using a positive resist with a thickness of about 1 μm. At this time, the resist is irradiated with deep ultraviolet light to oxidize the resist. Thereafter, polysilicon is anisotropically etched using a reactive ion etching method using a mixed gas of sulfur hexafluoride and carbon tetrachloride.

At this time, the dimensions of the polysilicon after etching are approximately the same as the dimensions of the resist. Next, arsenic ions are implanted without removing the resist. The injection conditions at this time are acceleration voltage 40
The KeV dose is 2×10 ffi. This ion implantation is for forming a highly doped drain and source diffusion layer 6. Thereafter, the gate electrode is isotropically etched using the resist as a mask. The method uses plasma etching using a mixed gas of Freon (200 SCCM) and oxygen (2 osccM). The amount of side etching by this etching is approximately 4000. Thereafter, the resist is removed by oxygen plasma, and arsenic ions are implanted in a self-aligned manner using the polysilicon electrode as a mask, resulting in the result shown in FIG. At this time, the implantation condition 7be7 is that the so KeV dose is 1×10. This ion implantation is for forming a lightly doped drain and source diffusion layer 7. Next, heat treatment is performed at 900° C. for 30 minutes to anneal the ion-implanted layer, and then an upper electrode and interlayer film are formed.

Effects of the Invention According to the present invention, a field effect transistor having a stable LDD structure can be obtained through a simple process.

FIG. 3 is a cross-sectional view of the device showing steps of the method.

DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Isolation oxide film, 3...Gate oxide film, 4...Gate electrode, 6...Photoresist , 6...
High concentration drain, source ion implantation layer, 7...
Low concentration drain and source ion implantation layers.

Name of agent: Patent attorney Toshio Nakao and one other person (-
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Claims (3)

[Claims] (1) A first step of sequentially laminating a gate insulating film and a gate electrode film made of polysilicon or a high melting point metal on the main surface of a semiconductor substrate of one conductivity type, and a gate formed on the gate electrode film. Using a resist mask for electrode formation,
a second step of anisotropically etching the gate electrode film to form a gate electrode; and a second step of ion-implanting a first impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask. a third step of forming source and drain first regions in a consistent manner; and a fourth step of isotropically etching the gate electrode using the resist mask.
After removing the resist mask, using the gate electrode as a mask, a second impurity having a conductivity type opposite to that of the semiconductor substrate and having a lower concentration than the first impurity is ion-implanted into the semiconductor substrate, and self-alignment is performed. source and drain second
A method for manufacturing a field effect transistor, comprising: a fifth step of forming a region; and a sixth step of forming an interlayer insulating film and a contact electrode for the source and drain first regions. (2) The method for manufacturing a field effect transistor according to claim 1, which includes the step of irradiating the resist mask with deep ultraviolet light after the first step. (3) The method for manufacturing a field effect transistor according to claim 1, wherein the fourth step is plasma etching using a mixed gas of fluorocarbon and oxygen.