JPH06104276A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lower resistance of a low concentration diffusion layer to become a source and a drain while improving reliability in a MOS transistor of an LDD structure having a gate electrode consisting of a polycrystalline silicon layer and a high melting point metal layer. CONSTITUTION:A gate insulating film 2 is formed on a one conductivity type semiconductor substrate 1 and a gate electrode 6 consisting of a polycrystalline silicon layer 4 and a high melting point metal layer 5 is formed on the gate insulating film 2. Then, a first insulation film 11 and a second insulation film 7 are formed on the gate electrode 6 while being laminated, and the second insulation film 7 and a third insulation film 9 are formed on the side of the gate electrode 6 while being laminated, besides the other conductivity type low concentration diffusion layer 8 having the gate electrode 6 as a mask and the other conductivity type high concentration diffusion layer 10 having the third insulation film 9 as a mask overlapping a part of a low concentration diffusion layer 8 is formed on the semiconductor substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated and highly reliable semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as the density of semiconductor devices has increased, it has been desired to reduce the sheet resistance and contact resistance of the polycrystalline silicon layer on the gate electrode in order to achieve higher speed and lower power consumption. It is rare. Therefore, a structure in which a refractory metal layer is deposited on the polycrystalline silicon layer on the gate electrode is used.

A conventional semiconductor device will be described below. FIG. 4 is a sectional view of a main part of a conventional semiconductor device.
The cross section of the N-channel transistor after performing the patterning is shown. As shown in FIG. 4, a polycrystalline silicon layer 4 is formed on the P-type silicon substrate 1 via a gate oxide film 3.
And a gate electrode 6 composed of the refractory metal layer 5 is formed. A low concentration diffusion layer 8 is formed on the P-type silicon substrate 1 by ion implantation using the gate electrode 6 as a mask.
A high-concentration diffusion layer 10 is formed outside the gate electrode 6 by ion implantation using the side wall 9 as a mask.

Such an N channel MOS transistor is formed as follows. First, the polycrystalline silicon layer 4 is formed on the P-type silicon substrate 1 via the gate oxide film 3.
After depositing the refractory metal layer 5, the polycrystalline silicon layer 4 and the refractory metal layer 5 are etched using the photoresist as a mask to form the gate electrode 6. Next, phosphorus ions or arsenic ions are implanted into the surface of the P-type silicon substrate 1 using the gate electrode 6 as a mask to form a low concentration diffusion layer 8. Next, an oxide film is deposited on the surface of the P-type silicon substrate 1 and the oxide film is etched by using the etch back method to remove the sidewall 9
To form. Next, arsenic ions are implanted on the surface of the P-type silicon substrate 1 using the side wall 9 as a mask to form a high concentration diffusion layer 10, and then activation heat treatment is performed to complete the transistor.

[0005]

However, in the above conventional structure, when the shallow junction is to be obtained, the activation of the low concentration diffusion layer 8 is performed after the formation of the high concentration diffusion layer 10, so that the low concentration diffusion layer 8 is activated. There is a problem that activation is not performed at a sufficient temperature and for a long time, and when the low concentration diffusion layer 8 is activated before the formation of the high concentration diffusion layer 10, film peeling or abnormal oxidation occurs.

The present invention solves the above-mentioned conventional problems, and provides a semiconductor device and a manufacturing method thereof capable of sufficiently activating a low-concentration diffusion layer without peeling off a refractory metal layer. To aim.

[0007]

In order to achieve this object, a semiconductor device of the present invention has a gate electrode in which a first insulating film and a second insulating film are laminated to form a gate. A second insulating film and a third insulating film are laminated on the side surface of the electrode, and the other conductivity type low concentration layer is formed on the semiconductor substrate using the gate electrode as a mask to overlap a part of the low concentration diffusion layer. The high-concentration diffusion layer of the other conductivity type is formed using the diffusion layer and the third insulating film as a mask.

In the method of manufacturing a semiconductor device of the present invention, a step of depositing a polycrystalline silicon layer on a first conductivity type semiconductor substrate via a gate oxide film and then depositing a refractory metal layer on the polycrystalline silicon layer. A step of depositing a first insulating film on the refractory metal layer, a step of patterning the first insulating film, the refractory metal layer and the polycrystalline silicon layer to form a gate electrode, and an upper part of the gate electrode. And a step of depositing a thin second insulating film on the side surface, a step of forming the other conductivity type low-concentration diffusion layer using the gate electrode as a mask and performing activation heat treatment, and a step of forming a third insulating film on the side surface of the gate electrode. And a step of forming a high-concentration diffusion layer of the other conductivity type using the third insulating film as a mask.

[0009]

With this structure, the activation of the low-concentration diffusion layer can be performed immediately after the formation of the low-concentration diffusion layer without film peeling, and the side wall can be formed without exposing the refractory metal layer.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of an essential part of the semiconductor device of the present invention. As shown in FIG.
A gate electrode 6 made of a refractory metal layer 5 and a polycrystalline silicon layer 4 formed via a LOCOS oxide film 2 and a gate oxide film 3 is formed on a type silicon substrate 1.
A first insulating film 11 and a second insulating film 7 are formed on the gate electrode 6.
Are laminated and formed, and the second insulating film 7 and the third insulating film 9 are laminated and formed on the side surface of the gate electrode 6. An N-type low-concentration diffusion layer 8 is formed on the P-type silicon substrate 1 using the gate electrode 6 as a mask, and an N-type high-concentration diffusion layer 10 is formed using the third insulating film 9 as a mask.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. 2A to 2C are process cross-sectional views of the first half of the manufacturing method,
3A to 3C are process cross-sectional views of the latter half process of the manufacturing method.

First, as shown in FIG. 2A, a LOCOS oxide film 2 and a gate oxide film 3 are formed on a P-type silicon substrate 1 in predetermined regions of about 700 nm and about 20 nm, respectively. Next, as shown in FIG. 2B, a polycrystalline silicon layer 4 is deposited to a thickness of 250 nm by the low pressure CVD method. Refractory metal layer 5 on it
Is deposited to 200 nm. The insulating film 11 is deposited thereon to a thickness of 200 nm. Next, as shown in FIG. 2 (c), gate patterning is performed using a dry etching technique. Next, as shown in FIG. 3A, an insulating film 7 is deposited to a thickness of 20 nm. Next, phosphorus ions or arsenic ions are ion-implanted on the surface of the P-type silicon substrate 1 to form the low-concentration diffusion layer 8, and then activation heat treatment is performed. Next, as shown in FIG. 3B, a P-type silicon substrate 1
After depositing an oxide film of 200 nm on the surface of, the side wall 9 is formed by etching the oxide film using the etch back method. Next, as shown in FIG. 3C, arsenic ions are implanted into the surface of the P-type silicon substrate 1 using the side wall 9 as a mask to form a high-concentration diffusion layer 10, and then activation heat treatment is performed to complete the transistor. To do.

[0013]

As described above, according to the present invention, sufficient activation of the low-concentration diffusion layer can be performed immediately after formation of the low-concentration diffusion layer without peeling off the film, and the refractory metal layer is not exposed to the side wall. It is possible to realize an excellent semiconductor device capable of forming a package and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a semiconductor device according to an embodiment of the present invention.

2A to 2C are process cross-sectional views of the first half of the method for manufacturing the same semiconductor device.

3A to 3C are process cross-sectional views of the latter half of the method for manufacturing the same semiconductor device.

FIG. 4 is a sectional view of a main part of a conventional semiconductor device.

[Explanation of symbols]

 1 Silicon Substrate (Semiconductor Substrate) 3 Gate Insulating Film 4 Polycrystalline Silicon Layer 5 Refractory Metal Layer 6 Gate Electrode 7 Insulating Film (Second Insulating Film) 8 Low Concentration Diffusion Layer 9 Sidewall (Third Insulating Film) 10 High-concentration diffusion layer 11 Insulating film (first insulating film)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 21/316 29/62 G 9055-4M 9274-4M H01L 21/94 A 7377-4M 29/78 301 P (72) Inventor Takashi Nakabayashi 1006 Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Atsushi Hori At 1006 Kadoma, Kadoma City Osaka Prefecture (72) Inventor Yoji Masuda, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A gate insulating film is formed on a conductive type semiconductor substrate, and a gate electrode composed of a polycrystalline silicon layer and a refractory metal layer is formed on the gate insulating film. A first insulating film and a second insulating film are stacked on the gate electrode, and a second insulating film and a third insulating film are stacked on the side surface of the gate electrode. On the semiconductor substrate, the other conductivity type low concentration diffusion layer using the gate electrode as a mask and the other conductivity type high concentration diffusion layer overlapping with part of the low concentration diffusion layer using the third insulating film as a mask are formed. Semiconductor device. 2. A step of depositing a polycrystalline silicon layer on a conductive type semiconductor substrate through a gate insulating film and then depositing a refractory metal layer on the polycrystalline silicon layer, and a step of depositing a refractory metal layer on the polycrystalline silicon layer. Forming a gate electrode having a first insulating film thereon by photolithography after depositing a first insulating film on the substrate, and depositing a thin second insulating film on the upper and side surfaces of the gate electrode; Forming a low concentration diffusion layer of the other conductivity type using the gate electrode as a mask;
Performing a heat treatment for activation of the low-concentration diffusion layer, forming a third insulating film on the side surface of the gate electrode, and forming a high-concentration diffusion layer of the other conductivity type using the third insulating film as a mask And a method of manufacturing a semiconductor device.