JPS63144575A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63144575A JPS63144575A JP29145786A JP29145786A JPS63144575A JP S63144575 A JPS63144575 A JP S63144575A JP 29145786 A JP29145786 A JP 29145786A JP 29145786 A JP29145786 A JP 29145786A JP S63144575 A JPS63144575 A JP S63144575A
- Authority
- JP
- Japan
- Prior art keywords
- regions
- film
- source
- drain regions
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- -1 oxygen ions Chemical class 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000003213 activating effect Effects 0.000 abstract description 2
- 239000007772 electrode material Substances 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910002065 alloy metal Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a method for manufacturing a semiconductor device.
（従来の技術）
従来、半導体装置は例えば次のようにして製造されてい
る。ｐ型の半導体基板に素子分離領域を形成すると共に
、該素子分離領域で分離された島状の素子領域を形成す
る。つづいて素子領域にゲート酸化膜を介してゲート電
極を形成し、更にｎ型のソース●ドレイン領域を形成し
た後、全面に第１の絶縁膜として、ＣＶＤ−Ｓｉｎ，膜
を堆積し、更に第２の絶縁膜としてＢＰＳＧ膜（ボロン
嗜リンシリケートガラス）を順次堆積する。そして、選
択的１ｃ ＣＶＤ−Ｓ ｉ Ｏ， ｇ、ＢＰＳＧ Ｍｊ
Ｃ ：ｌ ：／ ９ クト；ｈ −ルを開孔し、ＡＡｌ
［を蒸着した後バターニングして、コンタクトホールを
介して前記ソース●ドレイン領域等に接続し、Ｍ配線を
形成し、ＭＯＳ型半導体装置を製造する。(Prior Art) Conventionally, semiconductor devices have been manufactured, for example, in the following manner. An element isolation region is formed in a p-type semiconductor substrate, and island-shaped element regions separated by the element isolation region are formed. Next, a gate electrode is formed in the element region via a gate oxide film, and an n-type source/drain region is formed, and then a CVD-Sin film is deposited on the entire surface as a first insulating film, and then a second insulating film is deposited on the entire surface. As the second insulating film, BPSG films (boron phosphorus silicate glass) are sequentially deposited. and selective 1c CVD-S i O, g, BPSG Mj
C:l:/9 Cut;h - hole is drilled and AAl
[After being vapor-deposited, it is patterned and connected to the source and drain regions etc. through contact holes to form M wiring, thereby manufacturing a MOS type semiconductor device.
しかしながら、上述した従来の技術においては素子の高
速化・大規模化の要求から素子の微細化を進めると、い
わゆる短チヤネル効果が発生して電気的特性の劣化をも
たらす、即ち高速化により配線抵抗やソース・ドレイン
領域の抵抗を大きくすることができないためソース・ド
レイン領域形成のための不純−添加は極端に低濃度にで
きない、したがって拡散層の深さが深くなり、必然的に
横方向への拡散が進み、実効チャネル長が減少し、いわ
ゆる短チヤネル効果が発生してしまう。However, in the above-mentioned conventional technology, when elements are made smaller due to demands for higher speeds and larger scale elements, a so-called short channel effect occurs, resulting in deterioration of electrical characteristics. Since it is not possible to increase the resistance of the source/drain regions, the impurity doping for forming the source/drain regions cannot be made at an extremely low concentration. Therefore, the depth of the diffusion layer becomes deep, which inevitably causes lateral damage. As the diffusion progresses, the effective channel length decreases, resulting in the so-called short channel effect.
また、低抵抗にして拡散深さを浅くすると、電極取り出
し用ＡＪ配線を形成した後、いわゆるつき抜は現象が発
生し、接合が破壊され素子のリーク電流が増大し、特性
上重大な影響を引き起こしてし才う。In addition, if the resistance is low and the diffusion depth is shallow, a so-called punch-through phenomenon will occur after forming the AJ wiring for taking out the electrode, which will destroy the junction and increase the leakage current of the element, which will have a serious effect on the characteristics. I'm good at causing it.
（発明が解決しようとする問題点）
本発明は上記事情に鑑みてなされたもので、高速化、高
集積度化の要求から素子の微細化が進められた場合、短
チヤネル効果による電気的特性の劣化を防止し且・つ、
素子の信頼性を向上させることができる半導体装置の製
造方法を提供することを目的とするものである。(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned circumstances.When the miniaturization of elements is advanced due to the demand for higher speed and higher integration, the electrical characteristics due to the short channel effect To prevent the deterioration of the
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the reliability of the device.
（問題点を解決するための手段）
本発明は、ソース・ドレイン領域の形成予定領域に酸素
をイオン注入し、その後熱処理により活性化し、この領
域の一部に絶縁膜を任意の深さに容易に形成するもので
ある。(Means for Solving the Problems) The present invention involves implanting oxygen ions into regions where source/drain regions are to be formed, then activating them by heat treatment, and easily forming an insulating film in a part of this region to an arbitrary depth. It is to be formed.
（作用）
本発明による半導体装置の製造方法によれば、微細化さ
れた素子の電気的特性の劣化を防止し且つ信頼性が向上
された半導体装置を簡単な工程で製造できる。(Function) According to the method for manufacturing a semiconductor device according to the present invention, it is possible to prevent deterioration of the electrical characteristics of a miniaturized element and to manufacture a semiconductor device with improved reliability through a simple process.
（実施例）
次に本発明をｎチャネルＭＯＳトランジスタの製造に適
用した例について、第１図へ第５図を参照して説明する
。(Example) Next, an example in which the present invention is applied to the manufacture of an n-channel MOS transistor will be described with reference to FIGS. 1 and 5.
まず、Ｐ型シリコン基板（１）にフィールド酸化膜（２
）を形成し、このフィールド酸化膜で分離された島状の
基板領域表面に熱酸化によりゲート酸化膜（３）を形成
した後、全面にゲート電極材料膜、例えば多結晶シリコ
ン膜を堆積し、これをバターニングして前記ゲート酸化
膜上にゲート電極（４）を選択的に形成した（第１図）
。次いで、ソース・ドレイン領域となる領域のみに酸素
不純物をイオン注入する。マスクとしてフォトレジスト
膜（５）を用いる。その注入条件として加速エネルギー
は１０ｋｅｖ〜１００ｋｅＶ 、 Ｖ−ス量はＩ Ｘ
１０１８／ｍ以上任意に設定すれば良い。次いでフォト
レジスｌ’Ｎｆ５）を除去後、高温熱処理を行ない更に
活性化し、ソース・ドレイン領域となる領域の一部に第
１の絶縁膜（６）を形成する（第２図）。First, a field oxide film (2) is placed on a P-type silicon substrate (1).
), and after forming a gate oxide film (3) by thermal oxidation on the surface of the island-shaped substrate region separated by this field oxide film, a gate electrode material film, such as a polycrystalline silicon film, is deposited on the entire surface, This was patterned to selectively form a gate electrode (4) on the gate oxide film (Figure 1).
. Next, oxygen impurity ions are implanted only into regions that will become source and drain regions. A photoresist film (5) is used as a mask. The conditions for the implantation are that the acceleration energy is 10keV to 100keV, and the amount of V-s is I
It may be set arbitrarily to 1018/m or more. Next, after removing the photoresist l'Nf5), high-temperature heat treatment is performed to further activate it, and a first insulating film (6) is formed in a part of the region that will become the source/drain region (FIG. 2).
つづいてゲート電極及びフィールド酸化膜をマスクとし
てｎ型不純物、例えば砒素を島状の基板領域にイオン注
入し、その後の熱処理により活性化し、ＬＤＤ法を用い
ｎ型のソース・ドレイン領域（７１（８１を形成する（
第３図）。これは例えばＣＶＤ５ｉｎ、膜（９）を全面
堆積後、これを全面几ＩＥによってゲート側壁に自己整
合的に残置し、燐又は砒素を基板にイオン注入して形成
する。Next, using the gate electrode and field oxide film as a mask, n-type impurities, such as arsenic, are ion-implanted into the island-shaped substrate region, activated by subsequent heat treatment, and using the LDD method, n-type source/drain regions (71 (81) form (
Figure 3). This is formed, for example, by depositing a 5-inch CVD film (9) over the entire surface, leaving it on the gate sidewall in a self-aligned manner by IE over the entire surface, and implanting phosphorus or arsenic ions into the substrate.
ひきつづき全面に厚さ３０００λのＣＶＤ−８ｉｎ、膜
及び厚さ７０００ＡのＨＰ ＳＧ膜（９）αＱを順次堆
積して、２層構造の第２絶縁膜を形成する（第４図）。Subsequently, a CVD-8 inch film with a thickness of 3000λ and an HPSG film (9) αQ with a thickness of 7000A are sequentially deposited on the entire surface to form a second insulating film with a two-layer structure (FIG. 4).
次いでソース・ドレイン領域の一部に対応する第２の絶
縁膜及びゲート酸化膜を選択的にエツチングしてコンタ
クトホールを形成し、そして全面にＡノー８７を蒸着し
、バターニングして前記ソース・ドレイン領域にコンタ
クトホールを介して接続するソース・ドレイン電極を形
成し、ｎチャネル型のＷＳトランジスタを製造する（第
５図）。Next, the second insulating film and the gate oxide film corresponding to part of the source/drain region are selectively etched to form a contact hole, and A-no-87 is deposited on the entire surface and patterned to form the source/drain region. Source/drain electrodes connected to the drain region via contact holes are formed to manufacture an n-channel type WS transistor (FIG. 5).
このようにこの半導体装置の製造方法によればソース・
ドレイン領域下に＠縁膜層が設けられているため、浅い
拡散層を形成を容易に形成することができ、且つＡｌの
つき抜は現象を完全に防止することができた。In this way, according to this semiconductor device manufacturing method, the source
Since the @edge film layer was provided under the drain region, a shallow diffusion layer could be easily formed, and the phenomenon of Al penetration could be completely prevented.
本発明方法はｎチャネルＭＯＳトランジスタの製造のみ
に限らず、ＰチャネルＭＯ８トランジスタ。The method of the present invention is not limited to manufacturing only n-channel MOS transistors, but also P-channel MO8 transistors.
０ＭＯ８構造の製造にも同様に適用できる。It can be similarly applied to the production of 0MO8 structures.
以上説明したように、本発明によれば素子の信照性を高
めることができた。As explained above, according to the present invention, the reliability of the device can be improved.
第１図、第２図、第３図、第４図及び第５図は本発明の
一実施例に係わるｎチャネルＭＯ８型トランジスタの製
造方法を工程順に示す断面図である。
図において、
１・・・ｐ型シリコン膜、２・・・フィールド酸化膜、
３・・・ゲート酸化膜、４・・ゲート電極、５・・・フ
ォトレジスト膜、６・・・第一絶縁膜、７・・・ｎ型ソ
ース領域、Ｂ −・−ｎ型トレーン領域、９ ・・・Ｃ
ＶＤ−８ｉｏ、膜、１０・・・ＨＰ８Ｇ膜、１１・・・
ｉ配線、１２・・・Ａ／とＳｉの合金属。FIGS. 1, 2, 3, 4, and 5 are cross-sectional views showing a method of manufacturing an n-channel MO8 type transistor according to an embodiment of the present invention in order of steps. In the figure, 1... p-type silicon film, 2... field oxide film,
3... Gate oxide film, 4... Gate electrode, 5... Photoresist film, 6... First insulating film, 7... N-type source region, B--n-type train region, 9 ...C
VD-8io, membrane, 10...HP8G membrane, 11...
i wiring, 12... alloy metal of A/ and Si.
Claims (3)
ート電極を選択的に形成する工程と、後の工程でソース
、ドレイン領域となる領域のみに所望のピーク値を持つ
ように酸素を添加する工程と、ソース、ドレイン領域を
形成する工程と、全面に絶縁膜を堆積し、コンタクトホ
ールを形成する工程と、ソース、ドレイン領域とコンタ
クトホールを介して接続する取り出し金属配線を形成す
る工程とを具備したことを特徴とする半導体装置の製造
方法。(1) A process of selectively forming a gate electrode in the element region of a semiconductor substrate via a gate insulating film, and adding oxygen to only the regions that will become source and drain regions in a later step so as to have a desired peak value. a step of forming source and drain regions; a step of depositing an insulating film over the entire surface and forming contact holes; and a step of forming lead-out metal wiring connected to the source and drain regions via the contact holes. A method for manufacturing a semiconductor device, comprising:
ことを特徴とする、前記特許請求の範囲第１項記載の半
導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, characterized in that an ion implantation method is used as the method for adding oxygen.
＾１＾８／ｃｍ＾３以上のドーズ量でイオン注入するこ
とを特徴とする前記特許請求の範囲第２項記載の半導体
装置の製造方法。(3) As an ion implantation method, oxygen ions were added at 1×10
3. The method of manufacturing a semiconductor device according to claim 2, wherein ions are implanted at a dose of ^1^8/cm^3 or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29145786A JPS63144575A (en) | 1986-12-09 | 1986-12-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29145786A JPS63144575A (en) | 1986-12-09 | 1986-12-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63144575A true JPS63144575A (en) | 1988-06-16 |
Family
ID=17769115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29145786A Pending JPS63144575A (en) | 1986-12-09 | 1986-12-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63144575A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100489586B1 (en) * | 1997-12-30 | 2005-09-06 | 주식회사 하이닉스반도체 | Method of forming junction part of semiconductor device |
-
1986
- 1986-12-09 JP JP29145786A patent/JPS63144575A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100489586B1 (en) * | 1997-12-30 | 2005-09-06 | 주식회사 하이닉스반도체 | Method of forming junction part of semiconductor device |
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