JPH03171740A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable formation of a reference concentration diffusion region, a high- concentration source/drain region, and a low-concentration diffusion region in self- aligned manner without any need for a side-wall formation process by the ion implanta tion with a polysilicon oxide film, which is formed at a gate electrode or on the surface of this gate electrode by thermal oxidation, as a mask. CONSTITUTION:An N<+> polysilicon layer 23 which is formed on a P-type silicon sub strate 21 is subjected to patterning, thus forming a gate electrode 24. After that, with the gate electrode 24 as a mask, N-type impurities are ion-implanted, thus forming reference concentration N-type regions 26a and 26b on the surface of the substrate 21 on both sides of the gate electrode 24. Then, the surface of the gate electrode 24 is subjected to expansion oxidation by the thermal oxidation method, thus forming a polysilicon oxide film 27. Then, with the gate electrode 24 and the polysilicon oxide film 27 as masks, the N-type impurities are ion-implanted at high concentration, thus forming high-concentration source.drain regions 29a and 29b on the surface of the substrate 21. After that, with the gate electrode 24 as a mask, the N-type impurities are ion-implanted at low concentration, thus forming low-concentration N-type regions 31a and 31b on the surface of the substrate 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, particularly a MIS field effect transistor. [Prior Art] In recent years, with the miniaturization of semiconductor devices, the gate length of MIS transistors has become shorter, and device deterioration due to the generation of hot carriers has become a problem. Therefore, as a countermeasure to this problem, especially in NMISFETs, the so-called LDD structure, in which the drain region is made into a double diffusion structure of low concentration and high concentration diffusion regions, is widely used in order to alleviate the high electric field near the drain region and improve the withstand voltage. It has been used. by the way,
Such an LDD structure suppresses the generation of hot carriers by relaxing the electric field near the drain, but on the other hand, the hot carriers are affected by electrons captured in the gate oxide film near the drain, and the low concentration N-type region is The surface becomes depleted, which increases parasitic resistance, resulting in a disadvantage that the current driving ability of the transistor with the LDD structure decreases. Conventionally, as a method for manufacturing MI SIL field effect transistors that eliminates such drawbacks, there is a method disclosed in Japanese Patent Application Laid-Open No.
There is something disclosed in 73. This type of manufacturing method will be described below with reference to Figure 2. Figure 2 shows a cross-sectional view of the process. First, a gate oxide film 2 and a certain gate electrode 3 made of polysilicon are sequentially formed on a P-type silicon substrate 1. Next, using the gate electrode 3 as a mask, N-type impurity #'l (P) is ion-implanted at a low concentration to form low-concentration N-type regions 5 on the surface of the substrate 1 on both sides of the gate electrode 3.
a, 5b (Fig. 2a). Thereafter, a polysilicon oxide film 6 is grown on the surface of the gate electrode 3 by thermal oxidation. As a result, the gate length increases by the amount that polysilicon oxide film 6 expands and oxidizes. Next, the gate electrode 3 and polysilicon oxide 1
Using 196 as a mask, arsenic (As), which is an N-type impurity, is added.
Ions are implanted at a higher concentration than the impurity concentration of the low concentration N type regions 5a and 5b to form reference concentration N type regions 8a and 8b in contact with the outside of the low concentration N type regions 5a and 5b on the surface portion of the base Fi1. (Figure 2b). After that, after depositing SiOtll on the entire surface, reactive ion etching is performed to form a layer on both sides of the gate electrode 3.
Form sidewalls 9a and 9b. After that, gate electrode 3. Polysilicon oxide film 6 and sidewall 9a
, 9b as a mask, arsenic is applied to the reference concentration N-type region 8a,
Ions are implanted at a higher impurity concentration than those of the reference concentration N-type regions 8a. Highly doped source/drain regions 11a and 11b in contact with the outside of 8b were formed on the surface of the substrate 1 to complete the MOSFET (FIG. 2C). In this case, the high concentration source/drain regions 11a, llb are the reference concentration N type regions 8a. The impurity concentration is higher than that of 8b, and the reference concentration N-type region 8a and 8b are the low concentration N-type region 5.
The impurity concentration is higher than that of a and 5b. According to this triple diffusion LDD structure, by providing the reference concentration N type regions 8a and 8b, the low concentration N type region 8a and 8b are provided.
Depletion of the type regions 5a and 5b was alleviated, and as a result, a decrease in the current driving ability of the transistor could be suppressed.

[Invention tries to solve! Ia) However, in the conventional MISFET manufacturing method, sidewalls are used to obtain a triple diffusion structure, which increases the number of man-hours, leading to higher manufacturing costs and lower yields. Ta. SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the number of steps and improve the current driving ability of a transistor. [Means to solve the problem]

In order to achieve the above-mentioned object, the present invention includes a step of sequentially forming a gate electrode from a gate insulating film and polysilicon on a semiconductor substrate, and ion implantation of impurities at a desired concentration using the gate electrode as a mask. Then, forming reference concentration diffusion regions in a self-aligned manner on the surface of the substrate on both sides of the gate electrode, and expanding and oxidizing the surface of the gate electrode by a thermal oxidation method to form a polysilicon oxide film. step, using the polysilicon oxide film and the gate electrode as a mask, impurity ions are implanted at a concentration higher than the concentration of the reference concentration diffusion region, and a high concentration higher than the reference concentration adjacent to the outside of the reference concentration diffusion region is implanted. After forming the source/drain regions in a self-aligned manner and removing the polysilicon oxide film, using the gate electrode as a mask, impurity is ion-implanted to a concentration lower than that of the reference concentration diffusion region, and The method includes the step of forming in a self-aligned manner a low concentration diffusion region having a concentration lower than a reference concentration and in contact with the inside of the concentration diffusion region.

[For production]

In the present invention, gate i! After forming the reference concentration diffusion region using the electrode as a mask, high concentration source/drain regions are formed in a self-aligned manner using the gate electrode and the polysilicon oxide film formed on the surface of the L gate electrode by thermal oxidation as a mask. However, since the low concentration diffusion region is formed in a self-aligned manner using the narrow gate electrode after removing the polysilicon oxide film as a mask, there is no need for a zide wall formation process, and a triple diffusion LID structure is formed. is obtained. Therefore, the number of man-hours is reduced, and manufacturing costs and yields are improved. (Example) An example of the method for manufacturing a MISFET of the present invention will be described based on FIG. 1. Furthermore, Figure 1 shows a cross-sectional view of the process. First, gate oxidation n222 is formed on the P-type silicon substrate 2l.
is formed by a thermal oxidation method. Next, non-doped polysilicon is deposited to a thickness of, for example, 4000 cm on top of this by chemical vapor deposition (CVD), and then phosphorus, which is an N-type impurity, is diffused into the polysilicon. ``Polysilicon layer 23 (Figure 1a). The N-polysilicon Jii 23 is then patterned to form a gate t tri 2 4 (FIG. 1b). Thereafter, using the gate electrode 24 as a mask, N-type impurities such as As' are ion-implanted to a desired concentration, and the reference concentration N-type regions 26a. 26b (Fig. 1C). Next, the surface of the gate electrode 24 is expanded and oxidized by thermal oxidation to form a polysilicon oxide film 27 with a thickness of 1,000 μm. As a result, the gate length becomes longer by about 500 mm on one side, and at this time, the reference concentration N-type regions 26a and 26b undergo some thermal diffusion. Note that when the gate electrode 24 is oxidized, the surface of the substrate 2l is also oxidized, but this does not pose a problem because the oxidation rate is low. Next, using the gate electrode 24 and the polysilicon oxide film 27 as a mask, an N-type impurity, for example, arsenic, is ion-implanted to a higher concentration than the reference concentration N-type regions 26a and 26b, and outside the reference concentration N-type regions 26a and 26b. High concentration source/drain regions 29a, 2 in contact with
9b is formed on the surface of the substrate 21. Therefore, in this case, the source/drain regions 29a. The deviation between 29b and the reference concentration N-type region 26a26b, that is, the offset length, is the expansion of the polysilicon oxide film 27 from the shape of the gate electrode 24 before oxidation (dotted line in the figure), that is, the 500% offset length and the polysilicon oxide film Group Y$ concentration N at the time of 27 formation
This is the thermal diffusion L7 of the mold regions 26a and 26b (Fig. 1d). After that, polysilicon oxide film 27 and gate oxide film 2 are formed.
The oxide film on the substrate 2l except for 2 is removed. Vt, and using the gate electrode 24 as a mask, an N-type impurity such as phosphorus is added to the reference concentration N-type regions 26a. Ions are implanted at a concentration lower than that of the reference concentration N-type regions 26a. Low concentration N-type regions 31a and 3lb which are in contact with the inside of the substrate 26b are formed on the surface of the substrate 2l (FIG. 1e). Furthermore, after depositing an insulating film 32 on the entire surface, this insulating film 32
source/drain regions 29a. A hole is made in the part above 29b, and the M wiring 33 is formed in this opening part, and the process is completed (FIG. 1r).

Note that the method of the present invention uses boron (B) or BF! as a P-type impurity on an N-type silicon substrate. It is also applied to the manufacture of PMISFETs having P-type diffusion regions formed by ion implantation such as ion implantation. Further, the reference concentration N type regions 26a, 26b are the low concentration N type regions 31a. 3lb, the impurity concentration is higher than that of the high concentration source/drain regions 29a. The impurity concentration is lower than that of 29b. By the way, the high impurity concentration in the LDD structure is
The low impurity concentration is approximately X 10"io
About ns/ctl. [Effects of the Invention] As explained above, according to the present invention, the base IIi concentration is diffused in a self-aligned manner by ion implantation using the gate electrode and the polysilicon oxide film formed by thermal oxidation on the surface of the gate electrode as a mask. Since a high concentration source/drain region, a high concentration source/drain region, and a low concentration diffusion region are formed respectively, a triple diffusion LDD structure can be obtained without requiring a sidewall forming step. Therefore, the number of man-hours can be reduced, and therefore manufacturing costs can be reduced, yields can be improved, and the current driving ability of the transistor can also be improved.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view of an embodiment of the method of the present invention, and FIG. 2 is a process sectional view of a conventional method. 2l... P type silicon substrate, 22... Gate oxide film, 23... N° polysilicon layer, 24... Gate electrode, 26a, 26b... Reference concentration N type region, 27...
・Polysilicon oxide film, 29a, 29b...source・
Drain region, 31a, 3lb...Low concentration N type region. Narataka; last Nisai engineering drawing 2nd drawing

Claims (1)

[Claims] A step of sequentially forming a gate insulating film and a gate electrode made of polysilicon on a semiconductor substrate, and using the gate electrode as a mask, ion-implanting impurities at a desired concentration, and implanting impurities on both sides of the gate electrode. forming a reference concentration diffusion region in a self-aligned manner on the surface of the substrate; expanding and oxidizing the surface of the gate electrode by thermal oxidation;
a step of forming a polysilicon oxide film, and using the polysilicon oxide film and the gate electrode as masks, implanting impurity ions at a concentration higher than that of the reference concentration diffusion region, and forming a reference layer in contact with the outside of the reference concentration diffusion region; After removing the polysilicon oxide film, using the gate electrode as a mask, impurities are formed at a concentration lower than that of the reference concentration diffusion region. A method of manufacturing a semiconductor device, comprising the step of: implanting ions into the reference concentration diffusion region to form a low concentration diffusion region having a concentration lower than the reference concentration and in contact with the inside of the reference concentration diffusion region in a self-aligned manner.