JP4391745B2 - Manufacturing method of FET with notch gate - Google Patents

Manufacturing method of FET with notch gate Download PDF

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JP4391745B2
JP4391745B2 JP2002543688A JP2002543688A JP4391745B2 JP 4391745 B2 JP4391745 B2 JP 4391745B2 JP 2002543688 A JP2002543688 A JP 2002543688A JP 2002543688 A JP2002543688 A JP 2002543688A JP 4391745 B2 JP4391745 B2 JP 4391745B2
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Prior art keywords
gate
layer
implant
halo
gate layer
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JP2004514290A (en
Inventor
ノワク、エドワード
ハケイ、マーク
フルカワ、トシハル
ホラク、デヴィッド
ホルムズ、スティーヴン
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インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
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Priority to US09/713,830 priority Critical patent/US6891235B1/en
Application filed by インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation filed Critical インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
Priority to PCT/GB2001/005015 priority patent/WO2002041383A1/en
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    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/4966Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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    • H01L29/4983Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H01L29/4991Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to integrated circuit chips. More particularly, it relates to a field effect transistor (FET). More particularly, it relates to an improved FET having a T-gate.
[0002]
[Prior art]
The speed of the FET is mainly determined by the distance from end to end of the gate. Transistors with shorter gate conductor distances have a shorter spacing between the source and drain and generally have a higher speed. The industry has moved to photolithographic devices that provide light with shorter wavelengths and higher numerical aperture lenses, allowing this gate size to be reduced for each generation of integrated circuits. However, these changes often increased the variation in the line width of the upper and lower chips. Furthermore, these changes resulted in an increase in gate resistance.
[0003]
U.S. Pat. No. 5,750,430 describes a gate with curved sidewalls produced by depositing gate polysilicon in the window between the spacers. This transistor is larger in size from the bottom to the top. The channel length formed thereby is shorter than the minimum dimension, and the overlap capacity is reduced.
[0004]
In 1999, Washington, DC, Technical Digest of the 1999 International Electron Devices Meeting, page 415, T. Ghani et al.'S report “100nm GateLength High performance / Low Power CMOS Transistor” has a notch at the bottom of the poly gate. An FET with is described. This notch offsets the source-drain-extension implant, provides shorter gate dimensions with improved capacitance, and avoids increased resistance because the gate has a larger cross-sectional area as a whole. Yes.
[0005]
[Problems to be solved by the invention]
Gates defined by spacers with bent sidewalls and notched gates provide advantages, but substantial further device performance improvements are possible. This improvement can be induced by modifying the structure described in US Pat. No. 5,750,430 and T. Ghani. The following invention provides this new structure and a method for realizing this new structure.
[0006]
[Means for Solving the Problems]
In one aspect, the present invention is a FET that includes a gate having an upper portion having an upper dimension and a lower portion having a lower dimension. The upper dimension is larger than the lower dimension. The FET includes a diffusion defined by a lower portion.
[0007]
The FET also includes a diffusion defined by the top. The diffuser defined by the lower part can be a halo implant and the diffuser defined by the upper part can be an extension implant.
[0008]
Another aspect of the invention is achieved by a FET comprising a gate having a first conductive material under a second conductive material different from the first conductive material. The first conductive material is notched.
[0009]
Another aspect of the present invention is a method for fabricating a semiconductor device. The method includes providing a substrate formed from a first material. The substrate has a surface. The next step is to form a gate dielectric on this surface. A gate is then deposited on the gate dielectric. The gate includes a first gate layer and a second gate layer, the first gate layer is in contact with the gate dielectric, and the second gate layer is on the first gate layer. The next step is to chemically react the edge of the first gate layer to form a first reaction product. Finally, the method includes selectively removing the first reaction product relative to the remaining portion of the first gate layer and the second gate layer to provide a notch in the first gate layer.
[0010]
According to one embodiment, the FET has a T-shaped gate. This FET has a halo diffusion part self-aligned with respect to the lower part of the T and an extension diffusion part self-aligned with respect to the upper part. This separates the halo from the extension implant, which provides significant advantages. The upper and lower portions of the T-shaped gate can be formed from layers of two different materials, such as germanium and silicon. The two layers are patterned simultaneously. Then, the exposed lower edge of the lower layer is selectively chemically reacted to etch away the reaction product to provide a notch.
[0011]
In other embodiments, the gate is formed from a single gate conductor. Metal is conformally deposited along the sidewall, and recess etched to expose the top of the sidewall and heated to form a silicide along the bottom. The silicide is etched to provide a notch.
[0012]
The above and other features and advantages of the present invention will become apparent from the following detailed description of the invention, as illustrated in the accompanying drawings.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Halo or pocket implants are well known as a means of suppressing short channel effects in very short MOSFETs. Short channel effects include a decrease in Vt and an increase in subthreshold slope as gate length is shortened. Usually, halo formation is achieved by implanting the dopant type opposite to the source / drain doping (eg, by implanting boron into the NFET). High energy is used in the halo implant to reach under the gate beyond the source / drain extension implant. Typically, source / drain extension implants have significantly lower energy and higher dose as shown in Table 1. As a result, the halo p-dopant is often located deeper than the n-dopant in the source / drain diffusion. Therefore, the n-type source / drain diffusion portion is entirely covered with the p-type halo. Although p-type dopants in the channel region are useful for short channel effects, the halo extending under the source / drain has the disadvantageous effect of increasing the source / drain junction capacitance.
[Table 1]
[0014]
Although high energy is used to move the halo far from the source / drain and extension, generally the net p-dopant available for the halo is only a fraction of the total dose of implanted p-dopant. This is because most of the p-implants fall into the more heavily doped source / drain and cancel out. Therefore, with standard implant technology, normal control can only reach a limited halo concentration, which limits the degree of control of the short channel effect. Furthermore, it is difficult to control the halo carrier concentration due to the small number of p-type dopant atoms that remain unbalanced. Thus, small variations in the dose or energy of the halo or extension implant can result in large variations in halo carrier concentration.
[0015]
In the conventional halo, when the carrier concentration is in the range of 10 17 to 10 18 , a 10 × change in halo carrier concentration can be obtained at a distance of 70 to 100 A. This gradual rate of carrier concentration change is the result of offsetting the halo implant by the extension implant and the source / drain implant. Improved short channel control requires a more rapid change in carrier concentration that results in the same 10x change in carrier concentration at 30-40A. Furthermore, in order to improve the device performance, the halo concentration under the source / drain can be reduced to reduce the source / drain junction capacitance. As the halo doping concentration increases, the depletion region narrows, which increases the capacitance.
[0016]
From a notched gate, two distinct changes can be made. First, the energy of the halo implant can be reduced, which results in a less spread and thus steeper halo distribution result, as shown by comparing curves 16 and 16 'of FIG. Curve 16 is a conventional halo implant, while curve 16 ′ is a halo implant obtained by using the notched gate of the present invention described in detail herein below. Curve 18 is a distribution map of the extension implant for both conventional and notched gates. Second, in the region where the halo implant is spaced from the extension implant edge, the halo has a higher net doping concentration, as shown by points B and B 'on curves 17 and 17'. Have. This results in a narrower depletion region in this area. Furthermore, the higher halo doping results in a steeper junction, as shown at points A and A ′ in FIGS. As the depletion region is narrowed, Vt short channel control is improved. The doping distribution at the point A ′ on the curve 17 ′ is steeper than the doping distribution at the point A on the curve 17, and the device can be stopped by controlling the channel potential with a shorter channel.
[0017]
The halo doping distribution at point C ′ on curve 17 ′ is the point on curve 17 because a lower energy implant can be used to reduce diffusion and form a halo with a notched gate. It can be steeper than the halo doping distribution in C. As a result, the spread of the halo is reduced and the dispersion of the halo is reduced. Therefore, the linear Vt control can be improved even if the channel length is shortened. As shown in FIGS. 3, 4 and 5, the steeper distribution C ′ of the halo implant places the source and drain diffusions closer together before the two halos merge. Can do. As a result, the same Vt control can be performed even with a shorter channel length. Physically, FIGS. 3, 4 and 5 differ only in the gate length. In FIG. 3, both the conventional gate halo and the notched gate halo have an identifiable region adjacent to the source and drain, and are equally effective in Vt control. In FIG. 4, the notched gate halo continues to form an identifiable halo adjacent to the source and drain, but conventional halos begin to integrate and Vt is poorly controlled. In FIG. 5, the conventional halo is fully integrated, while the notched gate halo is about to begin integrating. Therefore, excellent Vt control can be realized with a shorter channel length by using the notched gate halo.
[0018]
One method of separating the halo implant from the extension implant is to implant a halo at the edge of the gate, then provide a spacer along the gate sidewall, and then implant the source / drain extension. The width of the spacer is 10-20 nm, which provides a gap between the halo and the extension implant. This method allows the desired separation from the halo source / drain extensions, but requires that the NFET extension block mask be used twice, once before spacer formation and once after. Is a drawback. This method also requires tight control of the spacer width to ensure that the separation of halo and implant can be reproduced. The present invention improves this approach.
[0019]
The method of the present invention provides a bevel implant of a halo using a tip-down T-gate, while providing an extension implant from a more perpendicular direction, thereby separating the halo implant from the extension implant, a sharper joint, and Enables tighter control of halo carrier concentration. Thus, the present invention allows the halo implant and extension implant to be placed laterally offset from each other without any masking step. Thus, the extension block mask may be used only once to provide both the halo and the extension. In the separation of the implant by this single mask, the T-shaped gate 20 is first etched on the semiconductor wafer 21. (T-shaped gates can be formed using the processes described herein below.)
[0020]
As shown in FIG. 6, the T-shaped gate 20 has a lower portion 22 having a dimension L 1 and an edge 23 on the gate dielectric 24. The T-gate 20 also has an upper portion 26 having a dimension L 2 and an edge 27 on the lower portion 22. The notch 28 is thereby defined and has a height h and a lateral length u. Here, u = (L 2 −L 1 ) / 2. After forming the T-shaped gate 20, an extension block mask (not shown) is provided to block the PFETS during the formation of the NFET 30.
[0021]
The p-type halo 32 is then implanted at an angle q given by tan q <h / u. Here, h is the height of the notch, and u is the lateral length of the notch. Accordingly, the halo 32 is defined by the lower portion 22 of the T-gate 20. In general, to provide device implants on wafers of different orientations, halo bevel implants are made from all four basic orientations. As shown in FIG. 6, any particular device receives an implant in an active area in two directions. Finally, the expansion diffusion part 34 is implanted at an angle perpendicular to the semiconductor wafer 21. Accordingly, the diffusion extension 34 is defined by the edge 27 of the large upper portion 26 of the gate 20.
[0022]
Accordingly, the implant edge 36 of the halo 32 is offset from the implant edge 38 of the extension 34 by a dimension approximately equal to u. This dimension is approximately equal to the dimension of the notch 28, and any implant is performed without any masking steps during the implant process. Because these two diffusions 32 and 34 are defined by different edges 23 and 27 of the gate 20, no masking step is required to achieve this separation. This is accomplished by performing vertical and beveled implants using the falling T-gate 20.
[0023]
In the next step, a layer of insulating material 46 is conformally deposited on all surfaces of the wafer 21, as shown in FIG. The insulating material 46 is made of a material such as silicon dioxide or silicon nitride. Next, as shown in FIG. 8, sidewall spacers 48 are formed using directional etching. Finally, as also shown in FIG. 8, the source / drain 50 is implanted, defined by spacers 48. Alternatively, as shown in FIG. 9, the insulating material 46 may be non-conformally deposited so that an air gap 49 is left behind the spacer 48 along the notched sidewall of the first layer 56. it can. A deposition process such as plasma enhanced chemical vapor deposition (PECVD) is known as a highly directional deposition process that deposits a thicker film in a horizontal plane compared to a vertical plane. As shown in FIG. 10, sidewall spacers 48 having air gaps 49 are formed using directional etching. The resulting air gap 49 has a dielectric constant of about 1.0, while the silicon dioxide sidewall spacer 48 has a dielectric constant of about 3.5. The air gap 49 reduces the effective dielectric constant of the sidewall spacer 48 and thus helps reduce the overlap capacitance.
[0024]
Although the T-shaped gate 20 allows separation of the halo and extension implants without the addition of a separate masking step, the process described herein allows the lower portion 22 to have a minimum length dimension. Also offers the great advantage of being able to substantially improve device performance. Furthermore, the method of the present invention allows this reduction in gate length without increasing line width tolerance. In addition, the T-shaped gate is provided with an upper portion 26 having a large area, thereby avoiding an unacceptable increase in gate resistance when the lower portion 22 shrinks. Thus, performance can be substantially improved without unacceptable negative effects.
[0025]
The T-gate 20 is formed by depositing a two-layer structure 54 on the gate dielectric 24 and isolation (not shown) on the wafer 21, as shown in FIG. The two-layer structure 54 includes a first layer such as a germanium layer 56 and a second layer such as a polysilicon layer 58. These two layers are selected from materials in which the first layer 56 and the second layer 58 are easily oxidized. Next, the two-layer structure 54 is patterned and etched by photolithography as shown in FIG. The etched germanium layer 56 and polysilicon layer 58 are equal in length and width. This length or width should be the smallest dimension that can be achieved with a photolithographic system.
[0026]
In the next step, the two-layer structure 54 is subjected to a chemical reaction step such as oxidation at about 500-600 C, as shown in FIG. At this temperature, germanium oxide 60 grows on the exposed edge of the germanium layer 56, as shown in FIG. The polysilicon layer 58 does not oxidize sufficiently at this temperature. The germanium oxide 60 grows and consumes a germanium layer 56 of 7 to 13 nm (lateral length u). Next, germanium oxide 60 is removed by water washing, and a notch 28 shown in FIG. 6 is provided. This oxidation process can be controlled very strictly and the reproducibility of the consumed germanium thickness is very good. All oxides can be removed without further etching of germanium or polysilicon. Thus, this oxidation and etching process allows a high degree of control over the amount of germanium layer 56 that is removed and allows tight tolerances in the length or width of the germanium layer 56. Accordingly, the germanium layer 56 has a dimension that is about 14 to about 26 nm shorter than the polysilicon layer 58. Thus, the size of the germanium layer 56 can be about 10 to about 50% less than the minimum size of the photolithographic system used, while the polysilicon layer 58 remains at the minimum size.
[0027]
In other embodiments, the first layer 56 may include a germanium compound Ge x Si 1-x . Here, x ranges from about 0.5 to about 1.0.
[0028]
Some other chemical reaction steps have similarly good control. For example, the first layer 56 can be polysilicon and the second layer 58 can be a refractory metal. A thin layer of metal such as platinum, titanium, tantalum, or cobalt is conformally deposited along the sidewalls of the two gate layers 56,58. Next, when the substrate is heated, the metal thin film reacts with the polysilicon layer 56 to form metal silicide along the sidewall edge of the first layer 56. The second layer 58 is a refractory metal and does not react. The notch 28 can then be formed by selectively etching the silicide so as not to affect the second layer.
[0029]
Alternatively, a single gate layer of polysilicon 66 can be used for gate 20 '. FIG. 14 shows a thin metal film 68 deposited and coated with a sidewall 70 of gate polysilicon 66. FIG. 15 shows that directional etching has been performed on the metal thin film 68, and the metal in the horizontal surface direction and in the direction of the upper portion 70a of the sidewall 70 of the gate polysilicon layer 66 is removed. Next, when the substrate 21 is heated, the remaining metal 68 ′ reacts with the polysilicon 66, and as shown in FIG. 16, the metal silicide 72 is formed only on the lower portion 70b of the sidewall 70 covered with the metal 68 ′. It is formed. Next, as shown in FIG. 17, the silicide is removed to form a notch 28. Metal silicide 72, such as cobalt silicide or titanium silicide, can be wet etched in hydrogen peroxide or hot sulfuric acid / hydrogen peroxide mixture.
[0030]
The T-gate 20 formed in this process has substantial advantages over prior art gates. Since the lower part of the gate 20 determines its effective channel length, the germanium layer 56 can be selectively oxidized and trimmed in this way by using tighter control than previous attempts to form a T-gate. Therefore, it is possible to provide a device with higher performance than a device without trimming. A longer or wider upper polysilicon layer 58 can be used to increase the overall conductivity of the gate conductor.
[0031]
If desired, the gate dielectric stack can also consist of a germanium lower layer and a silicon upper layer, and a SiGe graded layer between the two layers. In this case, a final gate conductor structure with a tapered profile is formed between the germanium film and the silicon film, instead of a sharp discontinuous profile.
[0032]
The first layer 56 and the second layer 58 may be made of other conductive materials that are selective in oxidation and oxide etching. For example, a refractory metal such as tungsten, tantalum, molybdenum, or titanium, or a silicide such as titanium silicide, cobalt silicide, or platinum silicide can be used for the second layer 58. Polysilicon can then be used for the first layer 56.
[0033]
In other embodiments, the first layer 56 can be selectively etched with respect to the second layer 58 to eliminate the oxidation step and form the T-shaped gate 20. However, in this case, it is expected that the process controllability is slightly inferior to the case where the etching is performed after the oxidation.
[0034]
Several embodiments of the present invention and modifications thereof have been described in detail herein and shown in the accompanying drawings, but various other modifications can be made without departing from the scope of the present invention, It will be apparent that it is possible to provide a FET with a notched gate. Nothing in the above specification is intended to limit the invention more narrowly than the appended claims. The provided examples are intended to be illustrative only and not exclusive.
[Brief description of the drawings]
FIG. 1 is an extension implant and halo doping profile for a conventional gate device and a notched gate device showing one side of the device.
FIG. 2 is an offset net doping profile of extension implants and halos for a conventional gate device and a notched gate device.
FIG. 3 is an offset net distribution profile of extension implants and halos for a conventional gate device and a notched gate device with different channel lengths showing the entire device including the source and drain. is there.
FIG. 4 is an offset net distribution profile of extension implants and halos for a conventional gate device and a notched gate device with different channel lengths showing the entire device including the source and drain. is there.
FIG. 5 is an offset net doping profile of extension implants and halos for conventional and notched gate devices with different channel lengths showing the entire device including source and drain. is there.
FIG. 6 is a cross-sectional view of a T-shaped gate showing a halo and extension implant defined by different edges of the T-shaped gate.
7 is a cross-sectional view showing process steps for forming spacers and source / drain implants for the T-shaped gate of FIG. 6. FIG.
FIG. 8 is a cross-sectional view showing process steps for forming spacers and source / drain implants for the T-shaped gate of FIG. 6;
9 is a cross-sectional view showing a process step of providing an air gap behind the spacer for the T-shaped gate of FIG. 6;
10 is a cross-sectional view showing a process step of providing an air gap behind a spacer for the T-shaped gate of FIG. 6;
11 is a cross-sectional view illustrating a process for fabricating the T-shaped gate of FIG.
12 is a cross-sectional view illustrating a process for fabricating the T-shaped gate of FIG. 6. FIG.
13 is a cross-sectional view illustrating a process for fabricating the T-shaped gate of FIG. 6. FIG.
FIG. 14 is a cross-sectional view illustrating another process for fabricating a T-gate without a two-layer structure of gate material.
FIG. 15 is a cross-sectional view illustrating another process for fabricating a T-gate without a two-layer structure of gate material.
FIG. 16 is a cross-sectional view illustrating another process for fabricating a T-gate without a two-layer structure of gate material.
FIG. 17 is a cross-sectional view illustrating another process for fabricating a T-gate without a two-layer structure of gate material.

Claims (6)

  1. A method of manufacturing a semiconductor device comprising:
    Providing a substrate made of a first material having a surface;
    Forming a gate dielectric on the surface;
    A first gate layer that contacts the gate dielectric is formed on the gate dielectric by depositing germanium or a germanium compound made of Ge x Si 1-x , where x is in the range of 0.5 to 1.0. a step, and forming the by forming a second gate layer by adhering the silicon on the first gate layer, gate conductor composed of said second gate layer and the first gate layer,
    Oxidizing the edge of the first gate conductor adjacent to the gate dielectric to form a first reaction product;
    Providing a notch in the first gate layer by selectively removing the first reaction product from the remaining portions of the first gate layer and the second gate layer;
    The first gate layer and the second gate layer are defined by edges of the second gate layer and from both edges of the extension diffusion formed by dopant implantation perpendicular to the gate dielectric. In order to form a halo extending in the channel region by a length corresponding to the width difference, a first dopant is implanted into the substrate at a predetermined angle with respect to the gate dielectric from a perpendicular perpendicular to the surface. An implant step, wherein the first dopant implant step is a halo implant;
    Including methods.
  2. Further comprising the method of claim 1 the step of providing a spacer along the sidewall of the second gate layer.
  3. The method according to claim 1 , wherein the first reaction product includes germanium oxide or silicon germanium oxide.
  4. Forming the gate conductor comprises forming a first layer of germanium on the gate dielectric, a second layer of silicon, and a SiGe graded layer between the first and second layers. including method of claim 1.
  5. Forming the extension diffusion as a second implant defined by the second gate layer of the gate conductor by performing a source / drain extension implant that implants a dopant perpendicular to the gate dielectric; comprising the method of claim 1.
  6. Forming a spacer adjacent to the top of the gate layer; and performing as a third implant defined by the spacer a source / drain implant that implants a dopant perpendicular to the gate dielectric. 6. The method of claim 5 , comprising.
JP2002543688A 2000-11-15 2001-11-13 Manufacturing method of FET with notch gate Expired - Fee Related JP4391745B2 (en)

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US7282423B2 (en) 2007-10-16

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