CN111697051A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN111697051A CN111697051A CN201910196119.3A CN201910196119A CN111697051A CN 111697051 A CN111697051 A CN 111697051A CN 201910196119 A CN201910196119 A CN 201910196119A CN 111697051 A CN111697051 A CN 111697051A
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- 238000000034 method Methods 0.000 title claims abstract description 97
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 150000002500 ions Chemical class 0.000 claims description 87
- 230000008569 process Effects 0.000 claims description 55
- 239000000463 material Substances 0.000 claims description 44
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 20
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 20
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 claims description 16
- -1 silicon carbide nitride Chemical class 0.000 claims description 15
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 24
- 238000000137 annealing Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 9
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 8
- 239000012495 reaction gas Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
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- 238000004519 manufacturing process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
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- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate is provided with a pseudo gate structure; forming a first opening and a second opening in the substrate on two sides of the pseudo gate structure, wherein a channel region is formed in the substrate between the first opening and the second opening; forming a first side wall on the side wall of the pseudo gate structure and the channel region; after the first side wall is formed, a first epitaxial layer is formed on the bottom surface of the first opening, and a second epitaxial layer is formed on the bottom surface of the second opening; after the first epitaxial layer and the second epitaxial layer are formed, removing the first side wall, forming a third opening between the dummy gate structure and the first epitaxial layer, and forming a fourth opening between the dummy gate structure and the second epitaxial layer; forming a third epitaxial layer on the first epitaxial layer and in the third opening, wherein the ion concentration of the third epitaxial layer is less than that of the first epitaxial layer; and forming a fourth epitaxial layer on the second epitaxial layer and in the fourth opening, wherein the ion concentration of the fourth epitaxial layer is less than that of the second epitaxial layer. The resulting structure enhances performance.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In the conventional semiconductor field, a conventional planar metal-oxide semiconductor field effect transistor (MOSFET) has a weak ability to control a channel current, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor (MOSFET), the fin type MOSFET has stronger short channel inhibition capability and stronger working current, and is widely applied to various semiconductor devices.
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of the integrated circuit devices to increase the speed thereof. Currently, as the semiconductor industry has progressed to the point of nanotechnology process in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices has been limited by various physical limits, particularly as the size of semiconductor devices has been reduced to the nanometer scale.
When the size of a semiconductor device is reduced to a nanometer level, the channel size of a gate in the device is correspondingly reduced, the short channel effect of a Fin field effect transistor (Fin FET) is more and more serious, and the performance of a semiconductor structure formed by the existing Fin field effect transistor (FinFET) needs to be improved urgently.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a pseudo gate structure; respectively forming a first opening and a second opening in the substrate at two sides of the pseudo gate structure, and forming a channel region in the substrate between the first opening and the second opening; forming a first side wall on the side wall of the pseudo gate structure and the surface of the side wall of the channel region; after the first side wall is formed, forming a first epitaxial layer on the bottom surface of the first opening, and forming a second epitaxial layer on the bottom surface of the second opening; after the first epitaxial layer and the second epitaxial layer are formed, removing the first side wall, forming a third opening between the dummy gate structure and the first epitaxial layer, and forming a fourth opening between the dummy gate structure and the second epitaxial layer; forming a third epitaxial layer on the first epitaxial layer and in the third opening, wherein the ion concentration of the third epitaxial layer is less than that of the first epitaxial layer; and forming a fourth epitaxial layer on the second epitaxial layer and in the fourth opening, wherein the ion concentration of the fourth epitaxial layer is less than that of the second epitaxial layer.
Optionally, the method for forming the first sidewall includes: depositing a first side wall material layer on the substrate, wherein the first side wall material layer is positioned on the side wall and the top of the pseudo gate structure, the side wall and the bottom of the first opening, and the bottom and the side wall of the second opening; and etching the first side wall material layer back until the substrate is exposed to form the first side wall.
Optionally, the first sidewall spacer is made of silicon oxide, silicon nitride, silicon carbide nitride, and silicon germanium nitride.
Optionally, the thickness of the first side wall is 2nm to 5 nm.
Optionally, the process for removing the first sidewall includes a dry etching process.
Optionally, the first epitaxial layer and the second epitaxial layer are formed simultaneously; the process for forming the first epitaxial layer and the second epitaxial layer comprises the following steps: and (5) an epitaxial growth process.
Optionally, the epitaxial growth process parameters include: the gas is SiH4 and GeH4, or SiH4 and PH3, and the ion concentration range of the gas is as follows: 8e 20-2 e 21/cc.
Optionally, the method for forming the third epitaxial layer includes: forming a first mask layer on the substrate, wherein the first mask layer exposes the third opening and the surface of the first epitaxial layer; forming a third epitaxial layer on the first epitaxial layer and in the third opening; the third epitaxial layer forming process includes: and (5) an epitaxial growth process.
Optionally, the epitaxial growth process parameters include: the gas is SiH4 and GeH4, or SiH4 and PH3, and the ion concentration range of the gas is as follows: 8e 20-1.2 e 21/cc.
Optionally, the method for forming the fourth epitaxial layer includes: forming a second mask layer on the substrate, wherein the second mask layer exposes the fourth opening and the surface of the second epitaxial layer; forming a fourth epitaxial layer on the second epitaxial layer and within the fourth opening; the fourth epitaxial layer forming process includes: and (5) an epitaxial growth process.
Optionally, the epitaxial growth process parameters include: the gas is SiH4 and GeH4, or SiH4 and PH3, and the ion concentration range of the gas is as follows: 4e 20-1.2 e 21/cc.
Optionally, the third epitaxial layer and the fourth epitaxial layer are formed simultaneously; the process for forming the third epitaxial layer and the fourth epitaxial layer comprises the following steps: and (5) an epitaxial growth process.
Optionally, the epitaxial growth process parameters include: the gas is SiH4 and GeH4, or SiH4 and PH3, and the ion concentration range of the gas is as follows: 4e 20-7 e 20/cubic centimeter.
Optionally, after the third epitaxial layer and the fourth epitaxial layer are formed, the method further includes: simultaneously carrying out selective ion implantation in the first epitaxial layer, the third epitaxial layer, the second epitaxial layer and the fourth epitaxial layer; the implanted ion species comprise N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions, and the energy is as follows: 5 kilo electron volts to 15 kilo electron volts, the ion concentration range is: 4e 20-8 e 20/cubic centimeter, the injection angle is: 0-15 degrees; the P-type ions comprise boron ions or boron-fluorine ions, and the energy is as follows: 1.5 kiloelectron volts, with ion concentrations ranging from: 4e 20-8 e 20/cubic centimeter, the injection angle is: 0 to 15 degrees.
Optionally, the ion concentration of the first epitaxial layer is the same as that of the second epitaxial layer.
Optionally, the ion concentration of the third epitaxial layer is greater than that of the fourth epitaxial layer.
Optionally, the ion concentration of the third epitaxial layer is the same as that of the fourth epitaxial layer.
Optionally, the method for forming the first opening and the second opening includes: and etching partial substrates on two sides of the pseudo gate structure by taking the pseudo gate structure as a mask to form the first opening and the second opening.
Optionally, the first epitaxial layer material includes phosphorus silicon or silicon germanium; the second epitaxial layer material comprises phosphorus silicon or silicon germanium; the third epitaxial layer material comprises phosphorus silicon or silicon germanium; the fourth epitaxial layer material comprises phosphorus silicon or silicon germanium.
Accordingly, the present invention also provides a semiconductor structure formed by any one of the above methods, comprising: a substrate; a gate structure on the substrate; the first epitaxial layer is positioned in the first opening and the second epitaxial layer is positioned in the second opening in the substrate on two sides of the grid structure; a third epitaxial layer positioned on the first epitaxial layer in the third opening between the gate structure and the first epitaxial layer; and the fourth epitaxial layer is positioned on the second epitaxial layer in a fourth opening between the gate structure and the second epitaxial layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the opening and the channel region are formed in the substrate on two sides of the pseudo gate structure respectively, the first side wall is formed on the side wall surface of the pseudo gate structure and the side wall surface of the channel region, the first epitaxial layer and the second epitaxial layer are formed in the surface of the bottom of the opening respectively, the first side wall is removed, the third epitaxial layer and the fourth epitaxial layer with low concentration are formed, and the first epitaxial layer and the third epitaxial layer are combined, the second epitaxial layer and the fourth epitaxial layer are combined and are used for forming a source region and a drain region respectively. The third epitaxial layer and the fourth epitaxial layer are in direct contact with the channel region, and ions diffused to the channel region by the source-drain doped layer are few due to low ion concentrations of the third epitaxial layer and the fourth epitaxial layer during subsequent annealing treatment, so that the doped ions diffused to the channel region are not easy to contact, and the short channel effect is inhibited. And the high-concentration first epitaxial layer is isolated from the channel region by the low-concentration third epitaxial layer, and the high-concentration second epitaxial layer is isolated from the channel region by the low-concentration fourth epitaxial layer, so that the ions of the high-concentration first epitaxial layer and the high-concentration second epitaxial layer are prevented from diffusing to the channel region, the contact resistance of a source-drain doped region and the series resistance between a source region and a drain region are reduced, and the electrical performance of the semiconductor device is ensured. In conclusion, the performance of the semiconductor device is improved.
Further, the ion concentration of the third epitaxial layer is greater than that of the fourth epitaxial layer, the first epitaxial layer and third epitaxial layer combination, and the second epitaxial layer and fourth epitaxial layer combination are respectively used for forming a source region and a drain region, so that the ion concentration of the formed source region is greater than that of the drain region, the ion concentration of the source region is high, the number of carriers activated by the source region is large after annealing, the series resistance among the source region, the channel region and the drain region is smaller, and the improvement of the electrical performance of the device is facilitated; meanwhile, the concentration of the drain region ions is low, so that the drain region ions can form a depletion region in a channel region, and the short channel effect can be effectively inhibited.
Drawings
FIG. 1 is a schematic cross-sectional view of an embodiment of a semiconductor structure;
fig. 2 to 13 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background, performance of a semiconductor structure formed by using conventional finfet devices is required to be improved. The description will be made with reference to the structure of a semiconductor.
FIG. 1 is a cross-sectional view of an embodiment of a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 having a fin 101 thereon; the fin part 101 is provided with a gate structure 103, and the side wall of the gate structure 103 is provided with a side wall 104; the gate structure 103 and the fin 101 on two sides of the sidewall 104 have a source drain epitaxial layer 105 therein.
In the semiconductor structure, doped ions are in the source-drain epitaxial layer 105, and a fin portion below the gate structure 103 and between the source-drain epitaxial layer 105 is a channel region. As the size of the semiconductor device is smaller and smaller, the size of the gate is correspondingly reduced, the channel region below the gate structure 103 is shortened, and the distance between the source epitaxial layer and the drain epitaxial layer is also shortened. In the process of forming the source-drain epitaxial layer 105, an annealing step is provided, doped ions in the source-drain epitaxial layer 105 can diffuse into a channel along with the thermal diffusion effect generated by annealing, and the diffusion of the doped ions in the source region and the doped ions in the drain region in the channel has the possibility of connection along with the shortening of the channel region, so that a series of short channel effects are generated, and the performance of a semiconductor device is influenced.
In order to solve the problems, the invention provides a semiconductor structure and a forming method thereof.A source-drain epitaxial region is respectively provided with two epitaxial layers, the two epitaxial layers have concentration difference, and when the concentration of the ions of the epitaxial layer in contact with a channel region is low during subsequent annealing treatment, less ions diffuse into the channel, so that the short channel effect is inhibited; meanwhile, the high-concentration epitaxial layer is not in contact with the channel, so that ions are prevented from diffusing into the channel, and the electrical performance of the device is ensured.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 13 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 2, a substrate 200 is provided, the substrate having a dummy gate structure 201 thereon, the dummy gate structure 201 including a second sidewall spacer 203 on a sidewall.
In this embodiment, the substrate 200 has a fin portion, and the dummy gate structure 201 crosses the fin portion. In other embodiments, the substrate 200 is a planar substrate.
The substrate 200 is made of monocrystalline silicon, polycrystalline silicon, amorphous silicon or semiconductor materials such as silicon, germanium, silicon germanium and gallium arsenide; in this embodiment, the material of the substrate 200 is monocrystalline silicon.
The material of the second sidewall spacers 203 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride, and in this embodiment, the material of the second sidewall spacers 203 includes silicon nitride.
Referring to fig. 3, a first opening 211 and a second opening 212 are respectively formed in the substrate 200 at two sides of the dummy gate structure 201, and a channel region 210 is formed in the substrate 200 between the first opening 211 and the second opening 212.
The method of forming the first opening 211 and the second opening 212 includes: and etching parts of the substrate 200 at two sides of the dummy gate structure 201 by using the dummy gate structure 201 as a mask to form the first opening 211 and the second opening 212.
The process of etching the substrate 200 at both sides of the dummy gate structure 201 includes an anisotropic dry etching process.
The first opening 211 provides a space for a first epitaxial layer to be formed on the bottom surface of the first opening 211.
The second opening 212 provides space for a subsequent formation of a second epitaxial layer on the bottom surface within the second opening 212.
In this embodiment, after the first opening 211 and the second opening 212 are formed subsequently, a first sidewall is formed on the sidewall of the dummy gate structure 201 and the sidewall surface of the channel region 210. Please refer to fig. 4 to 5.
Referring to fig. 4, a first sidewall material layer 213 is deposited on the substrate 200, wherein the first sidewall material layer 213 is located on the sidewalls and the top of the dummy gate structure 201, the sidewalls and the bottom of the first opening 211, and the bottom and the sidewalls of the second opening 212.
The material of the first sidewall material layer 213 includes silicon oxide, silicon nitride, silicon carbide nitride, and silicon germanium nitride. In this embodiment, the material of the first sidewall material layer 213 includes silicon oxide.
Referring to fig. 5, the first sidewall material layer 213 is etched back until the substrate 200 is exposed, so as to form the first sidewall 214.
In this embodiment, the significance of forming the first side wall 214 on the side wall of the dummy gate structure 201 and the side wall surface of the channel region 210 is: after the first side wall 214 is formed, a first epitaxial layer and a second epitaxial layer with high ion concentration are respectively grown on the bottom surfaces of the first opening 211 and the second opening 212, after the first side wall 214 is removed, a third epitaxial layer with low ion concentration is formed on the first epitaxial layer and in the third opening, a fourth epitaxial layer with low ion concentration is formed on the second epitaxial layer and in the fourth opening, the third epitaxial layer with low concentration and the fourth epitaxial layer with low concentration can be directly contacted with a channel region, so that when annealing treatment is carried out subsequently, ions diffused from a source-drain doped layer to the channel region are few, the doped ions diffused to the channel region are not easy to contact, and the short channel effect is inhibited. In this embodiment, the thickness of the first sidewall 214 is 2nm to 5 nm.
The significance of selecting the thickness range of the first side wall 214 to be 2nm to 5nm is as follows: if the thickness of the first sidewall 214 is less than 2nm, the requirement on the precision of the process is high, and the prior art is difficult to precisely etch; if the thickness of the first sidewall 214 is greater than 5nm, the distances between the first epitaxial layer and the second epitaxial layer, which are grown in the first opening 211 and the second opening 212, and the channel region 210 are further, the series resistance between the source region, the channel region, and the drain region is increased, the electrical performance of the semiconductor device is affected, the performance of the semiconductor device improved by forming a low-concentration epitaxial layer in contact with the channel region to reduce the diffusion of ions from the source region to the channel region is offset, and the significance of forming the first sidewall 214 on the sidewall of the dummy gate structure 201 and the sidewall surface of the channel region 210 is lost.
Referring to fig. 6, after forming the first sidewall 214, a first epitaxial layer 221 is formed on the bottom surface of the first opening 211, and a second epitaxial layer 222 is formed on the bottom surface of the second opening 212.
The first epitaxial layer 221 and the second epitaxial layer 222 are formed simultaneously.
The process of forming the first epitaxial layer 221 and the second epitaxial layer 222 includes: and (5) an epitaxial growth process.
The first epitaxial layer 221 and the second epitaxial layer 222 are made of the same material, and the material includes phosphorus silicon or silicon germanium.
The process parameters for forming the phosphorus-silicon epitaxial layer are as follows: the reaction gas includes: SiH4And pH3The gas ion concentration is: 8e 20/cubic centimeter to 2e 21/cubic centimeter, and the gas pressure range is as follows: 1 to 100 torr, and the temperature range is as follows: 500 ℃ to 800 ℃.
The technological parameters for forming the silicon-germanium epitaxial layer are as follows: the reaction gas includes: SiH4And GeH4The ion concentration is as follows: 8e 20/cubic centimeter to 2e 21/cubic centimeter, and the gas pressure range is as follows: 1 to 100 torr, and the temperature range is as follows: 500 ℃ to 800 ℃.
Referring to fig. 7, after the first epitaxial layer 221 and the second epitaxial layer 222 are formed, the first sidewall 214 is removed, a third opening 215 is formed between the dummy gate structure 201 and the first epitaxial layer 221, and a fourth opening 216 is formed between the dummy gate structure 201 and the second epitaxial layer 222.
The process of removing the first sidewall spacers 214 includes a dry etching process.
In this embodiment, the material of the second sidewall 203 of the dummy gate structure 201 includes silicon nitride, the material of the first sidewall 214 includes silicon oxide, and the gas in the dry etching process selects a gas having a larger etching selectivity to silicon nitride and silicon oxide, so that when the first sidewall 214 is removed, the second sidewall 203 of the dummy gate structure 201 is not damaged, and the first sidewall 214 can be removed completely.
After the first sidewall 214 is removed, a third epitaxial layer is formed on the first epitaxial layer 221 and in the third opening 215, wherein the ion concentration of the third epitaxial layer is less than that of the first epitaxial layer 221; a fourth epitaxial layer is formed on the second epitaxial layer 222 and within the fourth opening 216, the fourth epitaxial layer having an ion concentration less than the ion concentration of the second epitaxial layer 222.
In this embodiment, the third epitaxial layer is formed first, and then the fourth epitaxial layer is formed.
Referring to fig. 8, a third epitaxial layer 225 is formed on the first epitaxial layer 221 and within the third opening 215.
The method of forming the third epitaxial layer 225 includes: forming a first mask layer 230 on the substrate 200, wherein the first mask layer 230 exposes the third opening 215 and the surface of the first epitaxial layer 221; a third epitaxial layer 225 is formed on the first epitaxial layer 221 and within the third opening 215.
In this embodiment, the process for forming the third epitaxial layer 225 includes: and (5) an epitaxial growth process.
In this embodiment, the third epitaxial layer 225 and the first epitaxial layer 221 are commonly used for forming a source epitaxial layer, and the third epitaxial layer 225 and the first epitaxial layer 221 are made of the same material.
When the first epitaxial layer 221 is made of phosphorus silicon, the third epitaxial layer 225 is made of phosphorus silicon, and the gate structure is used for forming an NMOS device. The process parameters for forming the third epitaxial layer 225 are as follows: the reaction gas includes: SiH4And pH3The ion concentration of the gas is: 8e 20/cubic centimeter to 1.2e 21/cubic centimeter, and the gas pressure range is as follows: 1 to 100 torr, and the temperature range is as follows: 500 ℃ to 800 ℃.
When the first epitaxial layer 221 is made of silicon germanium, the third epitaxial layer 225 is made of silicon germanium, and the gate structure is used for forming a PMOS device. The process parameters for forming the third epitaxial layer 225 are as follows: the reaction gas includes: SiH4And GeH4The ion concentration of the gas is: 8e 20/cubic centimeter to 1.2e 21/cubic centimeter, and the gas pressure range is as follows: 1 to 100 torr, and the temperature range is as follows: 500 ℃ to 800 ℃.
Referring to fig. 9, a fourth epitaxial layer 226 is formed on the second epitaxial layer 222 and within the fourth opening 216.
The method of forming the fourth epitaxial layer 226 includes: forming a second mask layer 240 on the substrate 200, the second mask layer exposing the fourth opening 216 and the surface of the second epitaxial layer 222; a fourth epitaxial layer 226 is formed on the second epitaxial layer 222 and within the fourth opening 216.
In this embodiment, the forming process of the fourth epitaxial layer 226 includes: and (5) an epitaxial growth process.
In the present embodiment, the fourth epitaxial layer 226 and the second epitaxial layer 222 are commonly used for forming a drain epitaxial layer, and the material of the fourth epitaxial layer 226 and the material of the second epitaxial layer 222 are the same.
When the material of the second epitaxial layer 222 is phosphorus silicon, the material of the fourth epitaxial layer 226 is phosphorus silicon, and the gate structure is used for forming an NMOS device. The process parameters for forming the fourth epitaxial layer 226 are: the reaction gas includes: SiH4And pH3The ion concentration of the gas is: 4e 20/cubic centimeter to 1.2e 21/cubic centimeter, and the gas pressure range is as follows: 1 to 100 torr, and the temperature range is as follows: 500 ℃ to 800 ℃.
When the material of the second epitaxial layer 222 is silicon germanium and the material of the fourth epitaxial layer 226 is silicon germanium, the gate structure is used to form a PMOS device. The process parameters for forming the fourth epitaxial layer 226 are: the reaction gas includes: SiH4And GeH4The ion concentration of the gas is: 4e 20/cubic centimeter to 1.2e 21/cubic centimeter, and the gas pressure range is as follows: 1 to 100 torr, and the temperature range is as follows: 500 ℃ to 800 ℃.
In this embodiment, the third epitaxial layer 225 and the first epitaxial layer 221 together form a source epitaxial layer, and the fourth epitaxial layer 226 and the second epitaxial layer 222 together form a drain epitaxial layer, and the ion concentration of the source epitaxial layer is higher than that of the drain epitaxial layer. The meaning that the ion concentration of the source epitaxial layer is higher than that of the drain epitaxial layer is as follows: the ion concentration of the source epitaxial layer is greater than that of the drain epitaxial layer, the ion concentration of the source epitaxial layer is high, the number of carriers activated by the source epitaxial layer is large after annealing, and the series resistance among the source region, the channel region and the drain region is smaller, so that the improvement of the electrical performance of the device is facilitated; meanwhile, the concentration of ions in the drain epitaxial layer is low, so that a depletion region is formed in a channel region by source and drain doped ions, and the short channel effect can be effectively inhibited.
In other embodiments, the third epitaxial layer and the fourth epitaxial layer are formed simultaneously.
Referring to fig. 10, a third epitaxial layer 235 is formed on the first epitaxial layer 221 and within the third opening 215, and a fourth epitaxial layer 236 is formed on the second epitaxial layer 222 and within the fourth opening 216.
The third epitaxial layer 235 and the fourth epitaxial layer 236 are formed simultaneously, and the ion concentration of the third epitaxial layer 235 and the ion concentration of the fourth epitaxial layer 236 are the same.
The process of forming the third epitaxial layer 235 and the fourth epitaxial layer 236 includes: and (5) an epitaxial growth process.
The material of the third epitaxial layer 235 and the fourth epitaxial layer 236 includes phosphorus silicon or silicon germanium. The process parameters for forming the phosphorus-silicon epitaxial layer are as follows: the reaction gas includes: SiH4And pH3The ion concentration of the gas is: 4e 20/cubic centimeter to 7e 20/cubic centimeter, and the gas pressure range is as follows: 1 to 100 torr, and the temperature range is as follows: 500 ℃ to 800 ℃.
The technological parameters for forming the silicon-germanium epitaxial layer are as follows: the reaction gas includes: SiH4And GeH4The ion concentration is: 4e 20/cubic centimeter to 7e 20/cubic centimeter, and the gas pressure range is as follows: 1 to 100 torr, and the temperature range is as follows: 500 ℃ to 800 ℃.
The material of the third epitaxial layer 235 is the same as the material of the first epitaxial layer 221.
The material of the fourth epitaxial layer 236 is the same as the material of the second epitaxial layer 222.
To this end, the first opening 211 has therein a first epitaxial layer 221 and a third epitaxial layer 235, and the second opening 212 has therein a second epitaxial layer 222 and a fourth epitaxial layer 236.
In the present embodiment, the significance of forming the epitaxial layers twice in the first opening 211 and the second opening 212, respectively, is that: the ion concentration of the third epitaxial layer 235 is less than that of the first epitaxial layer 221, the ion concentration of the fourth epitaxial layer 236 is less than that of the second epitaxial layer 222, and the low-concentration third epitaxial layer and the low-concentration fourth epitaxial layer are in direct contact with the channel region, so that fewer ions diffuse from the source-drain doped layer to the channel region during subsequent annealing treatment, and the doped ions diffuse to the channel region are not easy to contact, so that the short channel effect is inhibited; the first epitaxial layer with high concentration and the channel region which are formed firstly are separated by the third epitaxial layer with low concentration, the second epitaxial layer with high concentration and the channel region which are formed firstly are separated by the fourth epitaxial layer with low concentration, and therefore when ions of the first epitaxial layer with high concentration and ions of the second epitaxial layer with high concentration are prevented from diffusing to the channel region, contact resistance of a source-drain doped region and series resistance between a source region and a drain region are reduced, and electrical performance of a semiconductor device is guaranteed. In conclusion, the performance of the semiconductor structure is improved.
Referring to fig. 11, after the third epitaxial layer 235 and the fourth epitaxial layer 236 are formed, the method further includes: selective ion implantation is simultaneously performed into the first and third epitaxial layers 221 and 235, and the second and fourth epitaxial layers 222 and 236.
The implanted ion species include N-type ions or P-type ions.
In this embodiment, the N-type ions include phosphorus ions or arsenic ions, and the energy is: 5 kilo electron volts to 15 kilo electron volts, the ion concentration range is: 4e 20-8 e 20/cubic centimeter, the injection angle is: 0-15 degrees; the P-type ions comprise boron ions or boron-fluorine ions, and the energy is as follows: 1.5 kiloelectron volts, with ion concentrations ranging from: 4e 20-8 e 20/cubic centimeter, the injection angle is: 0 to 15 degrees.
After performing selective ion implantation into the first epitaxial layer 221, the third epitaxial layer 235, the second epitaxial layer 222, and the fourth epitaxial layer 236, the method further includes: annealing treatment; removing the pseudo gate structure, and forming a gate opening in the substrate; and forming a gate structure in the gate opening.
In this embodiment, the annealing process parameters include: the annealing temperature is 850-1050 ℃; the annealing time is 2.7 seconds to 3.3 seconds.
Referring to fig. 12, the dummy gate structure 201 is removed, and a gate opening 250 is formed in the substrate.
The process of removing the dummy gate structure 201 includes a dry etching process.
Referring to fig. 13, a gate structure 251 is formed in the gate opening 250.
The gate structure 251 includes a gate dielectric layer (not shown), a work function layer (not shown) on the gate dielectric layer, and a gate layer (not shown) on the work function layer.
The gate dielectric layer is made of a high-K dielectric material, the K value is larger than 3.9, and the gate dielectric layer comprises titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide, lanthanum oxide and the like.
The work function layer material includes titanium nitride.
The gate layer material comprises a metal, such as tungsten.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 13, including:
a substrate 200;
a gate structure 251 located on the substrate 200;
the first epitaxial layer 221 in the first opening and the second epitaxial layer 222 in the second opening in the substrate are positioned at two sides of the gate structure 251;
a third epitaxial layer 235 positioned on the first epitaxial layer 221 in a third opening between the gate structure 251 and the first epitaxial layer 221;
a fourth epitaxial layer 236 on the second epitaxial layer 222 in a fourth opening between the gate structure 251 and the second epitaxial layer 222.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a pseudo gate structure;
respectively forming a first opening and a second opening in the substrate at two sides of the pseudo gate structure, and forming a channel region in the substrate between the first opening and the second opening; forming a first side wall on the side wall of the pseudo gate structure and the surface of the side wall of the channel region;
after the first side wall is formed, forming a first epitaxial layer on the bottom surface of the first opening, and forming a second epitaxial layer on the bottom surface of the second opening;
after the first epitaxial layer and the second epitaxial layer are formed, removing the first side wall, forming a third opening between the dummy gate structure and the first epitaxial layer, and forming a fourth opening between the dummy gate structure and the second epitaxial layer;
forming a third epitaxial layer on the first epitaxial layer and in the third opening, wherein the ion concentration of the third epitaxial layer is less than that of the first epitaxial layer;
and forming a fourth epitaxial layer on the second epitaxial layer and in the fourth opening, wherein the ion concentration of the fourth epitaxial layer is less than that of the second epitaxial layer.
2. The method for forming a semiconductor structure according to claim 1, wherein the method for forming the first side wall comprises: depositing a first side wall material layer on the substrate, wherein the first side wall material layer is positioned on the side wall and the top of the pseudo gate structure, the side wall and the bottom of the first opening, and the bottom and the side wall of the second opening; and etching the first side wall material layer back until the substrate is exposed to form the first side wall.
3. The method for forming a semiconductor structure according to claim 1, wherein the material of the first sidewall spacers comprises silicon oxide, silicon nitride, silicon carbide nitride, and silicon germanium nitride.
4. The method for forming a semiconductor structure according to claim 1, wherein the first sidewall spacers have a thickness of 2nm to 5 nm.
5. The method for forming a semiconductor structure according to claim 1, wherein the process for removing the first sidewall spacers comprises a dry etching process.
6. The method of forming a semiconductor structure of claim 1, wherein the first epitaxial layer and the second epitaxial layer are formed simultaneously; the process for forming the first epitaxial layer and the second epitaxial layer comprises the following steps: and (5) an epitaxial growth process.
7. The method of forming a semiconductor structure of claim 6, wherein the epitaxial growth process parameters comprise: the gas being SiH4And GeH4Or SiH4And pH3The gas ion concentration ranges are: 8e 20-2 e 21/cc.
8. The method of forming a semiconductor structure of claim 1, wherein forming the third epitaxial layer comprises: forming a first mask layer on the substrate, wherein the first mask layer exposes the third opening and the surface of the first epitaxial layer; forming a third epitaxial layer on the first epitaxial layer and in the third opening; the third epitaxial layer forming process includes: and (5) an epitaxial growth process.
9. The method of forming a semiconductor structure of claim 8, wherein the epitaxial growth process parameters comprise: the gas being SiH4And GeH4Or SiH4And pH3The gas ion concentration ranges are: 8e 20-1.2 e 21/cc.
10. The method of forming a semiconductor structure of claim 1, wherein the method of forming the fourth epitaxial layer comprises: forming a second mask layer on the substrate, wherein the second mask layer exposes the fourth opening and the surface of the second epitaxial layer; forming a fourth epitaxial layer on the second epitaxial layer and within the fourth opening; the fourth epitaxial layer forming process includes: and (5) an epitaxial growth process.
11. The method of forming a semiconductor structure of claim 10, wherein the epitaxial growth process parameters comprise: the gas being SiH4And GeH4Or SiH4And pH3The gas ion concentration ranges are: 4e 20-1.2 e 21/cc.
12. The method of forming a semiconductor structure of claim 1, wherein the third epitaxial layer and the fourth epitaxial layer are formed simultaneously; the process for forming the third epitaxial layer and the fourth epitaxial layer comprises the following steps: and (5) an epitaxial growth process.
13. The method of forming a semiconductor structure of claim 12, wherein the epitaxial growth process parameters comprise: the gas being SiH4And GeH4Or SiH4And pH3The gas ion concentration ranges are: 4e 20-7 e 20/cubic centimeter.
14. The method of forming a semiconductor structure of claim 1, wherein after forming the third epitaxial layer and the fourth epitaxial layer, further comprising: simultaneously carrying out ion implantation in the first epitaxial layer, the third epitaxial layer, the second epitaxial layer and the fourth epitaxial layer; the implanted ion species comprise N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions, and the energy is as follows: 5 kilo electron volts to 15 kilo electron volts, the ion concentration range is: 4e 20-8 e 20/cubic centimeter, the injection angle is: 0-15 degrees; the P-type ions comprise boron ions or boron-fluorine ions, and the energy is as follows: 1.5 kiloelectron volts, with ion concentrations ranging from: 4e 20-8 e 20/cubic centimeter, the injection angle is: 0 to 15 degrees.
15. The method of forming a semiconductor structure of claim 1, wherein the first epitaxial layer and the second epitaxial layer have the same ion concentration.
16. The method of forming a semiconductor structure of claim 1, wherein the third epitaxial layer ion concentration is greater than the fourth epitaxial layer ion concentration.
17. The method of forming a semiconductor structure of claim 1, wherein the third epitaxial layer and the fourth epitaxial layer have the same ion concentration.
18. The method of forming a semiconductor structure of claim 1, wherein forming the first and second openings comprises: and etching partial substrates on two sides of the pseudo gate structure by taking the pseudo gate structure as a mask to form the first opening and the second opening.
19. The method of forming a semiconductor structure of claim 1, wherein the first epitaxial layer material comprises phosphorus silicon or silicon germanium; the second epitaxial layer material comprises phosphorus silicon or silicon germanium; the third epitaxial layer material comprises phosphorus silicon or silicon germanium; the fourth epitaxial layer material comprises phosphorus silicon or silicon germanium.
20. A semiconductor structure formed by the method of any of claims 1 to 19, comprising:
a substrate;
a gate structure on the substrate;
the first epitaxial layer is positioned in the first opening and the second epitaxial layer is positioned in the second opening in the substrate on two sides of the grid structure;
a third epitaxial layer positioned on the first epitaxial layer in the third opening between the gate structure and the first epitaxial layer;
and the fourth epitaxial layer is positioned on the second epitaxial layer in a fourth opening between the gate structure and the second epitaxial layer.
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