CN115863404A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN115863404A CN115863404A CN202211555226.9A CN202211555226A CN115863404A CN 115863404 A CN115863404 A CN 115863404A CN 202211555226 A CN202211555226 A CN 202211555226A CN 115863404 A CN115863404 A CN 115863404A
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Abstract
The invention provides a semiconductor structure and a manufacturing method thereof. The method comprises the following steps: providing a substrate, wherein the substrate comprises a first well region with a first type of conductivity; forming a gate structure on the first well region; forming first lightly doped regions in the first well region corresponding to regions on two sides of the gate structure; forming a side wall on the side wall of the grid structure; performing ion implantation on the first lightly doped region to form a source electrode and a drain electrode respectively; and carrying out small-oxygen sintering on the surface of the substrate to form a barrier layer for blocking the ion precipitation of the source electrode and the drain electrode in the first well region. According to the technical scheme, the side wall is formed on the side wall of the grid structure, the heavily doped source electrode and a channel right below the grid structure are initially separated, and the hot electron effect is inhibited; the barrier layer is formed by adopting small oxygen sintering and is used for blocking the ion precipitation of the source electrode and the drain electrode in the corresponding well region, and the medium stability at the silicon-silicon dioxide-polycrystalline silicon interface is enhanced.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for manufacturing the same.
Background
The preparation of high quality silicon-based interface states is very complex both from a compositional and process standpoint. The complex gate dielectric structure causes difficulty for researchers to determine the corresponding relation between dielectric components and preparation processes and dielectric properties, thereby objectively influencing the production and application of silicon-based dielectrics. Among other things, because the energy values at the silicon-silicon dioxide-Polysilicon (POLY) interface are located at discrete or continuous electronic energy levels or bands in the forbidden silicon band, they can exchange charges with the substrate semiconductor in a short time, especially with charge drift during high temperatures, causing fluctuations in transistor voltage. From the present point of view, this is one of the key reasons affecting the stability of the medium.
Therefore, it is an urgent technical problem to provide a semiconductor structure and a method for fabricating the same capable of enhancing the dielectric stability at the silicon-silicon dioxide-polysilicon interface.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a semiconductor structure and a method for manufacturing the same to enhance the dielectric stability at the silicon-silicon dioxide-polysilicon interface.
In order to solve the above problems, the present invention provides a method of manufacturing a semiconductor structure, the method comprising: providing a substrate, wherein the substrate comprises a first well region with first type conductivity; forming a gate structure on the first well region; forming first lightly doped regions in the first well region corresponding to regions on two sides of the gate structure; forming a side wall on the side wall of the grid structure; performing ion implantation on the first lightly doped region to form a source electrode and a drain electrode respectively; and carrying out small-oxygen sintering on the surface of the substrate to form a barrier layer for blocking the ion precipitation of the source electrode and the drain electrode in the first well region.
In some embodiments, the step of forming a gate structure over the first well region further comprises: forming a gate oxide layer on the surface of the first well region; forming a polycrystalline silicon layer on the surface of the gate oxide layer, and patterning the polycrystalline silicon layer to form the gate structure; and etching the gate oxide layer by taking the gate structure as a mask plate so as to expose part of the first well region.
In some embodiments, the step of forming a polysilicon layer on the surface of the gate oxide layer and patterning the polysilicon layer to form the gate structure further comprises: forming a light resistance layer on the surface of the polycrystalline silicon layer far away from the gate oxide layer; forming an anti-reflection layer on the surface of the light resistance layer far away from the gate oxide layer; and patterning the anti-reflection layer and the photoresist layer, and etching the polysilicon layer by using the patterned photoresist layer as a mask to form the gate structure.
In some embodiments, the step of forming a sidewall spacer on the sidewall of the gate structure further includes: pre-cleaning the side wall of the grid structure; sintering the side wall of the grid structure by adopting silicon nitride to form a mask layer; sintering the mask layer by adopting silicon dioxide to form a protective layer; and etching part of the protective layer to form the side wall on the side wall of the grid structure.
In some embodiments, the regions in the first well region corresponding to two sides of the gate structure form first lightly doped regions: lightly doping regions corresponding to two sides of the gate structure in the first well region by using doping elements with second type conductivity to form a first lightly doped region; the step of performing ion implantation on the first lightly doped region to form a source and a drain respectively further comprises: and heavily doping the first lightly doped region by using doping elements with second type conductivity to respectively form a source electrode and a drain electrode.
In some embodiments, the step of heavily doping the first lightly doped region further comprises: and carrying out annealing precleaning and annealing treatment on the first well region.
In some embodiments, the substrate further comprises a second well region of a second type of conductivity, the first well region and the second well region being isolated by a shallow trench isolation structure; the method further comprises: forming a gate structure on the second well region; forming second lightly doped regions in the second well region corresponding to regions on two sides of the gate structure; forming a side wall on the side wall of the grid structure on the second well region; performing ion implantation on the second lightly doped region to form a source electrode and a drain electrode respectively; and carrying out small-oxygen sintering on the surface of the substrate to form a barrier layer for blocking the ion precipitation of the source electrode and the drain electrode in the second well region.
In order to solve the above problem, the present invention also provides a semiconductor structure comprising: a substrate comprising a first well region having a first type conductivity; the grid structure is positioned on the first well region, and the side wall of the grid structure is provided with a side wall; the source electrode and the drain electrode are positioned in the first well region and correspond to regions on two sides of the grid structure; and the barrier layer is covered on the surfaces of the grid structure, the side wall and the source electrode and the drain electrode, and is formed by adopting small oxygen sintering so as to block the ion precipitation of the source electrode and the drain electrode in the first well region.
In some embodiments, the source and drain have a second type of conductivity.
In some embodiments, the substrate further comprises a second well region of a second type of conductivity, the first well region and the second well region being isolated by a shallow trench isolation structure; the semiconductor structure further includes: the grid structure is positioned on the second well region, and the side wall of the grid structure is provided with a side wall; the source electrode and the drain electrode are positioned in the second well region and correspond to regions on two sides of the grid structure; and the barrier layer is covered on the grid structure, the side wall and the surfaces of the source electrode and the drain electrode in the second well region, and is formed by adopting small oxygen sintering to prevent ions of the source electrode and the drain electrode from being separated out.
According to the technical scheme, the side wall is formed on the side wall of the grid structure, so that the channel right below the heavily doped source electrode and the channel right below the grid structure are initially separated, and the hot electron effect is inhibited; the barrier layer is formed by adopting small-oxygen sintering so as to be used for blocking the ion precipitation of the source electrode and the drain electrode in the corresponding well region and enhancing the medium stability at the silicon-silicon dioxide-polysilicon interface.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic illustration of a method of fabricating a semiconductor structure according to a first embodiment of the present invention;
FIGS. 2 to 7 are schematic views of device structures formed in the main steps in the first embodiment of the present invention;
FIG. 8 is a schematic illustration of a step in a method of fabricating a semiconductor structure according to a second embodiment of the present invention;
fig. 9 to 10 are schematic views of the structures of devices formed by partial steps in the second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In order to solve the problem of medium stability caused by charge exchange at the silicon-silicon dioxide-polysilicon interface in the prior art, embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof.
First, a method for fabricating a semiconductor structure according to an embodiment of the present invention will be described.
Please refer to fig. 1, which is a schematic diagram illustrating a method for fabricating a semiconductor structure according to a first embodiment of the present invention. As shown in fig. 1, the method for manufacturing a semiconductor structure according to this embodiment includes: step S11, providing a substrate, wherein the substrate 101 includes a first well region having a first type conductivity; step S12, forming a gate structure on the first well region; step S13, forming first lightly doped regions in the first well region corresponding to regions on two sides of the gate structure; step S14, forming a side wall on the side wall of the grid structure; step S15, carrying out ion implantation on the first lightly doped region to form a source electrode and a drain electrode respectively; and S16, carrying out small oxygen sintering on the surface of the substrate 101 to form a blocking layer for blocking the ion precipitation of the source electrode and the drain electrode in the first well region.
Referring to step S11 and fig. 2, a substrate is provided, and the substrate 101 includes a first well 3 having a first type conductivity. In some embodiments, a doping element having a first type conductivity is used to ion-implant a partial region of the substrate 1 to form a first well region 3 having the first type conductivity. For example, a part of the substrate 1 may be subjected to pentavalent ion implantation to form an N well, or a part of the substrate 1 may be subjected to trivalent ion implantation to form a P well.
Referring to step S12 and fig. 3, a gate structure is formed on the first well 3. The specific step S12 further includes: forming a gate oxide layer 5 on the surface of the first well region 3; forming a polycrystalline silicon layer on the surface of the gate oxide layer 5, and patterning the polycrystalline silicon layer to form the gate structure 6; and etching the gate oxide layer 5 by taking the gate structure 6 as a mask so as to expose part of the first well region 3.
In other embodiments, the step of forming a polysilicon layer on the surface of the gate oxide layer 5 and patterning the polysilicon layer to form the gate structure 6 further includes: forming a light resistance layer on the surface of the polycrystalline silicon layer far away from the gate oxide layer 5; forming an anti-reflection layer on the surface of the photoresist layer far away from the gate oxide layer 5; and patterning the anti-reflection layer and the photoresist layer, and etching the polysilicon layer by using the patterned photoresist layer as a mask to form the gate structure 6.
Referring to step S13 and fig. 4, first lightly doped regions 81 are formed in the first well region 3 corresponding to the regions on both sides of the gate structure 6. In some embodiments, the regions of the first well region 3 corresponding to the two sides of the gate structure 6 are lightly doped with a doping element having the second type conductivity to form the first lightly doped region 81. The doping element of the second type conductivity is different from the doping element of the first type conductivity, for example, the doping element of the first type conductivity is a pentavalent ion element, and the doping element of the second type conductivity is a trivalent ion element.
Referring to step S14 and fig. 5, a sidewall is formed on the sidewall of the gate structure 6. The specific step S14 further includes: pre-cleaning the side wall of the grid structure 6; sintering the side wall of the grid structure 6 by adopting silicon nitride to form a mask layer; sintering the mask layer by adopting silicon dioxide to form a protective layer; and etching part of the protective layer to form the side wall 9 on the side wall of the gate structure 6.
In step S15 and fig. 6, ion implantation is performed on the first lightly doped region 81 to form a source and a drain, respectively. The specific step S15 further includes: the first lightly doped region 81 is heavily doped with a doping element having a second type of conductivity to form the source electrode 11 and the drain electrode 12, respectively. In some embodiments, the step of heavily doping the first lightly doped region 81 further comprises: and annealing, pre-cleaning and annealing treatment are carried out on the first well region 3.
Referring to step S16 and fig. 7, a small oxygen sintering process is performed on the surface of the substrate 101 to form a blocking layer 13 for blocking the ion deposition of the source 11 and the drain 12 in the first well region 3.
Please refer to fig. 8, which is a process diagram illustrating a method for fabricating a semiconductor structure according to a second embodiment of the present invention. As shown in fig. 8, the method for manufacturing a semiconductor structure according to this embodiment includes: s21, providing a substrate, wherein the substrate comprises a first well region with first type conductivity and a second well region with second type conductivity, and the first well region and the second well region are isolated through a shallow trench isolation structure; s22, forming gate structures on the first well region and the second well region, respectively; s23, forming first lightly doped regions in the first well region corresponding to the regions on two sides of the gate structure, and forming second lightly doped regions in the second well region corresponding to the regions on two sides of the gate structure; s24, forming side walls on the side walls of the gate structures; s25, performing ion implantation on the first lightly doped region to form a source electrode and a drain electrode respectively, and performing ion implantation on the second lightly doped region to form a source electrode and a drain electrode respectively; and S26, carrying out small oxygen sintering on the surface of the substrate to form a blocking layer for blocking the ion precipitation of the source electrode and the drain electrode in the first well region and the ion precipitation of the source electrode and the drain electrode in the second well region.
In this embodiment, the substrate 101 further includes a second well region of a second type conductivity, and the first well region and the second well region are isolated by a shallow trench isolation structure.
Referring to step S21 and fig. 9, a substrate 101 is provided, in which the substrate 101 includes a first well region 3 having a first type conductivity and a second well region 4 having a second type conductivity, and the first well region 3 and the second well region 4 are isolated by a shallow trench isolation structure 2. Specifically, step S21 further includes: providing a substrate 1, and etching the substrate 1 to form a trench 7, as shown in part (a) of fig. 9: forming a gate oxide layer 5 on the sidewall and bottom of the trench 7 and the surface of the substrate 1, as shown in part (b) of fig. 9; forming a shallow trench isolation structure 2 in the trench 7, as shown in part (c) of fig. 9; the substrate 1 on both sides of the sti structure 2 is respectively ion implanted to form a first well region 3 with a first type conductivity and a second well region 4 with a second type conductivity, as shown in (d) of fig. 9. For example, a region of the substrate 1 on one side of the shallow trench isolation structure 2 is implanted with pentavalent ions to form a first well region 3 (N-well) having a first type of conductivity, and a region of the substrate 1 on the other side of the shallow trench isolation structure 2 is implanted with trivalent ions to form a second well region 4 (P-well) having a second type of conductivity. In other embodiments, before the etching the substrate 1 to form the trench, a field oxide layer is further formed on the substrate, where the field oxide layer is used to implement isolation of the substrate to avoid parasitic tubes.
The manufacturing process of steps S22 to S26 is substantially the same as that of steps S12 to S16 in the first embodiment. The resulting semiconductor structure is shown in fig. 10. Specifically, in this embodiment, the gate structures 6 are formed on the surfaces of the first well region 3 and the second well region 4, respectively, and a first lightly doped region 81 is formed in the first well region 3 corresponding to the regions on both sides of the gate structure 6, and a second lightly doped region 82 is formed in the second well region 4 corresponding to the regions on both sides of the gate structure 6. In some embodiments, the regions corresponding to the two sides of the gate structure 6 in the first well region 3 are lightly doped with a doping element (for example, a trivalent ion element) having a second type of conductivity to form the first lightly doped region 81; regions in the second well region 4 corresponding to two sides of the gate structure 6 are lightly doped with a doping element (e.g., a pentavalent ion element) having the first type conductivity to form the second lightly doped region 82. The source 11 and the drain 12 are formed in the second well region 4 according to the first embodiment of the present invention, which includes heavily doping the second lightly doped region 82 with a doping element having the first type conductivity to form the source 11 and the drain 12 in the second well region 4.
In this embodiment, a blocking layer 13 is formed by performing small oxygen sintering on the substrate surface to block the ion deposition of the source electrode 11 and the drain electrode 12 in the first well region 3 and the second well region 4, respectively. In other embodiments, after the forming of the barrier layer 13 by performing the small oxygen sintering on the surface of the substrate 101, removing a portion of the barrier layer 13, for example, the barrier layer 13 on top of the gate structure 6, is further included for performing a subsequent process.
According to the technical scheme, the side wall is formed on the side wall of the grid structure, so that the channel right below the heavily doped source electrode and the channel right below the grid structure are initially separated, and the hot electron effect is inhibited; the barrier layer 13 is formed by sintering with small oxygen to block the ion precipitation of the source electrode 11 and the drain electrode 12 in the first well region 3 and the second well region 4, so as to enhance the dielectric stability at the silicon-silicon dioxide-polysilicon interface.
Based on the same inventive concept, the invention also provides a semiconductor structure.
Referring to fig. 7, in the present embodiment, the semiconductor structure includes: substrate 101, gate structure 6, source 11, drain 12, and barrier layer 13. The base 101 includes a substrate 1 and a first well region 3 with a first type conductivity formed on the substrate 1. The gate structure 6 is located on the first well region 3, and a sidewall 9 is provided on a sidewall of the gate structure 6. The source 11 and the drain 12 are located in the first well region 3 corresponding to the two sides of the gate structure 6. The blocking layer 13 covers the gate structure 6, the side walls 9, and the surfaces of the source electrode 11 and the drain electrode 12, and the blocking layer 13 is formed by sintering small oxygen and is used for blocking the ion precipitation of the source electrode 11 and the drain electrode 12 in the first well region 3. The formation of the semiconductor structure is described in the foregoing, and is not repeated herein.
In some embodiments, the source 11 and drain 12 have a second type of conductivity.
In some embodiments, a part of the substrate 1 is ion-implanted with pentavalent ions to form a first well region 3 with a first type conductivity, and then the region of the first well region 3 corresponding to the two sides of the gate structure 6 is lightly doped with a doping element (e.g. trivalent ion element) with a second type conductivity to form the first lightly doped region 81, and then the first lightly doped region 81 is heavily doped with a doping element (e.g. trivalent ion element) with a second type conductivity to form the source 11 and the drain 12 with a second type conductivity, respectively.
Referring to fig. 10, in the present embodiment, the semiconductor structure includes: a substrate 101, a plurality of gate structures 6, a source 11, a drain 12, and a barrier layer 13. The substrate 101 includes a substrate 1, and a first well region 3 having a first type conductivity and a second well region 4 having a second type conductivity formed on the substrate 1, wherein the first well region 3 and the second well region 4 are isolated by a shallow trench isolation structure 2. The first well region 3 and the second well region 4 are both provided with gate structures 6, and the side wall of each gate structure 6 is provided with a side wall 9. The first well region 3 is provided with a source electrode 11 and a drain electrode 12 corresponding to regions on two sides of the gate structure 6, and the second well region 4 is provided with a source electrode 11 and a drain electrode 12 corresponding to regions on two sides of the gate structure 6. The blocking layer 13 covers the gate structure 6 on the first well region 3, the sidewall 9, and the surfaces of the source 11 and the drain 12 in the first well region 4; and the gate structure 6, the sidewall 9, and the surfaces of the source 11 and the drain 12 in the second well region 4 are covered on the second well region 4. The barrier layer 13 is formed by small oxygen sintering for blocking the ion deposition of the corresponding source electrode 11 and drain electrode 12.
Experiments show that the semiconductor structure with the barrier layer 13 formed in the above manner has greatly improved resistance concentration, so that the dielectric stability at the silicon-silicon dioxide-polysilicon interface of the semiconductor structure is stronger.
According to the technical scheme, the side wall is formed on the side wall of the grid structure, the heavily doped source electrode and a channel right below the grid structure are initially separated, and the hot electron effect is inhibited; the barrier layer is formed by adopting small-oxygen sintering so as to be used for blocking the ion precipitation of the source electrode and the drain electrode in the corresponding well region and enhancing the medium stability at the silicon-silicon dioxide-polysilicon interface.
It is noted that, herein, relational terms such as second and third, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the statement that there is an element defined by the word "further comprising … …" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element. All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on differences from other embodiments.
The above description is only for the preferred embodiment of the present invention and should not be taken as limiting the scope of the present invention. It should be noted that modifications and adaptations can be made by those skilled in the art without departing from the principle of the present invention, and should be considered as within the scope of the present invention.
Claims (10)
1. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate, wherein the substrate comprises a first well region with first type conductivity;
forming a gate structure on the first well region;
forming first lightly doped regions in the first well region corresponding to regions on two sides of the gate structure;
forming a side wall on the side wall of the grid structure;
performing ion implantation on the first lightly doped region to form a source electrode and a drain electrode respectively;
and carrying out small-oxygen sintering on the surface of the substrate to form a barrier layer for blocking the ion precipitation of the source electrode and the drain electrode in the first well region.
2. The method of claim 1, wherein the step of forming a gate structure over the first well region further comprises:
forming a gate oxide layer on the surface of the first well region;
forming a polycrystalline silicon layer on the surface of the gate oxide layer, and patterning the polycrystalline silicon layer to form the gate structure;
and etching the gate oxide layer by taking the gate structure as a mask plate so as to expose part of the first well region.
3. The method of claim 2, wherein said steps of forming a polysilicon layer on a surface of said gate oxide layer and patterning said polysilicon layer to form said gate structure further comprise:
forming a light resistance layer on the surface of the polycrystalline silicon layer far away from the gate oxide layer;
forming an anti-reflection layer on the surface of the light resistance layer far away from the gate oxide layer;
and patterning the anti-reflection layer and the photoresist layer, and etching the polysilicon layer by using the patterned photoresist layer as a mask to form the gate structure.
4. The method of claim 1, wherein the step of forming a sidewall spacer on the sidewall of the gate structure further comprises:
pre-cleaning the side wall of the grid structure;
sintering the side wall of the grid structure by adopting silicon nitride to form a mask layer;
sintering the mask layer by adopting silicon dioxide to form a protective layer;
and etching part of the protective layer to form the side wall on the side wall of the grid structure.
5. The method of claim 1,
forming first lightly doped regions in the first well region corresponding to regions on two sides of the gate structure: lightly doping regions corresponding to two sides of the gate structure in the first well region by using doping elements with second type conductivity to form a first lightly doped region;
the step of performing ion implantation on the first lightly doped region to form a source and a drain respectively further comprises: and heavily doping the first lightly doped region by using doping elements with second type conductivity to respectively form a source electrode and a drain electrode.
6. The method of claim 5, wherein the step of heavily doping the first lightly doped region is further followed by:
and carrying out annealing precleaning and annealing treatment on the first well region.
7. The method of claim 1, wherein the substrate further comprises a second well region of a second type of conductivity, the first well region and the second well region being isolated from each other by a shallow trench isolation structure; the method further comprises:
forming a gate structure on the second well region;
forming second lightly doped regions in the second well region corresponding to regions on two sides of the gate structure;
forming a side wall on the side wall of the grid structure on the second well region;
performing ion implantation on the second lightly doped region to form a source electrode and a drain electrode respectively;
and performing small-oxygen sintering on the surface of the substrate 101 to form a blocking layer for blocking the ion precipitation of the source and the drain in the second well region.
8. A semiconductor structure, comprising:
a substrate comprising a first well region having a first type of conductivity;
the grid structure is positioned on the first well region, and the side wall of the grid structure is provided with a side wall;
the source electrode and the drain electrode are positioned in the first well region and correspond to regions on two sides of the grid structure;
and the barrier layer is covered on the surfaces of the grid structure, the side wall and the source electrode and the drain electrode, and is formed by adopting small oxygen sintering so as to block the ion precipitation of the source electrode and the drain electrode in the first well region.
9. The semiconductor structure of claim 8, wherein the source and drain have a second type of conductivity.
10. The semiconductor structure of claim 8, wherein the substrate further comprises a second well region of a second type of conductivity, the first well region being isolated from the second well region by a shallow trench isolation structure; the semiconductor structure further includes:
the grid structure is positioned on the second well region, and the side wall of the grid structure is provided with a side wall;
the source electrode and the drain electrode are positioned in the second well region and correspond to regions on two sides of the grid structure;
and the barrier layer is covered on the grid structure, the side wall and the surfaces of the source electrode and the drain electrode in the second well region, and is formed by adopting small oxygen sintering to prevent ions of the source electrode and the drain electrode from being separated out.
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