CN110265359B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN110265359B
CN110265359B CN201910568036.2A CN201910568036A CN110265359B CN 110265359 B CN110265359 B CN 110265359B CN 201910568036 A CN201910568036 A CN 201910568036A CN 110265359 B CN110265359 B CN 110265359B
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oxide layer
layer
gate oxide
gate
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CN110265359A (en
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许文山
董洁琼
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

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  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the same, the method comprising the steps of: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, and the substrate is provided with a high-voltage device area; forming a gate oxide layer on the high-voltage device region; defining a logic device region in the substrate; forming oxide layers on the surfaces of the high-voltage device area and the logic device area, wherein the thickness of the oxide layers is smaller than that of the gate oxide layers; forming a lightly doped drain region in the substrate at the side of the gate oxide layer; and forming a source electrode and a drain electrode in the lightly doped drain region under the oxide layer. The semiconductor device provided by the invention has good performance and is formed by combining the high-voltage device and the low-voltage logic device.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device combining a high voltage device region and a low voltage device region and a method for manufacturing the same.
Background
With the continuous development of semiconductor process technology, in a 3D NAND process, a symmetric or asymmetric high-voltage Double-Diffused Drain MOS (Double Diffused Drain MOS) device is often used to control a high-voltage signal in a peripheral circuit of a memory cell. However, in order to increase the I/O speed of the memory, for example, to make the speed thereof greater than 1G, a faster low voltage device is also required in the peripheral circuit. Therefore, a high voltage device and a low voltage device need to be combined in a chip.
The conventional process generally includes forming a polysilicon Gate (Poly Gate) of a semiconductor device, sequentially forming a lightly Doped Drain (L lightly Doped Drain, L DD) in a high-voltage device, forming a lightly Doped Drain in a low-voltage device, performing well region ion implantation, forming silicide, and the like, and performing a subsequent process, wherein when the Gate length of the low-voltage device is 65nm or less, the process may cause the following problems:
1. after the gate etching is completed, a residual oxide layer with a certain thickness is arranged above the high-voltage device region, and when the high-voltage device region is lightly doped, impurities can enter the gate oxide layer to influence the performance of the device. In addition, because the energy for forming the ultra-shallow junction is low, the residual oxide layer above the source-drain heavily doped region cannot be penetrated, and therefore the ion implantation of the region is influenced.
2. In order to reduce the light doping energy of the high-voltage device region, the residual oxide layer of the high-voltage device region can be thinned by using a mask after the gate etching is completed, but the silicon loss of the low-voltage device region can be caused and the problem of process control can be caused.
3. As the size of low voltage devices is reduced, for example, to 45nm logic process, PN junction is becoming shallower, the remaining oxide layer in the high voltage device region needs to be thinned, and when the thickness is thinned to 0A, the high voltage device may generate implant punch-through effect.
4. The L DD implant for the high voltage device region requires more Thermal Budget (Thermal Budget) to increase the breakdown voltage, and there is not enough Thermal Budget for a 45nm logic process to do so.
Disclosure of Invention
The invention aims to provide a semiconductor device combining a high-voltage device and a low-voltage logic device with good performance.
The present invention is directed to a method for manufacturing a semiconductor device, which includes the steps of: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, and the substrate is provided with a high-voltage device area; forming a gate oxide layer on the high-voltage device region; defining a logic device region in the substrate; forming oxide layers on the surfaces of the high-voltage device area and the logic device area, wherein the thickness of the oxide layers is smaller than that of the gate oxide layers; forming a lightly doped drain region in the substrate at the side of the gate oxide layer; and forming a source electrode and a drain electrode in the lightly doped drain region under the oxide layer.
In an embodiment of the present invention, after a lightly doped drain region is formed in the substrate at the side of the gate oxide layer, the gate oxide layer partially covers the lightly doped region.
In an embodiment of the invention, the lightly doped drain region has a side wall located below the gate oxide layer, and the side wall in the width direction of the gate oxide layer is 0.1-1 μm away from the side wall of the lightly doped drain region.
In an embodiment of the present invention, after the logic device region is defined in the substrate, an isolation structure for isolating the high-voltage device region and the logic device region is further formed.
In an embodiment of the present invention, in the step of forming the oxide layer on the surfaces of the high voltage device region and the logic device region, the oxide layer does not cover the gate oxide layer.
In an embodiment of the present invention, before forming the lightly doped drain region in the substrate at the side of the gate oxide layer, the method further includes: covering a protective layer on the logic device area; and forming a gate layer on the gate oxide layer.
In an embodiment of the present invention, the step of forming a source and a drain in the lightly doped drain region under the oxide layer includes: ion implantation is performed through the oxide layer.
In an embodiment of the present invention, the gate oxide layer does not cover the source and the drain when the source and the drain are formed.
In an embodiment of the invention, the thickness of the gate oxide layer is 10-50 nm.
The present invention also provides a semiconductor device including: a substrate; a logic device formed in the substrate; and the high-voltage device comprises a grid structure positioned on the substrate, the grid structure comprises a grid oxide layer, a grid layer positioned on the grid oxide layer and side walls positioned on two sides of the grid layer in the width direction, and the grid oxide layer protrudes out of the side walls in the width direction.
In an embodiment of the invention, the thickness of the gate oxide layer is 10-50 nm.
In an embodiment of the present invention, the high voltage device further includes a source, a drain, and a lightly doped drain, the lightly doped drain is located in the substrate at the side of the gate structure, and the source and the drain are located in the lightly doped drain.
In an embodiment of the invention, the lightly doped drain region has a side wall located below the gate oxide layer, and the side wall in the width direction of the gate oxide layer is 0.1-1 μm away from the side wall of the lightly doped drain region.
In an embodiment of the present invention, an isolation structure between the logic device and the high voltage device is further included.
In one embodiment of the present invention, the substrate has a high voltage well in which the high voltage device is formed and a low voltage well in which the logic device is formed.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:
1. respectively carrying out grid etching on the high-voltage device area and the low-voltage device area, and using a thicker hard mask when carrying out grid etching on the high-voltage device area, so that doped ions are prevented from entering a grid layer and a channel in the injection process of forming a low-doped drain area in the high-voltage device area;
2. the length of the gate oxide layer is changed, so that the gate oxide layer does not cover the drain electrode and the source electrode in the lightly doped drain region, and the formation of an ultra-shallow junction is facilitated;
3. the low-doped drain region is formed after the grid electrode of the high-voltage device region is formed, and the junction of the high-voltage device region can be gradually changed by using the heat of secondary oxidation of the grid electrode.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a schematic diagram of a semiconductor device having a high voltage device region and a low voltage device region;
fig. 2 is an exemplary flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 3 is one of the schematic structural diagrams of a semiconductor device in the manufacturing process according to an embodiment of the present invention;
FIGS. 4A-4D are schematic structural diagrams of a semiconductor device during formation of a gate oxide over a high voltage device region in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of a semiconductor device having a logic device region defined in a substrate in accordance with one embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a semiconductor device having an oxide layer formed on the surfaces of a high voltage device region and a logic device region according to an embodiment of the present invention;
FIGS. 7A-7D are schematic diagrams illustrating the structure of a semiconductor device during the formation of lightly doped drain regions in accordance with one embodiment of the present invention;
FIGS. 8A-8B are schematic diagrams illustrating the structure of a semiconductor device during processing of a logic device region in accordance with an embodiment of the present invention;
fig. 9A-9D are schematic views of cross-sectional structures of a semiconductor device according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.
Fig. 1 is a schematic diagram of a semiconductor device having a high voltage device region and a low voltage device region. Referring to fig. 1, the semiconductor device 100 includes a substrate 101, and a high voltage device region 110 and a low voltage device region 120 formed in the substrate 101. The high-voltage device region 110 and the low-voltage period region 120 are separated by a Shallow Trench Isolation (STI) region 130.
As shown in fig. 1, the shallow trench isolation region 130 isolates the high voltage device region 110 from the low voltage device region 120. The high voltage device region 110 and the low voltage device region 120 are Active Areas (AA) to facilitate the subsequent formation of source, drain and gate electrodes thereof in the respective Active regions.
The processes for forming the shallow trench isolation region 130 may include isolation oxide deposition, mask layer deposition (e.g., nitride), trench formation by etching, filling of trenches with deposited insulating material (e.g., oxide), planarization, and the like.
Next, a gate oxide 112/122 is formed on the upper surface of the substrate 101, a polysilicon film is deposited, the gate oxide 112/122 and the polysilicon film are etched by using a mask to form a gate 111/121, and then L DD processes are performed in the high-voltage device region 110 and the low-voltage device region 120, respectively, to form a source/drain region.
When the gate length of the low voltage device is required to be 65nm or less, the above process may have the following problems:
as shown in fig. 1, after the gate etching process is completed, the thickness of the gate oxide layer 112 of the high-voltage device region 110 is about 400A, the thickness of the gate oxide layer 122 of the low-voltage device region 120 is about 20A, the thickness of the thin film of the gate 111 in the high-voltage device region 110 is generally less than 1050A, and the ion implantation depth of the high-voltage region L DD is 1000-2000A, so that ions enter the gate oxide layer 112 during the high-voltage region L DD, which affects the performance of the device.
In order to solve the above problem, some solutions are to thin the gate oxide layer 112 on the high-voltage device region 110 to about 100A by using mask etching after the gate 111 is formed, but since the gate oxide layer 112 of the low-voltage device region 110 is thinned at the same time, the substrate of the low-voltage device region 110 may be etched, and silicon loss may occur.
It should be noted that the above numbers are given as examples for illustration and are not intended to limit the actual situation.
As the gate length requirement for the low voltage device continues to decrease, for example, to 45nm, the thickness of the gate 111/121 becomes smaller, the gate oxide layer 112 of the high voltage device region 110 needs to be thinned further, and if the thickness is thinned to 0A, the injection punch-through effect may occur in the L DD of the high voltage device region 110.
Furthermore, in 45nm logic processes, there is no Thermal Budget (Thermal Budget) greater than 700 degrees other than pulse annealing (Spike Anneal) and laser annealing (L ase Anneal) after gate etch, whereas L DD for high voltage device region 110 requires more Thermal Budget, thus, also causing insufficient Thermal Budget.
Fig. 2 is an exemplary flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 2, the manufacturing method includes the steps of:
step 210, a semiconductor structure is provided, the semiconductor structure including a substrate having a high voltage device region.
In step 210, the substrate in the provided semiconductor structure may be a variety of semiconductor materials known to those skilled in the art, such as a Silicon substrate (Si), a Germanium substrate (Ge), a Silicon Germanium substrate (SiGe), a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), etc. The silicon substrate may include a single crystal silicon substrate, a polycrystalline silicon substrate, or the like. As for the single crystal silicon substrate, a P-type single crystal silicon substrate or an N-type single crystal silicon substrate can be classified according to the type of ions to be doped. The P-type monocrystalline silicon substrate is formed by doping P-type doping ions, such as indium ions, boron ions, gallium ions, aluminum ions, boron fluoride ions and the like, in the monocrystalline silicon substrate; the N-type single crystal silicon substrate is formed by doping a single crystal silicon substrate with N-type dopant ions such as arsenic ions, phosphorus ions, antimony ions, and the like.
Fig. 3 is one of the schematic structural diagrams of a semiconductor device in the manufacturing process according to an embodiment of the present invention. Referring to fig. 3, the substrate 301 is a P-type single crystal silicon substrate, and a high voltage device region 310 is formed in the substrate 301. High-voltage P-well regions 311 and high-voltage N-well regions 312 are formed in the high-voltage device region 310 near the upper surface of the substrate 301. The formation of the high-voltage P-well region 311 is to implant P-type doped ions into the region by using an ion implantation process; the hvnw 312 is formed by implanting N-type dopant ions in this region using an ion implantation process.
In some embodiments, since the substrate 301 is a P-type single crystal silicon substrate doped with P-type dopant ions, the hvpwell region 311 need not be formed separately. In these embodiments, in the high-voltage device region 310, the regions other than the high-voltage N-well region 312 may be considered as high-voltage P-well regions 311.
The following steps will be described with reference to a P-type single crystal silicon substrate shown in fig. 3 as an example of a method for manufacturing a semiconductor device of the present invention. It is to be understood that the drawings presented in this specification are for purposes of illustration only and are not intended to limit the scope or application of the present invention. Those skilled in the art can make corresponding adjustments on other types of substrates to achieve the same technical effect according to the idea of the present invention.
A gate oxide layer is formed over the high voltage device region, step 220.
The gate oxide layer formed over high-voltage device region 310 is for the purpose of subsequently forming a gate layer over the gate oxide layer, which may serve as a gate for a high-voltage device in a semiconductor device. Fig. 4A-4D are schematic structural diagrams of a semiconductor device during formation of a gate oxide layer over a high voltage device region in accordance with an embodiment of the present invention. Referring to fig. 4A, a barrier layer 410 is first deposited on the upper surface of the substrate 301. Common barrier layer 410 materials may include silicon nitride or silicon oxynitride. The process of depositing the barrier layer 410 may use chemical deposition, physical deposition, thermal oxidation, and the like. In the present embodiment, the material of the barrier layer is silicon nitride, and the thickness of the barrier layer is 100 to 500A. Next, a patterned photoresist layer 420 is deposited on the top surface of the barrier layer 410. The pattern on the photoresist layer 420 is used to define the area where the gate oxide needs to be formed, as shown by the gaps in the photoresist layer 420 in fig. 4A.
Referring to fig. 4B, the barrier layer 410 is etched using the photoresist layer 420 as a mask to open the area where the gate oxide layer needs to be grown, wherein the area 411 corresponds to the hvpwell region 311 in the hvpd region 310 and the area 412 corresponds to the hvnwell region 312 in the hvpd region 310. Regions 411 and 412 will be used to grow the gate oxide. Referring to fig. 4B, after the etching of the barrier layer 410 is completed, the photoresist layer 420 is cleaned away, exposing the upper surface of the barrier layer 410.
It should be noted that, in the present embodiment, the method for manufacturing a semiconductor structure of the present invention is described by taking one high-voltage device region 310 as an example, in an actual implementation, a plurality of high-voltage device regions 310 may be included on the substrate 301, and the steps in the method may be performed simultaneously on the plurality of high-voltage device regions 310.
Referring to fig. 4C, gate oxide layers 431 and 432 are generated at regions 411 and 412. In the present embodiment, the gate oxide layers 431 and 432 may be silicon oxide layers formed using a Thermal Oxidation (RTO) method or an In-situ steam Generation (ISSG) method. As shown in fig. 4C, the gate oxide 431/432 is produced to a thickness substantially equal to the thickness of the barrier layer 410. In some embodiments, gate oxide 431/432 has a thickness of 10-50 nm.
The interface between the gate oxide 431/432 and its adjacent barrier layer 410 is not an ideal vertical interface as shown in fig. 4C, but rather a graded interface. As shown in the enlarged partial schematic view of the region R, the material of the portion of the gate oxide 431/432 at the interface penetrates into the barrier layer 410 through the vertical interface.
Referring to fig. 4D, the remaining barrier layer 410 shown in fig. 4C is cleaned away, leaving gate oxide 431/432 in the relevant area of the upper surface of high voltage device region 310.
In step 230, a logic device region is defined in the substrate.
Fig. 5 is a schematic diagram of a semiconductor device having a logic device region defined in a substrate in accordance with an embodiment of the present invention. Referring to fig. 5, an area adjacent to the high voltage device region 310 is defined as a logic device region 510 in the substrate 301. The logic device region 510 is used to form other logic circuits in the peripheral circuits. In the present embodiment, the logic device region 510 is used to form a low voltage logic device in the peripheral circuit to increase the I/O speed of the memory.
As shown in fig. 5, a logic P well region 511 and a logic N well region 512 are formed in the logic device region 510 in regions near the upper surface of the substrate 301. The logic P well 511 is formed by implanting P-type doped ions into the logic P well 511 by an ion implantation process; logic N-well region 512 is formed by implanting N-type dopant ions into the region using an ion implantation process.
In some embodiments, since substrate 301 is a P-type single crystal silicon substrate doped with P-type dopant ions, logic P-well region 511 need not be formed separately. In these embodiments, in logic device region 510, the regions other than logic N-well region 512 may be considered logic P-well regions 511.
As shown in fig. 5, hvpwell region 311, hvnwell region 312, logic pwell region 511 and logic nwell region 512 are all active areas where the body of the transistor is located, and these active areas will be used to form the source, drain and gate of the transistor in subsequent steps.
In some embodiments, isolation structures 520 are also formed between each active region. The isolation structure 520 not only isolates the high voltage device region 310 from the logic device region 510, but also isolates the active regions in the respective regions to take advantage of the mutual independence between the devices formed on the respective active regions. In the present embodiment, a shallow trench isolation process STI is used to form each isolation structure 520. The shallow trench isolation process may include isolation oxide deposition, mask layer deposition (e.g., nitride), trench formation by etching, trench filling with deposited insulating material (e.g., oxide), planarization, and the like.
The isolation structure 520 may be formed before or after the formation of the high voltage device region 310 and the logic device region 510, or may be formed between the processes of forming the high voltage device region 310 and the logic device region 510.
Since the high-voltage device region 310 and the logic device region 510 are formed on the same substrate 301, ideally, the upper surfaces of the formed hvp-well region 311, hvn-well region 312, logic P-well region 511, and logic N-well region 512 are at the same horizontal plane.
In some embodiments, step 230 further includes adjusting the threshold voltage of logic device region 510 by an ion implantation process when forming logic P-well region 511 and logic N-well region 512.
And 240, forming oxide layers on the surfaces of the high-voltage device area and the logic device area, wherein the thickness of the oxide layers is smaller than that of the gate oxide layers.
It should be noted that after step 230 is completed, cleaning is performed on the upper surfaces of the high voltage device region 310 and the logic device region 510 to facilitate the formation of the oxide layer in step 240.
Fig. 6 is a schematic structural diagram of a semiconductor device in which an oxide layer is formed on the surfaces of a high-voltage device region and a logic device region according to an embodiment of the present invention. Referring to fig. 6, an oxide layer 610 is formed on the upper surfaces of the high voltage device region 310 and the logic device region 510. It is noted that in high voltage device region 310, layer oxide 610 does not overlie gate oxide 431/432, but rather only overlies the exposed well region in high voltage device region 310. The layer oxide 610 has a thickness less than the thickness of the gate oxide 431/432. The material of the oxide layer 610 may be silicon oxide or the like. The formation process of the oxide layer 610 may include, but is not limited to, a process technique such as thermal oxidation growth (RTP), in-situ moisture growth (ISSG), and the like.
Step 250, forming a lightly doped drain region in the substrate at the side of the gate oxide layer.
In some embodiments, the steps of forming the lightly doped drain region may further include forming a protective layer over the logic device region 510 and forming a gate layer over the gate oxide layer 431/432.
Fig. 7A-7D are schematic structural diagrams of a semiconductor device during formation of lightly doped drain regions in accordance with an embodiment of the present invention. Referring to fig. 7A, a gate layer 710 and a mask layer 720 are sequentially deposited on the upper surfaces of the high-voltage device region 310 and the logic device region 510. Wherein the gate layer 710 is used to form the gate of the corresponding device in each active region, and the mask layer 720 is used to perform a patterned etch on the gate layer 710 to form the desired gate.
In some embodiments, after the gate layer 710 is formed, a pre-doping step is further included in the gate layer 710 to improve the N-type polysilicon depletion effect. Thereafter, a mask layer 720 is formed over the gate layer 710.
In one embodiment, the gate layer 710 to be formed is a polysilicon gate. A polysilicon film may be formed on the upper surfaces of the high voltage device region 310 and the logic device region 510 as the gate layer 710 by chemical vapor deposition.
In one embodiment, the thickness of the gate layer 710 is 800-1100A, and the thickness of the mask layer 720 is about 800A. The material forming the mask layer 720 may be silicon nitride as a hard mask.
Referring to fig. 7B, high-voltage device region 310 is etched using patterned masking layer 720 to form gate layer 711/712 corresponding to high-voltage P-well region 311 and high-voltage N-well region 312, and the area above logic device region 510 is not etched. Gate layer 713 and mask layer 723, overlying logic device region 510, together form a protective layer that protects logic device region 510 when a lightly doped drain is subsequently formed in high voltage device region 310.
Referring to fig. 7C, lightly doped drain regions 731/732 are formed in the substrate beside the gate oxide layer 431/432 on the upper surface of the high voltage device region 310, respectively. Wherein two lightly doped drain regions 731 are formed in the substrate at two sides of the gate oxide layer 431, respectively, and the type of doping ions in the two lightly doped drain regions 731 is opposite to the type of doping ions in the substrate. In the embodiment shown in fig. 7C, the substrate beside the gate oxide layer 431 is the hvp well region 311, wherein P-type doped ions are doped, and the doped ions in the lightly doped drain region 731 are N-type. Similarly, two lightly doped drain regions 732 are formed in the substrate at two sides of the gate oxide layer 432, respectively, and the type of the dopant ions in the lightly doped drain regions 732 is opposite to the type of the dopant ions in the substrate where the lightly doped drain regions are located. In the embodiment shown in fig. 7C, the substrate on which the side of the gate oxide layer 432 is located is the hvnw region 312, wherein N-type dopant ions are doped, and the dopant ions in the lightly doped drain region 732 are P-type.
As shown in fig. 7C, the hvnw region 312 is separated from the hvnw region 311 by a spacer structure 520, so the lightly doped drain regions 731/732 between two adjacent regions are isolated from each other.
Note that only one mask layer 720 is shown in fig. 7A-7C, however, in this embodiment, actually, the lightly doped drain region 731 is formed in the high-voltage P-well region 311 and the lightly doped drain region 732 is formed in the high-voltage N-well region 312 in two steps, which need to be performed separately using two mask layers. In other embodiments, the lightly doped drain region 731 may be formed only in the hvp-well region 311, or the lightly doped drain region 732 may be formed only in the hvn-well region 312, so that only one mask layer is needed, and one mask layer and corresponding process steps may be saved.
Ideally, the width of the channel between two lightly doped drain regions formed in the same well region is equal to the width of the gate layer above the lightly doped drain regions due to the mask layer 710. For example, the channel width between two lightly doped drain regions 731 generated in the high-voltage P-well region 311 is equal to the width of the gate layer 711 above it.
Fig. 7D shows that the remaining mask layer 720 is further removed on the basis of the previous steps. It is to be understood that the step of forming the gate layer 711/712 may further include steps of cleaning, removing photoresist, performing secondary oxidation on the gate layer 711/712, and forming a polysilicon gate after the etching is completed.
Referring to fig. 7D, the lightly doped drain region has a sidewall below the gate oxide layer, and the sidewall in the width direction of the gate oxide layer is 0.1-1 μm away from the sidewall of the lightly doped drain region. Taking the lightly doped drain region 731 as an example, the sidewall of the lightly doped drain region 731 under the gate oxide layer 431 is s1, the sidewall of the gate oxide layer 431 in the width direction thereof is s2, and the distance between the sidewalls s1 and s2 is D, as shown in fig. 7D. In the examples of the present invention, d ranges from 0.1 to 1 μm.
Fig. 8A-8B are schematic structural diagrams of a semiconductor device during processing of a logic device region in an embodiment of the invention.
Referring to fig. 8A, a mask layer 810 is deposited on the upper surfaces of the high voltage device region 310 and the logic device region 510. The mask layer 810 may be a hard mask layer composed of an apf (advanced Patterning film) film and a silicon oxynitride DARC (dielectric independent-Reflection Coating). In this embodiment, the thickness of the APF film can be 1100A, and the thickness of the silicon oxynitride DARC can be 320A.
Referring to fig. 8B, logic device region 510 is etched using a patterned mask (not shown) to obtain gate layer 821/822 of logic device region 510. In the present embodiment, gate layer 821 corresponds to logic P-well region 511 of logic device region 510, and gate layer 822 corresponds to logic N-well region 512 of logic device region 510.
After the etching of the gate layer 821/822 is completed, the steps of removing the residual mask layer 810, cleaning the plasma, removing the photoresist, and performing a second oxidation on the gate layer 821/822 are included. This portion of the thermal budget can be utilized by the high voltage device.
In step 260, a source and a drain are formed in the lightly doped drain region under the oxide layer.
Fig. 9A-9D are schematic views of cross-sectional structures of a semiconductor device according to an embodiment of the invention. Where fig. 9A shows a high voltage NMOS device, fig. 9B shows a high voltage PMOS device, fig. 9C shows a low voltage NMOS device, and fig. 9D shows a low voltage PMOS device.
Step 260 is described below with reference to fig. 9A as an example. Referring to fig. 9A, the semiconductor device includes a high-voltage P-well region 311 formed in a high-voltage device region 310 and two lightly doped drain regions 731 therein. There is an isolation structure 520 at each end of the hvpwell region 311 so that the area between the two isolation structures 520 can form a separate device. The two lightly doped drain regions 731 are respectively located in the substrate at two side edges of the gate oxide layer 431, and the lightly doped drain regions 731 have side walls located below the gate oxide layer 431, and the distance from the side walls of the gate oxide layer 431 in the width direction to the side walls of the lightly doped drain regions 731 is 0.1-1 μm. The ideal distance between the two lightly doped drain regions 731 is equal to the width of the gate layer 711 of the semiconductor device.
The source 910 and the drain 910 of the MOS device are formed in the lightly doped drain region 731 by ion implantation. It will be appreciated that the source 910 and drain 910 electrodes located at opposite ends of the gate oxide layer 431 are similar in structure, with one serving as the source and the other as the drain.
Referring to fig. 6 and 8B, the step of forming the source electrode 910 and the drain electrode 910 further includes performing ion implantation through the oxide layer 610. The thickness of the oxide layer 610 is smaller than that of the gate oxide layer 431, and after the foregoing steps, the thickness of the oxide layer 610 is gradually reduced, so the oxide layer 610 is not shown in fig. 9A. In forming the ultra shallow junctions, the source 910 and drain 910 may be formed in the lightly doped drain 731 through the oxide layer 610, even at a lower energy.
In step 260, the source 910 and drain 910 are formed by implanting ions of the same type as the lightly doped drain 731. In the present embodiment, the doping ions of the lightly doped drain region 731 are N-type, and the ions implanted into the lightly doped drain region 731 in this step are also N-type. The semiconductor device shown in fig. 9A is therefore an NMOS device.
Referring to fig. 9A, the gate oxide layer 431 does not cover the source electrode 910 and the drain electrode 910. That is, neither the source electrode 910 nor the drain electrode 910 formed at this step is covered by the gate oxide layer 431 and has a certain distance from the gate oxide layer 431. Thus, the process of ion implantation into the source electrode 910 and the drain electrode 910 is not hindered by the gate oxide layer 431.
In some embodiments, before forming the source and the drain in step 260, forming a sidewall spacer 920 on both sides of the gate layer 711 is further included to prevent the source-drain implant from being too close to the channel, which may cause the channel to be too short and even cause source-drain connection. The process for forming the sidewall spacers 920 may use a sidewall formation process familiar to those skilled in the art. The gate oxide layer 431 protrudes from the sidewall spacers 920 in the width direction.
After the source electrode 910 and the drain electrode 910 are formed, a process of forming a silicide (Salicide)911 on the upper surfaces of the source electrode 910 and the drain electrode 910 and a silicide 921 on the gate layer 711 is also included. This process is performed by a Salicide process familiar to those skilled in the art. As shown in fig. 9A, the silicide 911 formed on the upper surfaces of the source 910 and the drain 910 has a width smaller than that of the source 910 or the drain 910; the width of the silicide 921 formed over the gate layer 711 is smaller than that of the gate layer 711.
The semiconductor device shown in fig. 9B has a similar structure to that shown in fig. 9A, but there is also a difference. Referring to fig. 9B, the semiconductor device includes a high-voltage nwell region 312 formed in the high-voltage device region 310 and two lightly doped drain regions 732 therein. There is an isolation structure 520 at each end of the hvnw 312 so that the area between the isolation structures 520 can form a separate device. The two lightly doped drain regions 732 are respectively located in the substrate at both side edges of the gate oxide layer 432, and the lightly doped drain regions 732 have sidewalls located below the gate oxide layer 432, and the distance from the sidewalls of the gate oxide layer 432 in the width direction to the sidewalls of the lightly doped drain regions 732 is 0.1-1 μm. The desired distance between the two lightly doped drain regions 732 is equal to the width of the gate layer 712 of the semiconductor device.
The source 912 and drain 912 of the MOS device are formed in the lightly doped drain region 732 by ion implantation. Referring to fig. 6 and 8B, in this step, ion implantation through the oxide layer 610 is also performed. The thickness of the oxide layer 610 is less than the thickness of the gate oxide layer 432, and after the foregoing steps, the thickness of the oxide layer 610 is gradually reduced, so the oxide layer 610 is not shown in fig. 9B. When forming the ultra shallow junction, source 912 and drain 912 may be formed in the lightly doped drain region 732 through the oxide layer 610, even at a lower energy.
In step 260, the source 912 and drain 912 are formed by implanting ions of the same type as the lightly doped drain region 732. In the present embodiment, the dopant ions of the lightly doped drain region 732 are P-type, and the ions implanted into the lightly doped drain region 732 in this step are also P-type. Thus, the semiconductor device shown in fig. 9B is a PMOS device.
Referring to fig. 9B, the gate oxide layer 432 does not cover the source 912 and the drain 912. That is, neither the source electrode 912 nor the drain electrode 912 formed at this step is covered by the gate oxide layer 432 and has a certain distance from the gate oxide layer 432. Thus, the process of ion implantation into the source 912 and the drain 912 is not hindered by the gate oxide layer 432.
Unlike the NMOS device shown in fig. 9A, the source 912 and the drain 912 in the PMOS device are each connected to their adjacent isolation structures 520. The width of the source 912 and drain 912 in the PMOS device is also greater than the width of the source 910 and drain 910 in the NMOS device.
In some embodiments, before forming the source and the drain in step 260, a sidewall 921 is further formed on both sides of the gate layer 712 to prevent the source and drain implants from being too close to the channel, which may cause the channel to be too short and even cause source and drain communication. The sidewall formation process may be a sidewall formation process familiar to those skilled in the art. The gate oxide layer 432 protrudes beyond the side walls 921 in the width direction.
After the source electrode 912 and the drain electrode 912 are formed, a process of forming a silicide (Salicide)913 on upper surfaces of the source electrode 912 and the drain electrode 912 and a silicide 922 on the gate electrode layer 712 is further included. This process is performed by a Salicide process familiar to those skilled in the art. As shown in fig. 9B, the silicide 913 formed on the upper surfaces of the source 912 and the drain 912 has a width smaller than that of the source 912 or the drain 912; the silicide 922 formed on the gate layer 712 has a width less than that of the gate layer 712. The silicide 913 formed on the upper surfaces of the source 912 and the drain 912 is connected to the adjacent isolation structure 520.
The semiconductor device shown in fig. 9C and 9D is formed in the logic device region 510 of the aforementioned semiconductor device. Taking fig. 9C as an example, the semiconductor device includes a logic P-well region 511 in a logic device region 510, and an isolation structure 520 is disposed at each end of the logic P-well region 511, so that an area between the two isolation structures 520 can form an independent device. After the logic device region 510 is subjected to the processing steps shown in fig. 8A and 8B, a source 930 and a drain 930 may be formed in the logic P well region 511 by means of ion implantation. The type of the implanted ions is opposite to the type of the doped ions in the substrate, i.e., the logic P well region 511. In the embodiment shown in fig. 9C, the type of implanted ions is N-type. Therefore, the semiconductor device shown in fig. 9C is an NMOS device.
Referring to fig. 9C, the oxide layer 610 formed on the upper surface of the logic device region 510 has a thickness that is inherently smaller than the gate oxide layer 431 on the upper surface of the high voltage device region 310. Therefore, as can be seen from fig. 7A and 9C, the thickness of gate layer 821 formed on oxide layer 610 is greater than the thickness of gate layer 711/712 formed on gate oxide layer 431. After the foregoing steps, the oxide layer 610 under the gate layer 821 still remains, and the remaining portion of the oxide layer 610 has been thinned to be negligible. Therefore, the width of the remaining oxide layer 610 is almost equal to the width of the gate layer 821.
Referring to fig. 9C, before forming the source 930 and the drain 930, forming spacers 940 on two sides of the oxide layer 610 and the gate layer 821 is further included to prevent the source-drain implant from being too close to the channel, which may result in too short channel and even source-drain connection. The process for forming the sidewall spacers 940 may use a sidewall formation process familiar to those skilled in the art.
In addition, in the embodiment shown in fig. 9C, a Halo L DD region 950 is further formed at the source terminal and the drain terminal near the channel, respectively, the Halo L DD region 950 has sidewalls located below the oxide layer 610, the upper surface of the sidewall is covered by the sidewall 940, and the width of the sidewall is smaller than the width of the source 930 and the drain 930, the Halo L DD region 950 helps to reduce the leakage current of the semiconductor device, reduce the thermo-electronic effect, and suppress the threshold voltage shift.
After the source and drain electrodes 930 and 930 are formed, a process of forming a silicide (Salicide)931 on upper surfaces of the source and drain electrodes 930 and forming a silicide 931 on the gate layer 821 is also included. This process is performed by a Salicide process familiar to those skilled in the art.
The step of forming the source and drain electrodes in the semiconductor device shown in fig. 9D is similar to the step of forming the source 930 and drain 930 in fig. 9C, except for the type of implanted ions. In the embodiment shown in fig. 9D, the semiconductor device includes a logic N-well region 512 in a logic device region 510. The ion type implanted into the source 932 and the drain 932 is P-type. Thus, the semiconductor device shown in fig. 9D is a PMOS device.
In the steps of the method for manufacturing a semiconductor device of the present invention, the process for removing the residual mask layer (e.g., silicon nitride) may be to clean the mask layer using a reagent (e.g., phosphoric acid) that reacts with the mask layer.
The present invention also includes a semiconductor device including a substrate, a logic device formed in the substrate, and a high voltage device. The high-voltage device comprises a grid structure positioned on a substrate, wherein the grid structure comprises a grid oxide layer, a grid layer positioned on the grid oxide layer and side walls positioned on two sides of the grid layer in the width direction, and the grid oxide layer protrudes out of the side walls in the width direction.
The overall structure of the semiconductor device is described below with reference to fig. 8B and fig. 9A to 9D. Among them, fig. 9A and 9B show the structures of two kinds of high-voltage devices in the semiconductor device, which are located in the high-voltage device region 310 of the semiconductor device shown in fig. 8B. Fig. 9C and 9D show the structures of two kinds of logic devices in the semiconductor device, which are located in the logic device region 510 of the semiconductor device shown in fig. 8B. Fig. 8B is merely an illustration, and the semiconductor device of the present invention may include a plurality of high voltage devices and a plurality of logic devices.
In some embodiments, the semiconductor device has a high voltage well and a low voltage well in the substrate. Referring to fig. 8B, the hvw well includes hvp-well region 311 and hvn-well region 312, and the hvw well includes logic P-well region 511 and logic N-well region 512. The two high-voltage devices shown in fig. 9A and 9B are located in hvpwell region 311 and hvnwell region 312, respectively; the two logic devices shown in fig. 9C and 9D are located in logic P-well region 511 and logic N-well region 512, respectively.
Next, a high-voltage device of a semiconductor device of the present invention will be described by taking fig. 9A as an example. The high voltage device includes a gate structure located on a substrate. The substrate refers to the substrate 301 of the semiconductor device shown in fig. 3. Further, the substrate refers to a substrate in the high-voltage device region 310 on the substrate 301 shown in fig. 3. Further, in fig. 9A, the substrate is referred to as a hvpwell region 311. As mentioned above, in some embodiments, since the substrate 301 is a P-type single crystal silicon substrate doped with P-type dopant ions, the hvnw region 311 corresponds to the region of the substrate 301 except the hvnw region 312.
Referring to fig. 9A, the gate structure of the high voltage device includes a gate oxide layer 431, a gate layer 711 located above the gate oxide layer 431, and sidewalls 920 located on two sides of the gate layer 711 in a width direction, where the gate oxide layer 431 protrudes from the sidewalls 920 in the width direction, and a lightly doped drain region 731 is formed in the substrate at a side of the gate oxide layer 431.
In some embodiments, the gate oxide 431 has a thickness of 10-50 nm.
In some embodiments, as shown in fig. 9A, the high voltage device further includes a source 910, a drain 910, and a lightly doped drain region 731. The lightly doped drain region 731 is located in the substrate at the side of the gate structure, and the source 910 and the drain 910 are located in the lightly doped drain region 731.
In some embodiments, as shown in fig. 9A, the lightly doped drain region 731 has a sidewall below the gate oxide layer 431, and the sidewall of the gate oxide layer 431 in the width direction is 0.1-1 μm away from the sidewall of the lightly doped drain region 731.
Referring to fig. 8B, the semiconductor device of the present invention further has an isolation structure 520 between the logic device and the high voltage device.
It is to be understood that the semiconductor device of the present invention can be manufactured according to a method for manufacturing a semiconductor device of the present invention. Therefore, the description about the semiconductor device in the method of manufacturing a semiconductor device of the present invention is applicable to the explanation of the structure and function of the semiconductor device of the present invention.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims (8)

1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, and the substrate is provided with a high-voltage device area;
forming a gate oxide layer on the high-voltage device region;
defining a logic device region in the substrate;
forming oxide layers on the surfaces of the high-voltage device area and the logic device area, wherein the thickness of the oxide layers is smaller than that of the gate oxide layers;
sequentially depositing a grid layer and a mask layer on the upper surfaces of the high-voltage device area and the logic device area;
when the logic device area is covered with the gate layer and the mask layer, the gate layer is formed on the gate oxide layer of the high-voltage device area, and a lightly doped drain area is formed in the substrate on the side edge of the gate oxide layer; and
source and drain-are formed in lightly doped drain regions under the oxide layer.
2. The method of claim 1, wherein said gate oxide layer partially covers said lightly doped region after forming a lightly doped drain region in said substrate laterally of said gate oxide layer.
3. The method of claim 2, wherein the lightly doped drain region has a sidewall below the gate oxide layer, the sidewall in the width direction of the gate oxide layer being 0.1-1 μm from the sidewall of the lightly doped drain region.
4. The method of claim 1, further comprising forming an isolation structure that isolates the high voltage device region from a logic device region after defining the logic device region in the substrate.
5. The method of claim 1, wherein in the step of forming an oxide layer on the surfaces of the high voltage device region and the logic device region, the oxide layer does not cover the gate oxide layer.
6. The method of claim 1, wherein forming a source and a drain in a lightly doped drain region below the oxide layer comprises: ion implantation is performed through the oxide layer.
7. The method of claim 1, wherein the gate oxide layer does not cover the source and drain electrodes when the source and drain electrodes are formed.
8. The method of claim 1, wherein the gate oxide layer has a thickness of 10-50 nm.
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