JPH11111979A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which can be driven at a high speed, while the occurrence of a short channel effect is suppressed even if the device is made finer. SOLUTION: Since a semiconductor device has a structure such that a source region 12 and a drain region 13 are bent toward a gate electrode 9, with the regions 12 and 13 being partially protruded, the regions of the source and drain regions 12 and 13 facing the gate electrode 9 become smaller, and the parasitic capacitances between the gate electrode 9 and the source and the drain regions 12 and 13 can be reduced. In addition, since the impurity concentrations in the protruded sections are lower, no wide space-charge region is formed around the protruded sections. Therefore, the occurrence of a short-channel effect can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOS transistor capable of operating at high speed and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the recent increase in the degree of integration of semiconductor integrated circuits, miniaturization of elements constituting the circuits has been progressing. Among these elements, the MOSFET (Metal-Oxide-Semico
An nductor Field Effect Transistor (MOS field effect transistor) performs switching by applying a voltage to a gate electrode 54 formed on a gate insulating film 53, and using a change in conduction of a channel region 55 thereunder. This is one of the basic elements of a semiconductor integrated circuit used as an element. However, when the channel length is shortened with miniaturization, a phenomenon called a short channel effect appears and becomes a problem.

A semiconductor substrate 50 and a source region 51 of a MOSFET
A space charge region 56 is formed near the PN junction boundary of the drain region 52 by a diffusion potential, and when a voltage is applied to the drain region 52, the region farther from the gate electrode 54 and the deeper region is more drain than the gate voltage. Be more strongly affected by voltage. Therefore, as shown in FIG. 5A, the space charge region 56 is enlarged by applying a drain voltage to the PN junction between the semiconductor substrate 50 and the drain region 52. Due to this space charge amount region 56, when the channel length is shortened with miniaturization, FIG.
As shown in FIG. 5, even if the voltage of the gate electrode 54 is set to 0 V in order to turn off the transistor, that is, the state where no current flows, when the voltage is applied to the drain region, the source region 51 and the drain region 52 Space charge region 56
Are in contact with each other and the drain current leaks out, a phenomenon called so-called punch-through appears. Such a phenomenon that occurs as a result of shortening the channel length is collectively called a short channel effect.

In order to avoid this short channel effect, various devices such as an LDD (Lightly Doped Drain) structure shown in FIG. 6 and an SPDD (Solid Phase Diffused Drain) structure shown in FIG. 7 have been proposed. The LDD structure absorbs part of the electric field by providing a low-concentration region 57 having a low impurity concentration in a shallow portion near the channel region 55 of the source region 51 and the drain region 52, thereby absorbing the channel region 55.
This is a structure for suppressing the space charge region extending to the side. However, the electric resistance of the low-concentration region 57 is high, causing a reduction in current driving force. In the SPDD structure, a region 58 having a high impurity concentration is formed in a shallower region by forming a low-concentration region of the LDD structure using solid-phase diffusion. The SPDD structure can form source and drain regions having lower resistance than the conventional LDD structure, but has a problem that it is difficult to sufficiently reduce the resistance when the gate length is less than 0.2 mm. In addition, S4D (Silicided Silicon-Sidewall Source
and Drain) structure are disclosed in JP-A-8-78683 and
95 Symposium on VLSI Technology Digest of Technica
l It is disclosed on pages 11-12 of Papers. S4D
As shown in FIG. 8, the structure is such that the side wall insulating film conventionally provided on the side surface of the gate electrode is used as a side wall conductive film 59, and the side wall conductive film 59 is also used as a source region and a drain region, thereby forming a conductive path. The current driving force is increased by securing a wide sectional area and keeping the resistance low.

[0005]

SUMMARY OF THE INVENTION However, the conventional
In the S4D structure, the side surface of the gate electrode 54 is
And the drain region 52 is covered, and the sidewall insulating film 60 separating the gate electrode 54 and the drain region 52 is a silicon nitride film having a high selectivity with respect to a silicon oxide film during etching. A large parasitic capacitance was generated between the drain region 54 and the drain region 52 and the source region 51, which hindered high-speed driving. Further, in the case of using the silicide structure for the gate electrode 54, the source region 51, and the drain region 52 in order to reduce the layer resistance, the S4D structure requires a separate silicide process, and the manufacturing process is complicated.

As described above, the present invention provides a semiconductor device which can be driven at a high speed while suppressing the short channel effect even when the MOSFET is miniaturized, and an easy manufacturing method thereof. Aim.

[0007]

According to the first and second aspects of the present invention, as shown in FIG. 1, the source region 12 and the drain region 13 are bent toward the gate electrode 7 and partially project. Therefore, the area of the source region 12 and the drain region 13 facing the gate electrode 7 is small, and the parasitic capacitance between the gate electrode 7 and the source region 12 and the drain region 13 can be reduced.

According to the third aspect of the present invention, the short channel effect can be prevented because the impurity concentration of the projection is low and the space charge region is not formed widely around the projection. According to the fourth aspect of the invention, since the impurity concentration of the portion of the source region 12 and the drain region 13 outside the protrusion is high, the layer resistance of the source region and the drain region can be reduced.

According to the fifth aspect of the present invention, since the end of the gate electrode is inclined, the parasitic capacitance between the source region and the drain region can be reduced. In the invention described in claim 6, since the source region, the drain region, and the gate electrode are made of silicide, the respective layer resistances can be reduced. The invention according to claims 7 and 8 is a method for manufacturing such a semiconductor device.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIG. A p-type source region 12 and a p-type drain region 13 are formed on the n-type semiconductor substrate 1 at predetermined intervals, and the source region and the drain region have bent portions 1 on side surfaces facing each other.
2a and 13a, projecting upward at an angle of approximately 45 degrees. A region of the semiconductor substrate 1 sandwiched between the tips of the protruding protrusions 12b and 13b is a channel region 14, and a gate electrode 7 is formed on the channel region 14 via a gate insulating film 15. Gate electrode 7,
The surfaces of the source region 12 and the drain region 13 have a so-called salicide structure in which a silicide film made of a refractory metal such as titanium is formed. The impurity concentrations of the source region 12 and the drain region 13 are determined by the protrusions 12b and 13b.
5E16atoms / cm3 and the flat part 12 outside the projection
In c and 13c, it is high and is 5E17 atoms / cm3.

The impurity concentration of the projections 12b and 13b is not limited to the above concentration. However, if the impurity concentration is too low, the electric resistance increases and the current driving force of the element decreases, so that the short channel effect does not occur. Increase in range. The bent portions 12a and 13a are flat portions 12c having a high impurity concentration.
And 13c and the projections 12b and 13b are connected to each other. For high-speed driving, the bent portions 12a and 13a have a high impurity concentration, and the formation region thereof is formed on the substrate so that the short channel effect does not appear. It is desirable to be shallow from the surface.

Further, in order to make the structure more resistant to the short channel effect, the impurity concentration of the bent portion 13a is desirably an intermediate value between the protrusion 13b and the flat portion 13c. According to the semiconductor device of the present embodiment, since the projections 12b and 13b have an angle of about 45 degrees with respect to the semiconductor substrate, the channel length is reduced while maintaining the distance between the source region 12 and the drain region 13. In addition, since the end of the gate electrode 7 is inclined, the distance between the gate electrode 7 and the source region 12 and the drain region 13 is larger than in the related art, so that the parasitic capacitance can be reduced. Further, the portions 12b and 13b where the source region 12 and the drain region 13 protrude toward the gate electrode 7 have a low impurity concentration, so that a short channel effect can be prevented.

Although the angle of the projection of the present invention is not limited to 45 degrees, if the angle is too large, it will hinder the miniaturization of the device. If the angle is too small, the distance between the source region 12 and the drain region 13 will be small. Since the distance is shortened, the short channel effect becomes apparent. Therefore, the angle of the protrusion of the present invention is desirably 40 to 90 degrees. The thickness of the protrusions 12b and 13b is thinner than the flat portions 12c and 13c, but may be the same. That is, the protrusions 12b and 13b have the same thickness from the flat portion toward the gate electrode. Even so, it is assumed that the source and drain regions on the gate electrode side of the bent portion are projections.
However, the thinner the projection, the shorter the channel effect,
Needless to say, it is desirable from the viewpoint of miniaturization.
Further, the source and drain regions may bend from the flat portion to the gate electrode, and may be gradually bent to the gate electrode side end. In this case, the boundary between the bent portion and the protrusion is not clear. However, for convenience, the upper surface of the flat portion separates the gate and the source, the lower portion is referred to as a bent portion, and the upper portion is referred to as a protrusion.

A method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described below in accordance with, for example, a 0.3 mm design rule. Step 1: As shown in FIG. 2 (a), for example, the surface of the n-type semiconductor substrate 1 is oxidized and the first silicon oxide film 2 is
0 ° is formed. Next, CVD (Chemical Vapor Depositio
A polysilicon film 3 is formed to a thickness of 2000 ° using the n) method, and BF2 is ion-implanted at 5E15 atoms / cm2 to impart conductivity. Next, the second silicon oxide films 4 and 1000 of 100 ° are formed by LPCVD (Low pressure CVD).
The silicon nitride film 5 is formed in order. The second silicon oxide film 4 has the purpose of improving the contact between the silicon nitride film 5 and the polysilicon film 3 and absorbing the stress applied from above, and may be formed as necessary.

Step 2: As shown in FIG. 2 (b), a silicon nitride film 5, a silicon oxide film 4, a polysilicon film 3 in predetermined regions are formed using a photoresist (not shown) as a mask.
Are sequentially etched by switching the etching gas. At this time, the width of the remaining portion is 0.5 mm. Step 3: As shown in FIG.
The semiconductor substrate 1 and the side surfaces of the polysilicon film 3 are oxidized by pyrogenic oxidation at 0 ° C. for 60 minutes to form a thick oxide film 6 and the remaining polysilicon film 3 becomes the gate electrode 7. By performing the pyrogenic oxidation, the side surface of the polysilicon film 3 can be effectively oxidized, and the oxidized region cuts into the upper and lower ends of the polysilicon film 3 to form a bird's beak. Is formed. As a result, the capacitive coupling with the projections of the source and drain regions to be formed later can be further reduced. Here, the thick oxide film 6
Is 2000 mm, the gate length of this embodiment is about 0.3 mm. The lower surface of the thick oxide film 6 has a gentle curved surface, and a curved portion and a protruding portion are later formed by the curved surface.

Step 4: As shown in FIG. 2 (d), for example, BF2 ions are implanted at an energy of 260 keV and a dose of 6E13ato.
At a rate of ms / cm 2, ions are obliquely implanted at an angle of, for example, 45 degrees to the left and right with respect to the normal line of the semiconductor substrate 1 to form the low concentration layer 8. As a result, impurity ions can be implanted into the lower portion of the silicon nitride film 5 which cannot be implanted only by implanting substantially vertically, and these portions become bent portions and projections of the source region and the drain region. here,
According to the energy of 260 keV, since the depth of the peak concentration of the implanted ions is about 200 °, the thickness of the protrusion is 8 μm.
00Å.

Step 5: As shown in FIG. 3 (a), BF2
Ion energy 320 keV, implantation dose 2E15atoms / cm2
Then, ions are implanted almost vertically to form the middle concentration layer 9. Here, the term “substantially perpendicular” means that ions are implanted at an angle of, for example, about 7 degrees with respect to the normal to the semiconductor substrate 1 in order to prevent ions from entering deeply due to channeling with the silicon lattice.

Step 6: As shown in FIG. 3B, the entire surface is etched back to expose the middle concentration layer 9. Next, BF2 ions are implanted at an energy of 30 keV and an injection amount of 1E16atoms.
Ion implantation is performed almost vertically at / cm 2 to form a high concentration layer 10. The implantation energy in this step is 30 keV, which is very low. Therefore, high-concentration implanted ions are not implanted deeply in the semiconductor substrate 1, and the high-concentration layer 10 is formed near the surface of the substrate. Next, the layers 7, 8, 9, and 10 into which the impurities are implanted are activated by lamp annealing at 1000 ° C. for 30 seconds.

Step 7: As shown in FIG. 3C, the silicon nitride film 5 is removed, the silicon oxide film is lightly etched by 100 °, the second silicon oxide film 4 is removed, and the gate electrode 7 is removed. To expose. Next, a Ti film is deposited at 500 ° C. by a sputtering method, and 600 ° C. in a nitrogen atmosphere.
Perform a silicide reaction at ~ 700 ° C for 30 minutes. Thus, a Ti silicide film 11 is formed on the surfaces of the source, drain and gate electrodes. Next, unreacted Ti and TiN deposited on the silicon oxide film are removed with a mixed solution of sulfuric acid and hydrogen peroxide to form a salicide structure. Here, in the manufacturing process of the S4D structure, the gate electrode, the source,
Although the drain region and the drain region are separately silicided, the present invention can reduce the number of steps because a salicide structure in which the gate electrode, the source, and the drain region are formed in the same manner can be used. As described above, the MOSFET of the present embodiment is formed.

In this embodiment, polysilicon is exemplified as the material of the gate electrode. However, amorphous silicon may be used, or amorphous silicon may be crystallized. In the present embodiment, the order of the steps is not limited to the present embodiment. For example, although the step of obliquely introducing impurity ions is referred to as step 4, the step of substantially vertically implanting step 5 is replaced with the step of performing substantially perpendicular implantation. May be. Also, the third
As shown in FIG. 4B, the entire surface may be etched and then ion-implanted to form layers 7, 8, and 10. In this case, in order to prevent the short channel effect, it is necessary to reduce the implantation depth by keeping the ion implantation energy of the low concentration layer 8 at 140 keV and the ion implantation energy of the middle concentration layer 9 at about 80 keV. is there.

In this embodiment, BF2 is described as an ion to be implanted. However, phosphorus may be used when the substrate is p-type. In the present embodiment, the ion implantation has been described as an example of the impurity implantation method. However, after exposing the layer to be implanted, implantation may be performed using solid-phase diffusion, and the layer may be covered again with an insulating film.

In all of the embodiments described above, titanium has been described as an example of the metal silicide, but other high melting point metals such as tungsten may be used. In all the embodiments described above, since the concentration of implanted ions is diffused by heat treatment after implantation such as annealing, it goes without saying that the boundary is unclear.

[0023]

As described in detail above, claims 1 and 2
According to the invention described in (1), since the source and drain regions are bent toward the gate electrode and partially protruded, the areas of the source and drain regions facing the gate electrode are small, and the gate electrode and the source region and The parasitic capacitance between the drain region and the drain region can be reduced, and the element can be driven at high speed.

According to the third aspect of the present invention, since the space concentration region is not formed widely around the protrusion because the impurity concentration of the protrusion is low, the short channel effect can be prevented and the element can be miniaturized. According to the fourth aspect of the present invention, since the impurity concentration of the portion of the source region 12 and the drain region 13 outside the projection is high, the layer resistance of the source region and the drain region is low, and the element is driven at a low voltage and at a high speed. it can.

According to the fifth aspect of the present invention, since the end of the gate electrode is inclined, the parasitic capacitance between the source region and the drain region can be reduced, so that the element can be driven at high speed. . According to the sixth aspect of the invention, since the source region, the drain region, and the gate electrode are made of silicide, the respective layer resistances can be reduced, and the element can be driven at a low voltage and at a high speed.

The invention according to claims 7 and 8 is a method for manufacturing such a semiconductor device. As described above, according to the present invention, even if the channel length is reduced with miniaturization, the short channel effect is effectively suppressed, and the parasitic capacitance between the source / drain region and the gate electrode is reduced. It is possible to provide a semiconductor device which can be suppressed and can be driven at high speed, and an easy manufacturing method thereof.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing method according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a manufacturing method according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the structure of a conventional MOSFET.

FIG. 5 is a cross-sectional view illustrating a short channel effect.

FIG. 6 is a sectional view showing a structure of a conventional LDD type MOSFET.

FIG. 7 is a sectional view showing the structure of a conventional SPDD type MOSFET.

FIG. 8 is a sectional view showing the structure of a conventional S4D type MOSFET.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 301G

Claims (8)

[Claims] 1. A semiconductor substrate of a first conductivity type, a source region and a drain region of a second conductivity type formed at a predetermined interval on the semiconductor substrate, and between the source region and the drain region. A channel region formed, and a gate electrode formed above the channel region with an insulating film interposed therebetween, and ends of the source region and the drain region adjacent to the channel region are bent toward the gate electrode. ,
A semiconductor device provided with a projection protruding toward the gate electrode. 2. The semiconductor device according to claim 1, wherein the inclination bent toward the gate electrode is 45 to 90 degrees with respect to the semiconductor substrate. 3. The semiconductor device according to claim 2, wherein the impurity concentration of the source region and the drain region is low at the bent portion and / or the protrusion. 4. The semiconductor device according to claim 3, wherein the source region and the drain region include a region having a high impurity concentration on a side of the bent portion opposite to a channel region. 5. The semiconductor according to claim 4, wherein an end of the gate electrode located above a contact point between the channel region and the protrusion is inclined with respect to the semiconductor substrate. apparatus. 6. The semiconductor device according to claim 5, wherein a silicide film is formed on surfaces of said source region and said drain region and a surface of said gate electrode. 7. A step of sequentially forming a silicon oxide film, a conductive film of a second conductivity type and a silicon nitride film on a semiconductor substrate of a first conductivity type, and patterning predetermined regions of the silicon nitride film and the silicon film. Forming a thick oxide film by oxidizing a surface of the semiconductor substrate and side surfaces of the conductive film using the silicon nitride film as a mask; performing ion implantation obliquely using the silicon nitride film as a mask to form the thick oxide film; Implanting impurities near the boundary between the semiconductor substrate and the semiconductor substrate; performing ion implantation substantially perpendicularly; implanting impurities into a portion near the boundary between the thick oxide film and the semiconductor substrate to form a source region and a drain region; Forming a semiconductor device, and removing the silicon nitride film. 8. A step of sequentially forming a silicon oxide film, a conductive film of a second conductive type, and a silicon nitride film on a semiconductor substrate of a first conductive type, and patterning predetermined regions of the silicon nitride film and the silicon film. Forming a thick oxide film by oxidizing a surface of the semiconductor substrate and side surfaces of the conductive film using the silicon nitride film as a mask; performing ion implantation obliquely using the silicon nitride film as a mask to form the thick oxide film; Implanting impurities near the boundary between the semiconductor substrate and the semiconductor substrate; performing ion implantation substantially perpendicularly; implanting impurities into a portion near the boundary between the thick oxide film and the semiconductor substrate to form a source region and a drain region; And exposing the region into which the impurities are implanted by etching the conductive film and the thick oxide film using the silicon nitride film as a mask, Removing the silicon nitride film, and forming a refractory metal film on the entire surface, performing a silicide reaction, and forming a silicide film on the surfaces of the source region, the drain region, and the gate electrode. A method for manufacturing a semiconductor device, comprising: